arch/alpha/ev5.cc

   1 /* $Id$ */
   2
   3 #include "arch/alpha/alpha_memory.hh"
   4 #include "arch/alpha/isa_traits.hh"
   5 #include "arch/alpha/osfpal.hh"
   6 #include "base/kgdb.h"
   7 #include "base/remote_gdb.hh"
   8 #include "base/stats/events.hh"
   9 #include "cpu/exec_context.hh"
  10 #include "cpu/fast_cpu/fast_cpu.hh"
  11 #include "sim/debug.hh"
  12 #include "sim/sim_events.hh"
  13
  14 #ifdef FULL_SYSTEM
  15
  16 #ifndef SYSTEM_EV5
  17 #error This code is only valid for EV5 systems
  18 #endif
  19
  20 ////////////////////////////////////////////////////////////////////////
  21 //
  22 //
  23 //
  24 void
  25 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  26 {
  27     if (regs->pal_shadow == use_shadow)
  28         panic("swap_palshadow: wrong PAL shadow state");
  29
  30     regs->pal_shadow = use_shadow;
  31
  32     for (int i = 0; i < NumIntRegs; i++) {
  33         if (reg_redir[i]) {
  34             IntReg temp = regs->intRegFile[i];
  35             regs->intRegFile[i] = regs->palregs[i];
  36             regs->palregs[i] = temp;
  37         }
  38     }
  39 }
  40
  41 ////////////////////////////////////////////////////////////////////////
  42 //
  43 //  Machine dependent functions
  44 //
  45 void
  46 AlphaISA::initCPU(RegFile *regs)
  47 {
  48     initIPRs(regs);
  49     // CPU comes up with PAL regs enabled
  50     swap_palshadow(regs, true);
  51
  52     regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
  53     regs->npc = regs->pc + sizeof(MachInst);
  54 }
  55
  56 ////////////////////////////////////////////////////////////////////////
  57 //
  58 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
  59 //
  60 Addr
  61 AlphaISA::fault_addr[Num_Faults] = {
  62     0x0000,     /* No_Fault */
  63     0x0001,     /* Reset_Fault */
  64     0x0401,     /* Machine_Check_Fault */
  65     0x0501,     /* Arithmetic_Fault */
  66     0x0101,     /* Interrupt_Fault */
  67     0x0201,     /* Ndtb_Miss_Fault */
  68     0x0281,     /* Pdtb_Miss_Fault */
  69     0x0301,     /* Alignment_Fault */
  70     0x0381,     /* DTB_Fault_Fault */
  71     0x0381,     /* DTB_Acv_Fault */
  72     0x0181,     /* ITB_Miss_Fault */
  73     0x0181,     /* ITB_Fault_Fault */
  74     0x0081,     /* ITB_Acv_Fault */
  75     0x0481,     /* Unimplemented_Opcode_Fault */
  76     0x0581,     /* Fen_Fault */
  77     0x2001,     /* Pal_Fault */
  78     0x0501,     /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
  79 };
  80
  81 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  82     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  83     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  84     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  85     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  86
  87 ////////////////////////////////////////////////////////////////////////
  88 //
  89 //
  90 //
  91 void
  92 AlphaISA::initIPRs(RegFile *regs)
  93 {
  94     uint64_t *ipr = regs->ipr;
  95
  96     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
  97     ipr[IPR_PAL_BASE] = PAL_BASE;
  98     ipr[IPR_MCSR] = 0x6;
  99 }
 100
 101
 102 template <class XC>
 103 void
 104 AlphaISA::processInterrupts(XC *xc)
 105 {
 106     //Check if there are any outstanding interrupts
 107     //Handle the interrupts
 108     int ipl = 0;
 109     int summary = 0;
 110     IntReg *ipr = xc->getIprPtr();
 111
 112     check_interrupts = 0;
 113
 114     if (ipr[IPR_ASTRR])
 115         panic("asynchronous traps not implemented\n");
 116
 117     if (ipr[IPR_SIRR]) {
 118         for (int i = INTLEVEL_SOFTWARE_MIN;
 119              i < INTLEVEL_SOFTWARE_MAX; i++) {
 120             if (ipr[IPR_SIRR] & (ULL(1) << i)) {
 121                 // See table 4-19 of the 21164 hardware reference
 122                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 123                 summary |= (ULL(1) << i);
 124             }
 125         }
 126     }
 127
 128     uint64_t interrupts = xc->intr_status();
 129
 130     if (interrupts) {
 131         for (int i = INTLEVEL_EXTERNAL_MIN;
 132              i < INTLEVEL_EXTERNAL_MAX; i++) {
 133             if (interrupts & (ULL(1) << i)) {
 134                 // See table 4-19 of the 21164 hardware reference
 135                 ipl = i;
 136                 summary |= (ULL(1) << i);
 137             }
 138         }
 139     }
 140
 141     if (ipl && ipl > ipr[IPR_IPLR]) {
 142         ipr[IPR_ISR] = summary;
 143         ipr[IPR_INTID] = ipl;
 144         xc->trap(Interrupt_Fault);
 145         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 146                 ipr[IPR_IPLR], ipl, summary);
 147     }
 148
 149 }
 150
 151 template <class XC>
 152 void
 153 AlphaISA::zeroRegisters(XC *xc)
 154 {
 155     // Insure ISA semantics
 156     // (no longer very clean due to the change in setIntReg() in the
 157     // cpu model.  Consider changing later.)
 158     xc->xc->setIntReg(ZeroReg, 0);
 159     xc->xc->setFloatRegDouble(ZeroReg, 0.0);
 160 }
 161
 162 void
 163 ExecContext::ev5_trap(Fault fault)
 164 {
 165     DPRINTF(Fault, "Fault %s\n", FaultName(fault));
 166     Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
 167
 168     assert(!misspeculating());
 169     kernelStats.fault(fault);
 170
 171     if (fault == Arithmetic_Fault)
 172         panic("Arithmetic traps are unimplemented!");
 173
 174     AlphaISA::InternalProcReg *ipr = regs.ipr;
 175
 176     // exception restart address
 177     if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
 178         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 179
 180     if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
 181         fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
 182         // traps...  skip faulting instruction
 183         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 184     }
 185
 186     if (!PC_PAL(regs.pc))
 187         AlphaISA::swap_palshadow(&regs, true);
 188
 189     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
 190     regs.npc = regs.pc + sizeof(MachInst);
 191 }
 192
 193
 194 void
 195 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 196 {
 197     InternalProcReg *ipr = regs->ipr;
 198     bool use_pc = (fault == No_Fault);
 199
 200     if (fault == Arithmetic_Fault)
 201         panic("arithmetic faults NYI...");
 202
 203     // compute exception restart address
 204     if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
 205         // traps...  skip faulting instruction
 206         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 207     } else {
 208         // fault, post fault at excepting instruction
 209         ipr[IPR_EXC_ADDR] = regs->pc;
 210     }
 211
 212     // jump to expection address (PAL PC bit set here as well...)
 213     if (!use_pc)
 214         regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
 215     else
 216         regs->npc = ipr[IPR_PAL_BASE] + pc;
 217
 218     // that's it! (orders of magnitude less painful than x86)
 219 }
 220
 221 bool AlphaISA::check_interrupts = false;
 222
 223 Fault
 224 ExecContext::hwrei()
 225 {
 226     uint64_t *ipr = regs.ipr;
 227
 228     if (!PC_PAL(regs.pc))
 229         return Unimplemented_Opcode_Fault;
 230
 231     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 232
 233     if (!misspeculating()) {
 234         kernelStats.hwrei();
 235
 236         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 237             AlphaISA::swap_palshadow(&regs, false);
 238
 239         AlphaISA::check_interrupts = true;
 240     }
 241
 242     // FIXME: XXX check for interrupts? XXX
 243     return No_Fault;
 244 }
 245
 246 uint64_t
 247 ExecContext::readIpr(int idx, Fault &fault)
 248 {
 249     uint64_t *ipr = regs.ipr;
 250     uint64_t retval = 0;        // return value, default 0
 251
 252     switch (idx) {
 253       case AlphaISA::IPR_PALtemp0:
 254       case AlphaISA::IPR_PALtemp1:
 255       case AlphaISA::IPR_PALtemp2:
 256       case AlphaISA::IPR_PALtemp3:
 257       case AlphaISA::IPR_PALtemp4:
 258       case AlphaISA::IPR_PALtemp5:
 259       case AlphaISA::IPR_PALtemp6:
 260       case AlphaISA::IPR_PALtemp7:
 261       case AlphaISA::IPR_PALtemp8:
 262       case AlphaISA::IPR_PALtemp9:
 263       case AlphaISA::IPR_PALtemp10:
 264       case AlphaISA::IPR_PALtemp11:
 265       case AlphaISA::IPR_PALtemp12:
 266       case AlphaISA::IPR_PALtemp13:
 267       case AlphaISA::IPR_PALtemp14:
 268       case AlphaISA::IPR_PALtemp15:
 269       case AlphaISA::IPR_PALtemp16:
 270       case AlphaISA::IPR_PALtemp17:
 271       case AlphaISA::IPR_PALtemp18:
 272       case AlphaISA::IPR_PALtemp19:
 273       case AlphaISA::IPR_PALtemp20:
 274       case AlphaISA::IPR_PALtemp21:
 275       case AlphaISA::IPR_PALtemp22:
 276       case AlphaISA::IPR_PALtemp23:
 277       case AlphaISA::IPR_PAL_BASE:
 278
 279       case AlphaISA::IPR_IVPTBR:
 280       case AlphaISA::IPR_DC_MODE:
 281       case AlphaISA::IPR_MAF_MODE:
 282       case AlphaISA::IPR_ISR:
 283       case AlphaISA::IPR_EXC_ADDR:
 284       case AlphaISA::IPR_IC_PERR_STAT:
 285       case AlphaISA::IPR_DC_PERR_STAT:
 286       case AlphaISA::IPR_MCSR:
 287       case AlphaISA::IPR_ASTRR:
 288       case AlphaISA::IPR_ASTER:
 289       case AlphaISA::IPR_SIRR:
 290       case AlphaISA::IPR_ICSR:
 291       case AlphaISA::IPR_ICM:
 292       case AlphaISA::IPR_DTB_CM:
 293       case AlphaISA::IPR_IPLR:
 294       case AlphaISA::IPR_INTID:
 295       case AlphaISA::IPR_PMCTR:
 296         // no side-effect
 297         retval = ipr[idx];
 298         break;
 299
 300       case AlphaISA::IPR_CC:
 301         retval |= ipr[idx] & ULL(0xffffffff00000000);
 302         retval |= curTick  & ULL(0x00000000ffffffff);
 303         break;
 304
 305       case AlphaISA::IPR_VA:
 306         retval = ipr[idx];
 307         break;
 308
 309       case AlphaISA::IPR_VA_FORM:
 310       case AlphaISA::IPR_MM_STAT:
 311       case AlphaISA::IPR_IFAULT_VA_FORM:
 312       case AlphaISA::IPR_EXC_MASK:
 313       case AlphaISA::IPR_EXC_SUM:
 314         retval = ipr[idx];
 315         break;
 316
 317       case AlphaISA::IPR_DTB_PTE:
 318         {
 319             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 320
 321             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 322             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 323             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 324             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 325             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 326             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 327             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 328         }
 329         break;
 330
 331         // write only registers
 332       case AlphaISA::IPR_HWINT_CLR:
 333       case AlphaISA::IPR_SL_XMIT:
 334       case AlphaISA::IPR_DC_FLUSH:
 335       case AlphaISA::IPR_IC_FLUSH:
 336       case AlphaISA::IPR_ALT_MODE:
 337       case AlphaISA::IPR_DTB_IA:
 338       case AlphaISA::IPR_DTB_IAP:
 339       case AlphaISA::IPR_ITB_IA:
 340       case AlphaISA::IPR_ITB_IAP:
 341         fault = Unimplemented_Opcode_Fault;
 342         break;
 343
 344       default:
 345         // invalid IPR
 346         fault = Unimplemented_Opcode_Fault;
 347         break;
 348     }
 349
 350     return retval;
 351 }
 352
 353 #ifdef DEBUG
 354 // Cause the simulator to break when changing to the following IPL
 355 int break_ipl = -1;
 356 #endif
 357
 358 Fault
 359 ExecContext::setIpr(int idx, uint64_t val)
 360 {
 361     uint64_t *ipr = regs.ipr;
 362     uint64_t old;
 363
 364     if (misspeculating())
 365         return No_Fault;
 366
 367     switch (idx) {
 368       case AlphaISA::IPR_PALtemp0:
 369       case AlphaISA::IPR_PALtemp1:
 370       case AlphaISA::IPR_PALtemp2:
 371       case AlphaISA::IPR_PALtemp3:
 372       case AlphaISA::IPR_PALtemp4:
 373       case AlphaISA::IPR_PALtemp5:
 374       case AlphaISA::IPR_PALtemp6:
 375       case AlphaISA::IPR_PALtemp7:
 376       case AlphaISA::IPR_PALtemp8:
 377       case AlphaISA::IPR_PALtemp9:
 378       case AlphaISA::IPR_PALtemp10:
 379       case AlphaISA::IPR_PALtemp11:
 380       case AlphaISA::IPR_PALtemp12:
 381       case AlphaISA::IPR_PALtemp13:
 382       case AlphaISA::IPR_PALtemp14:
 383       case AlphaISA::IPR_PALtemp15:
 384       case AlphaISA::IPR_PALtemp16:
 385       case AlphaISA::IPR_PALtemp17:
 386       case AlphaISA::IPR_PALtemp18:
 387       case AlphaISA::IPR_PALtemp19:
 388       case AlphaISA::IPR_PALtemp20:
 389       case AlphaISA::IPR_PALtemp21:
 390       case AlphaISA::IPR_PALtemp22:
 391       case AlphaISA::IPR_PAL_BASE:
 392       case AlphaISA::IPR_IC_PERR_STAT:
 393       case AlphaISA::IPR_DC_PERR_STAT:
 394       case AlphaISA::IPR_PMCTR:
 395         // write entire quad w/ no side-effect
 396         ipr[idx] = val;
 397         break;
 398
 399       case AlphaISA::IPR_CC_CTL:
 400         // This IPR resets the cycle counter.  We assume this only
 401         // happens once... let's verify that.
 402         assert(ipr[idx] == 0);
 403         ipr[idx] = 1;
 404         break;
 405
 406       case AlphaISA::IPR_CC:
 407         // This IPR only writes the upper 64 bits.  It's ok to write
 408         // all 64 here since we mask out the lower 32 in rpcc (see
 409         // isa_desc).
 410         ipr[idx] = val;
 411         break;
 412
 413       case AlphaISA::IPR_PALtemp23:
 414         // write entire quad w/ no side-effect
 415         old = ipr[idx];
 416         ipr[idx] = val;
 417         kernelStats.context(old, val);
 418         break;
 419
 420       case AlphaISA::IPR_DTB_PTE:
 421         // write entire quad w/ no side-effect, tag is forthcoming
 422         ipr[idx] = val;
 423         break;
 424
 425       case AlphaISA::IPR_EXC_ADDR:
 426         // second least significant bit in PC is always zero
 427         ipr[idx] = val & ~2;
 428         break;
 429
 430       case AlphaISA::IPR_ASTRR:
 431       case AlphaISA::IPR_ASTER:
 432         // only write least significant four bits - privilege mask
 433         ipr[idx] = val & 0xf;
 434         break;
 435
 436       case AlphaISA::IPR_IPLR:
 437 #ifdef DEBUG
 438         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 439             debug_break();
 440 #endif
 441
 442         // only write least significant five bits - interrupt level
 443         ipr[idx] = val & 0x1f;
 444         kernelStats.swpipl(ipr[idx]);
 445         break;
 446
 447       case AlphaISA::IPR_DTB_CM:
 448         kernelStats.mode((val & 0x18) != 0);
 449
 450       case AlphaISA::IPR_ICM:
 451         // only write two mode bits - processor mode
 452         ipr[idx] = val & 0x18;
 453         break;
 454
 455       case AlphaISA::IPR_ALT_MODE:
 456         // only write two mode bits - processor mode
 457         ipr[idx] = val & 0x18;
 458         break;
 459
 460       case AlphaISA::IPR_MCSR:
 461         // more here after optimization...
 462         ipr[idx] = val;
 463         break;
 464
 465       case AlphaISA::IPR_SIRR:
 466         // only write software interrupt mask
 467         ipr[idx] = val & 0x7fff0;
 468         break;
 469
 470       case AlphaISA::IPR_ICSR:
 471         ipr[idx] = val & ULL(0xffffff0300);
 472         break;
 473
 474       case AlphaISA::IPR_IVPTBR:
 475       case AlphaISA::IPR_MVPTBR:
 476         ipr[idx] = val & ULL(0xffffffffc0000000);
 477         break;
 478
 479       case AlphaISA::IPR_DC_TEST_CTL:
 480         ipr[idx] = val & 0x1ffb;
 481         break;
 482
 483       case AlphaISA::IPR_DC_MODE:
 484       case AlphaISA::IPR_MAF_MODE:
 485         ipr[idx] = val & 0x3f;
 486         break;
 487
 488       case AlphaISA::IPR_ITB_ASN:
 489         ipr[idx] = val & 0x7f0;
 490         break;
 491
 492       case AlphaISA::IPR_DTB_ASN:
 493         ipr[idx] = val & ULL(0xfe00000000000000);
 494         break;
 495
 496       case AlphaISA::IPR_EXC_SUM:
 497       case AlphaISA::IPR_EXC_MASK:
 498         // any write to this register clears it
 499         ipr[idx] = 0;
 500         break;
 501
 502       case AlphaISA::IPR_INTID:
 503       case AlphaISA::IPR_SL_RCV:
 504       case AlphaISA::IPR_MM_STAT:
 505       case AlphaISA::IPR_ITB_PTE_TEMP:
 506       case AlphaISA::IPR_DTB_PTE_TEMP:
 507         // read-only registers
 508         return Unimplemented_Opcode_Fault;
 509
 510       case AlphaISA::IPR_HWINT_CLR:
 511       case AlphaISA::IPR_SL_XMIT:
 512       case AlphaISA::IPR_DC_FLUSH:
 513       case AlphaISA::IPR_IC_FLUSH:
 514         // the following are write only
 515         ipr[idx] = val;
 516         break;
 517
 518       case AlphaISA::IPR_DTB_IA:
 519         // really a control write
 520         ipr[idx] = 0;
 521
 522         dtb->flushAll();
 523         break;
 524
 525       case AlphaISA::IPR_DTB_IAP:
 526         // really a control write
 527         ipr[idx] = 0;
 528
 529         dtb->flushProcesses();
 530         break;
 531
 532       case AlphaISA::IPR_DTB_IS:
 533         // really a control write
 534         ipr[idx] = val;
 535
 536         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 537         break;
 538
 539       case AlphaISA::IPR_DTB_TAG: {
 540           struct AlphaISA::PTE pte;
 541
 542           // FIXME: granularity hints NYI...
 543           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 544               panic("PTE GH field != 0");
 545
 546           // write entire quad
 547           ipr[idx] = val;
 548
 549           // construct PTE for new entry
 550           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 551           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 552           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 553           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 554           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 555           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 556           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 557
 558           // insert new TAG/PTE value into data TLB
 559           dtb->insert(val, pte);
 560       }
 561         break;
 562
 563       case AlphaISA::IPR_ITB_PTE: {
 564           struct AlphaISA::PTE pte;
 565
 566           // FIXME: granularity hints NYI...
 567           if (ITB_PTE_GH(val) != 0)
 568               panic("PTE GH field != 0");
 569
 570           // write entire quad
 571           ipr[idx] = val;
 572
 573           // construct PTE for new entry
 574           pte.ppn = ITB_PTE_PPN(val);
 575           pte.xre = ITB_PTE_XRE(val);
 576           pte.xwe = 0;
 577           pte.fonr = ITB_PTE_FONR(val);
 578           pte.fonw = ITB_PTE_FONW(val);
 579           pte.asma = ITB_PTE_ASMA(val);
 580           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 581
 582           // insert new TAG/PTE value into data TLB
 583           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 584       }
 585         break;
 586
 587       case AlphaISA::IPR_ITB_IA:
 588         // really a control write
 589         ipr[idx] = 0;
 590
 591         itb->flushAll();
 592         break;
 593
 594       case AlphaISA::IPR_ITB_IAP:
 595         // really a control write
 596         ipr[idx] = 0;
 597
 598         itb->flushProcesses();
 599         break;
 600
 601       case AlphaISA::IPR_ITB_IS:
 602         // really a control write
 603         ipr[idx] = val;
 604
 605         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 606         break;
 607
 608       default:
 609         // invalid IPR
 610         return Unimplemented_Opcode_Fault;
 611     }
 612
 613     // no error...
 614     return No_Fault;
 615 }
 616
 617 /**
 618  * Check for special simulator handling of specific PAL calls.
 619  * If return value is false, actual PAL call will be suppressed.
 620  */
 621 bool
 622 ExecContext::simPalCheck(int palFunc)
 623 {
 624     kernelStats.callpal(palFunc);
 625
 626     switch (palFunc) {
 627       case PAL::halt:
 628         halt();
 629         if (--System::numSystemsRunning == 0)
 630             new SimExitEvent("all cpus halted");
 631         break;
 632
 633       case PAL::bpt:
 634       case PAL::bugchk:
 635         if (system->breakpoint())
 636             return false;
 637         break;
 638     }
 639
 640     return true;
 641 }
 642
 643 //Forward instantiation for FastCPU object
 644 template
 645 void AlphaISA::processInterrupts(FastCPU *xc);
 646
 647 //Forward instantiation for FastCPU object
 648 template
 649 void AlphaISA::zeroRegisters(FastCPU *xc);
 650
 651 #endif // FULL_SYSTEM