arch/alpha/ev5.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/alpha/tlb.hh"
  30 #include "arch/alpha/isa_traits.hh"
  31 #include "arch/alpha/osfpal.hh"
  32 #include "base/kgdb.h"
  33 #include "base/remote_gdb.hh"
  34 #include "base/stats/events.hh"
  35 #include "config/full_system.hh"
  36 #include "cpu/base.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/fast/cpu.hh"
  39 #include "kern/kernel_stats.hh"
  40 #include "sim/debug.hh"
  41 #include "sim/sim_events.hh"
  42
  43 #if FULL_SYSTEM
  44
  45 using namespace EV5;
  46
  47 ////////////////////////////////////////////////////////////////////////
  48 //
  49 //
  50 //
  51 void
  52 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  53 {
  54     if (regs->pal_shadow == use_shadow)
  55         panic("swap_palshadow: wrong PAL shadow state");
  56
  57     regs->pal_shadow = use_shadow;
  58
  59     for (int i = 0; i < NumIntRegs; i++) {
  60         if (reg_redir[i]) {
  61             IntReg temp = regs->intRegFile[i];
  62             regs->intRegFile[i] = regs->palregs[i];
  63             regs->palregs[i] = temp;
  64         }
  65     }
  66 }
  67
  68 ////////////////////////////////////////////////////////////////////////
  69 //
  70 //  Machine dependent functions
  71 //
  72 void
  73 AlphaISA::initCPU(RegFile *regs, int cpuId)
  74 {
  75     initIPRs(regs, cpuId);
  76     // CPU comes up with PAL regs enabled
  77     swap_palshadow(regs, true);
  78
  79     regs->intRegFile[16] = cpuId;
  80     regs->intRegFile[0] = cpuId;
  81
  82     regs->pc = regs->ipr[IPR_PAL_BASE] + (new ResetFault)->vect();
  83     regs->npc = regs->pc + sizeof(MachInst);
  84 }
  85
  86 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  87     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  88     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  89     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  90     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  91
  92 ////////////////////////////////////////////////////////////////////////
  93 //
  94 //
  95 //
  96 void
  97 AlphaISA::initIPRs(RegFile *regs, int cpuId)
  98 {
  99     uint64_t *ipr = regs->ipr;
 100
 101     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
 102     ipr[IPR_PAL_BASE] = PalBase;
 103     ipr[IPR_MCSR] = 0x6;
 104     ipr[IPR_PALtemp16] = cpuId;
 105 }
 106
 107
 108 template <class CPU>
 109 void
 110 AlphaISA::processInterrupts(CPU *cpu)
 111 {
 112     //Check if there are any outstanding interrupts
 113     //Handle the interrupts
 114     int ipl = 0;
 115     int summary = 0;
 116     IntReg *ipr = cpu->getIprPtr();
 117
 118     cpu->checkInterrupts = false;
 119
 120     if (ipr[IPR_ASTRR])
 121         panic("asynchronous traps not implemented\n");
 122
 123     if (ipr[IPR_SIRR]) {
 124         for (int i = INTLEVEL_SOFTWARE_MIN;
 125              i < INTLEVEL_SOFTWARE_MAX; i++) {
 126             if (ipr[IPR_SIRR] & (ULL(1) << i)) {
 127                 // See table 4-19 of the 21164 hardware reference
 128                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 129                 summary |= (ULL(1) << i);
 130             }
 131         }
 132     }
 133
 134     uint64_t interrupts = cpu->intr_status();
 135
 136     if (interrupts) {
 137         for (int i = INTLEVEL_EXTERNAL_MIN;
 138              i < INTLEVEL_EXTERNAL_MAX; i++) {
 139             if (interrupts & (ULL(1) << i)) {
 140                 // See table 4-19 of the 21164 hardware reference
 141                 ipl = i;
 142                 summary |= (ULL(1) << i);
 143             }
 144         }
 145     }
 146
 147     if (ipl && ipl > ipr[IPR_IPLR]) {
 148         ipr[IPR_ISR] = summary;
 149         ipr[IPR_INTID] = ipl;
 150         cpu->trap(new InterruptFault);
 151         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 152                 ipr[IPR_IPLR], ipl, summary);
 153     }
 154
 155 }
 156
 157 template <class CPU>
 158 void
 159 AlphaISA::zeroRegisters(CPU *cpu)
 160 {
 161     // Insure ISA semantics
 162     // (no longer very clean due to the change in setIntReg() in the
 163     // cpu model.  Consider changing later.)
 164     cpu->xc->setIntReg(ZeroReg, 0);
 165     cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 166 }
 167
 168 void
 169 ExecContext::ev5_temp_trap(Fault fault)
 170 {
 171     DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
 172     cpu->recordEvent(csprintf("Fault %s", fault->name()));
 173
 174     assert(!misspeculating());
 175     kernelStats->fault(fault);
 176
 177     if (fault->isA<ArithmeticFault>())
 178         panic("Arithmetic traps are unimplemented!");
 179
 180     AlphaISA::InternalProcReg *ipr = regs.ipr;
 181
 182     // exception restart address
 183     if (!fault->isA<InterruptFault>() || !inPalMode())
 184         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 185
 186     if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
 187         fault == InterruptFault && !inPalMode() */) {
 188         // traps...  skip faulting instruction.
 189         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 190     }
 191
 192     if (!inPalMode())
 193         AlphaISA::swap_palshadow(&regs, true);
 194
 195     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] +
 196         (dynamic_cast<AlphaFault *>(fault.get()))->vect();
 197     regs.npc = regs.pc + sizeof(MachInst);
 198 }
 199
 200
 201 void
 202 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 203 {
 204     InternalProcReg *ipr = regs->ipr;
 205     bool use_pc = (fault == NoFault);
 206
 207     if (fault->isA<ArithmeticFault>())
 208         panic("arithmetic faults NYI...");
 209
 210     // compute exception restart address
 211     if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
 212         // traps...  skip faulting instruction
 213         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 214     } else {
 215         // fault, post fault at excepting instruction
 216         ipr[IPR_EXC_ADDR] = regs->pc;
 217     }
 218
 219     // jump to expection address (PAL PC bit set here as well...)
 220     if (!use_pc)
 221         regs->npc = ipr[IPR_PAL_BASE] +
 222             (dynamic_cast<AlphaFault *>(fault.get()))->vect();
 223     else
 224         regs->npc = ipr[IPR_PAL_BASE] + pc;
 225
 226     // that's it! (orders of magnitude less painful than x86)
 227 }
 228
 229 Fault
 230 ExecContext::hwrei()
 231 {
 232     uint64_t *ipr = regs.ipr;
 233
 234     if (!inPalMode())
 235         return new UnimplementedOpcodeFault;
 236
 237     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 238
 239     if (!misspeculating()) {
 240         kernelStats->hwrei();
 241
 242         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 243             AlphaISA::swap_palshadow(&regs, false);
 244
 245         cpu->checkInterrupts = true;
 246     }
 247
 248     // FIXME: XXX check for interrupts? XXX
 249     return NoFault;
 250 }
 251
 252 uint64_t
 253 ExecContext::readIpr(int idx, Fault &fault)
 254 {
 255     uint64_t *ipr = regs.ipr;
 256     uint64_t retval = 0;        // return value, default 0
 257
 258     switch (idx) {
 259       case AlphaISA::IPR_PALtemp0:
 260       case AlphaISA::IPR_PALtemp1:
 261       case AlphaISA::IPR_PALtemp2:
 262       case AlphaISA::IPR_PALtemp3:
 263       case AlphaISA::IPR_PALtemp4:
 264       case AlphaISA::IPR_PALtemp5:
 265       case AlphaISA::IPR_PALtemp6:
 266       case AlphaISA::IPR_PALtemp7:
 267       case AlphaISA::IPR_PALtemp8:
 268       case AlphaISA::IPR_PALtemp9:
 269       case AlphaISA::IPR_PALtemp10:
 270       case AlphaISA::IPR_PALtemp11:
 271       case AlphaISA::IPR_PALtemp12:
 272       case AlphaISA::IPR_PALtemp13:
 273       case AlphaISA::IPR_PALtemp14:
 274       case AlphaISA::IPR_PALtemp15:
 275       case AlphaISA::IPR_PALtemp16:
 276       case AlphaISA::IPR_PALtemp17:
 277       case AlphaISA::IPR_PALtemp18:
 278       case AlphaISA::IPR_PALtemp19:
 279       case AlphaISA::IPR_PALtemp20:
 280       case AlphaISA::IPR_PALtemp21:
 281       case AlphaISA::IPR_PALtemp22:
 282       case AlphaISA::IPR_PALtemp23:
 283       case AlphaISA::IPR_PAL_BASE:
 284
 285       case AlphaISA::IPR_IVPTBR:
 286       case AlphaISA::IPR_DC_MODE:
 287       case AlphaISA::IPR_MAF_MODE:
 288       case AlphaISA::IPR_ISR:
 289       case AlphaISA::IPR_EXC_ADDR:
 290       case AlphaISA::IPR_IC_PERR_STAT:
 291       case AlphaISA::IPR_DC_PERR_STAT:
 292       case AlphaISA::IPR_MCSR:
 293       case AlphaISA::IPR_ASTRR:
 294       case AlphaISA::IPR_ASTER:
 295       case AlphaISA::IPR_SIRR:
 296       case AlphaISA::IPR_ICSR:
 297       case AlphaISA::IPR_ICM:
 298       case AlphaISA::IPR_DTB_CM:
 299       case AlphaISA::IPR_IPLR:
 300       case AlphaISA::IPR_INTID:
 301       case AlphaISA::IPR_PMCTR:
 302         // no side-effect
 303         retval = ipr[idx];
 304         break;
 305
 306       case AlphaISA::IPR_CC:
 307         retval |= ipr[idx] & ULL(0xffffffff00000000);
 308         retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
 309         break;
 310
 311       case AlphaISA::IPR_VA:
 312         retval = ipr[idx];
 313         break;
 314
 315       case AlphaISA::IPR_VA_FORM:
 316       case AlphaISA::IPR_MM_STAT:
 317       case AlphaISA::IPR_IFAULT_VA_FORM:
 318       case AlphaISA::IPR_EXC_MASK:
 319       case AlphaISA::IPR_EXC_SUM:
 320         retval = ipr[idx];
 321         break;
 322
 323       case AlphaISA::IPR_DTB_PTE:
 324         {
 325             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 326
 327             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 328             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 329             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 330             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 331             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 332             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 333             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 334         }
 335         break;
 336
 337         // write only registers
 338       case AlphaISA::IPR_HWINT_CLR:
 339       case AlphaISA::IPR_SL_XMIT:
 340       case AlphaISA::IPR_DC_FLUSH:
 341       case AlphaISA::IPR_IC_FLUSH:
 342       case AlphaISA::IPR_ALT_MODE:
 343       case AlphaISA::IPR_DTB_IA:
 344       case AlphaISA::IPR_DTB_IAP:
 345       case AlphaISA::IPR_ITB_IA:
 346       case AlphaISA::IPR_ITB_IAP:
 347         fault = new UnimplementedOpcodeFault;
 348         break;
 349
 350       default:
 351         // invalid IPR
 352         fault = new UnimplementedOpcodeFault;
 353         break;
 354     }
 355
 356     return retval;
 357 }
 358
 359 #ifdef DEBUG
 360 // Cause the simulator to break when changing to the following IPL
 361 int break_ipl = -1;
 362 #endif
 363
 364 Fault
 365 ExecContext::setIpr(int idx, uint64_t val)
 366 {
 367     uint64_t *ipr = regs.ipr;
 368     uint64_t old;
 369
 370     if (misspeculating())
 371         return NoFault;
 372
 373     switch (idx) {
 374       case AlphaISA::IPR_PALtemp0:
 375       case AlphaISA::IPR_PALtemp1:
 376       case AlphaISA::IPR_PALtemp2:
 377       case AlphaISA::IPR_PALtemp3:
 378       case AlphaISA::IPR_PALtemp4:
 379       case AlphaISA::IPR_PALtemp5:
 380       case AlphaISA::IPR_PALtemp6:
 381       case AlphaISA::IPR_PALtemp7:
 382       case AlphaISA::IPR_PALtemp8:
 383       case AlphaISA::IPR_PALtemp9:
 384       case AlphaISA::IPR_PALtemp10:
 385       case AlphaISA::IPR_PALtemp11:
 386       case AlphaISA::IPR_PALtemp12:
 387       case AlphaISA::IPR_PALtemp13:
 388       case AlphaISA::IPR_PALtemp14:
 389       case AlphaISA::IPR_PALtemp15:
 390       case AlphaISA::IPR_PALtemp16:
 391       case AlphaISA::IPR_PALtemp17:
 392       case AlphaISA::IPR_PALtemp18:
 393       case AlphaISA::IPR_PALtemp19:
 394       case AlphaISA::IPR_PALtemp20:
 395       case AlphaISA::IPR_PALtemp21:
 396       case AlphaISA::IPR_PALtemp22:
 397       case AlphaISA::IPR_PAL_BASE:
 398       case AlphaISA::IPR_IC_PERR_STAT:
 399       case AlphaISA::IPR_DC_PERR_STAT:
 400       case AlphaISA::IPR_PMCTR:
 401         // write entire quad w/ no side-effect
 402         ipr[idx] = val;
 403         break;
 404
 405       case AlphaISA::IPR_CC_CTL:
 406         // This IPR resets the cycle counter.  We assume this only
 407         // happens once... let's verify that.
 408         assert(ipr[idx] == 0);
 409         ipr[idx] = 1;
 410         break;
 411
 412       case AlphaISA::IPR_CC:
 413         // This IPR only writes the upper 64 bits.  It's ok to write
 414         // all 64 here since we mask out the lower 32 in rpcc (see
 415         // isa_desc).
 416         ipr[idx] = val;
 417         break;
 418
 419       case AlphaISA::IPR_PALtemp23:
 420         // write entire quad w/ no side-effect
 421         old = ipr[idx];
 422         ipr[idx] = val;
 423         kernelStats->context(old, val);
 424         break;
 425
 426       case AlphaISA::IPR_DTB_PTE:
 427         // write entire quad w/ no side-effect, tag is forthcoming
 428         ipr[idx] = val;
 429         break;
 430
 431       case AlphaISA::IPR_EXC_ADDR:
 432         // second least significant bit in PC is always zero
 433         ipr[idx] = val & ~2;
 434         break;
 435
 436       case AlphaISA::IPR_ASTRR:
 437       case AlphaISA::IPR_ASTER:
 438         // only write least significant four bits - privilege mask
 439         ipr[idx] = val & 0xf;
 440         break;
 441
 442       case AlphaISA::IPR_IPLR:
 443 #ifdef DEBUG
 444         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 445             debug_break();
 446 #endif
 447
 448         // only write least significant five bits - interrupt level
 449         ipr[idx] = val & 0x1f;
 450         kernelStats->swpipl(ipr[idx]);
 451         break;
 452
 453       case AlphaISA::IPR_DTB_CM:
 454         if (val & 0x18)
 455             kernelStats->mode(Kernel::user);
 456         else
 457             kernelStats->mode(Kernel::kernel);
 458
 459       case AlphaISA::IPR_ICM:
 460         // only write two mode bits - processor mode
 461         ipr[idx] = val & 0x18;
 462         break;
 463
 464       case AlphaISA::IPR_ALT_MODE:
 465         // only write two mode bits - processor mode
 466         ipr[idx] = val & 0x18;
 467         break;
 468
 469       case AlphaISA::IPR_MCSR:
 470         // more here after optimization...
 471         ipr[idx] = val;
 472         break;
 473
 474       case AlphaISA::IPR_SIRR:
 475         // only write software interrupt mask
 476         ipr[idx] = val & 0x7fff0;
 477         break;
 478
 479       case AlphaISA::IPR_ICSR:
 480         ipr[idx] = val & ULL(0xffffff0300);
 481         break;
 482
 483       case AlphaISA::IPR_IVPTBR:
 484       case AlphaISA::IPR_MVPTBR:
 485         ipr[idx] = val & ULL(0xffffffffc0000000);
 486         break;
 487
 488       case AlphaISA::IPR_DC_TEST_CTL:
 489         ipr[idx] = val & 0x1ffb;
 490         break;
 491
 492       case AlphaISA::IPR_DC_MODE:
 493       case AlphaISA::IPR_MAF_MODE:
 494         ipr[idx] = val & 0x3f;
 495         break;
 496
 497       case AlphaISA::IPR_ITB_ASN:
 498         ipr[idx] = val & 0x7f0;
 499         break;
 500
 501       case AlphaISA::IPR_DTB_ASN:
 502         ipr[idx] = val & ULL(0xfe00000000000000);
 503         break;
 504
 505       case AlphaISA::IPR_EXC_SUM:
 506       case AlphaISA::IPR_EXC_MASK:
 507         // any write to this register clears it
 508         ipr[idx] = 0;
 509         break;
 510
 511       case AlphaISA::IPR_INTID:
 512       case AlphaISA::IPR_SL_RCV:
 513       case AlphaISA::IPR_MM_STAT:
 514       case AlphaISA::IPR_ITB_PTE_TEMP:
 515       case AlphaISA::IPR_DTB_PTE_TEMP:
 516         // read-only registers
 517         return new UnimplementedOpcodeFault;
 518
 519       case AlphaISA::IPR_HWINT_CLR:
 520       case AlphaISA::IPR_SL_XMIT:
 521       case AlphaISA::IPR_DC_FLUSH:
 522       case AlphaISA::IPR_IC_FLUSH:
 523         // the following are write only
 524         ipr[idx] = val;
 525         break;
 526
 527       case AlphaISA::IPR_DTB_IA:
 528         // really a control write
 529         ipr[idx] = 0;
 530
 531         dtb->flushAll();
 532         break;
 533
 534       case AlphaISA::IPR_DTB_IAP:
 535         // really a control write
 536         ipr[idx] = 0;
 537
 538         dtb->flushProcesses();
 539         break;
 540
 541       case AlphaISA::IPR_DTB_IS:
 542         // really a control write
 543         ipr[idx] = val;
 544
 545         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 546         break;
 547
 548       case AlphaISA::IPR_DTB_TAG: {
 549           struct AlphaISA::PTE pte;
 550
 551           // FIXME: granularity hints NYI...
 552           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 553               panic("PTE GH field != 0");
 554
 555           // write entire quad
 556           ipr[idx] = val;
 557
 558           // construct PTE for new entry
 559           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 560           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 561           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 562           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 563           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 564           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 565           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 566
 567           // insert new TAG/PTE value into data TLB
 568           dtb->insert(val, pte);
 569       }
 570         break;
 571
 572       case AlphaISA::IPR_ITB_PTE: {
 573           struct AlphaISA::PTE pte;
 574
 575           // FIXME: granularity hints NYI...
 576           if (ITB_PTE_GH(val) != 0)
 577               panic("PTE GH field != 0");
 578
 579           // write entire quad
 580           ipr[idx] = val;
 581
 582           // construct PTE for new entry
 583           pte.ppn = ITB_PTE_PPN(val);
 584           pte.xre = ITB_PTE_XRE(val);
 585           pte.xwe = 0;
 586           pte.fonr = ITB_PTE_FONR(val);
 587           pte.fonw = ITB_PTE_FONW(val);
 588           pte.asma = ITB_PTE_ASMA(val);
 589           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 590
 591           // insert new TAG/PTE value into data TLB
 592           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 593       }
 594         break;
 595
 596       case AlphaISA::IPR_ITB_IA:
 597         // really a control write
 598         ipr[idx] = 0;
 599
 600         itb->flushAll();
 601         break;
 602
 603       case AlphaISA::IPR_ITB_IAP:
 604         // really a control write
 605         ipr[idx] = 0;
 606
 607         itb->flushProcesses();
 608         break;
 609
 610       case AlphaISA::IPR_ITB_IS:
 611         // really a control write
 612         ipr[idx] = val;
 613
 614         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 615         break;
 616
 617       default:
 618         // invalid IPR
 619         return new UnimplementedOpcodeFault;
 620     }
 621
 622     // no error...
 623     return NoFault;
 624 }
 625
 626 /**
 627  * Check for special simulator handling of specific PAL calls.
 628  * If return value is false, actual PAL call will be suppressed.
 629  */
 630 bool
 631 ExecContext::simPalCheck(int palFunc)
 632 {
 633     kernelStats->callpal(palFunc);
 634
 635     switch (palFunc) {
 636       case PAL::halt:
 637         halt();
 638         if (--System::numSystemsRunning == 0)
 639             new SimExitEvent("all cpus halted");
 640         break;
 641
 642       case PAL::bpt:
 643       case PAL::bugchk:
 644         if (system->breakpoint())
 645             return false;
 646         break;
 647     }
 648
 649     return true;
 650 }
 651
 652 //Forward instantiation for FastCPU object
 653 template
 654 void AlphaISA::processInterrupts(FastCPU *xc);
 655
 656 //Forward instantiation for FastCPU object
 657 template
 658 void AlphaISA::zeroRegisters(FastCPU *xc);
 659
 660 #endif // FULL_SYSTEM