arch/alpha/ev5.cc

   1 /* $Id$ */
   2
   3 #include "targetarch/alpha_memory.hh"
   4 #ifdef DEBUG
   5 #include "sim/debug.hh"
   6 #endif
   7 #include "cpu/exec_context.hh"
   8 #include "sim/sim_events.hh"
   9 #include "targetarch/isa_traits.hh"
  10 #include "base/remote_gdb.hh"
  11 #include "base/kgdb.h"  // for ALPHA_KENTRY_IF
  12 #include "targetarch/osfpal.hh"
  13
  14 #ifdef FULL_SYSTEM
  15
  16 #ifndef SYSTEM_EV5
  17 #error This code is only valid for EV5 systems
  18 #endif
  19
  20 ////////////////////////////////////////////////////////////////////////
  21 //
  22 //
  23 //
  24 void
  25 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  26 {
  27     if (regs->pal_shadow == use_shadow)
  28         panic("swap_palshadow: wrong PAL shadow state");
  29
  30     regs->pal_shadow = use_shadow;
  31
  32     for (int i = 0; i < NumIntRegs; i++) {
  33         if (reg_redir[i]) {
  34             IntReg temp = regs->intRegFile[i];
  35             regs->intRegFile[i] = regs->palregs[i];
  36             regs->palregs[i] = temp;
  37         }
  38     }
  39 }
  40
  41 ////////////////////////////////////////////////////////////////////////
  42 //
  43 //  Machine dependent functions
  44 //
  45 void
  46 AlphaISA::initCPU(RegFile *regs)
  47 {
  48     initIPRs(regs);
  49     // CPU comes up with PAL regs enabled
  50     swap_palshadow(regs, true);
  51
  52     regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
  53     regs->npc = regs->pc + sizeof(MachInst);
  54 }
  55
  56 ////////////////////////////////////////////////////////////////////////
  57 //
  58 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
  59 //
  60 Addr
  61 AlphaISA::fault_addr[Num_Faults] = {
  62     0x0000,     /* No_Fault */
  63     0x0001,     /* Reset_Fault */
  64     0x0401,     /* Machine_Check_Fault */
  65     0x0501,     /* Arithmetic_Fault */
  66     0x0101,     /* Interrupt_Fault */
  67     0x0201,     /* Ndtb_Miss_Fault */
  68     0x0281,     /* Pdtb_Miss_Fault */
  69     0x0301,     /* Alignment_Fault */
  70     0x0381,     /* DTB_Fault_Fault */
  71     0x0381,     /* DTB_Acv_Fault */
  72     0x0181,     /* ITB_Miss_Fault */
  73     0x0181,     /* ITB_Fault_Fault */
  74     0x0081,     /* ITB_Acv_Fault */
  75     0x0481,     /* Unimplemented_Opcode_Fault */
  76     0x0581,     /* Fen_Fault */
  77     0x2001,     /* Pal_Fault */
  78     0x0501,     /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
  79 };
  80
  81 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  82     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  83     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  84     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  85     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  86
  87 ////////////////////////////////////////////////////////////////////////
  88 //
  89 //
  90 //
  91 void
  92 AlphaISA::initIPRs(RegFile *regs)
  93 {
  94     uint64_t *ipr = regs->ipr;
  95
  96     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
  97     ipr[IPR_PAL_BASE] = PAL_BASE;
  98     ipr[IPR_MCSR] = 0x6;
  99 }
 100
 101
 102 void
 103 ExecContext::ev5_trap(Fault fault)
 104 {
 105     assert(!misspeculating());
 106     kernelStats.fault(fault);
 107
 108     if (fault == Arithmetic_Fault)
 109         panic("Arithmetic traps are unimplemented!");
 110
 111     AlphaISA::InternalProcReg *ipr = regs.ipr;
 112
 113     // exception restart address
 114     if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
 115         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 116
 117     if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
 118         fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
 119         // traps...  skip faulting instruction
 120         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 121     }
 122
 123     if (!PC_PAL(regs.pc))
 124         AlphaISA::swap_palshadow(&regs, true);
 125
 126     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
 127     regs.npc = regs.pc + sizeof(MachInst);
 128 }
 129
 130
 131 void
 132 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 133 {
 134     InternalProcReg *ipr = regs->ipr;
 135     bool use_pc = (fault == No_Fault);
 136
 137     if (fault == Arithmetic_Fault)
 138         panic("arithmetic faults NYI...");
 139
 140     // compute exception restart address
 141     if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
 142         // traps...  skip faulting instruction
 143         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 144     } else {
 145         // fault, post fault at excepting instruction
 146         ipr[IPR_EXC_ADDR] = regs->pc;
 147     }
 148
 149     // jump to expection address (PAL PC bit set here as well...)
 150     if (!use_pc)
 151         regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
 152     else
 153         regs->npc = ipr[IPR_PAL_BASE] + pc;
 154
 155     // that's it! (orders of magnitude less painful than x86)
 156 }
 157
 158 bool AlphaISA::check_interrupts = false;
 159
 160 Fault
 161 ExecContext::hwrei()
 162 {
 163     uint64_t *ipr = regs.ipr;
 164
 165     if (!PC_PAL(regs.pc))
 166         return Unimplemented_Opcode_Fault;
 167
 168     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 169
 170     if (!misspeculating()) {
 171         kernelStats.hwrei();
 172
 173         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 174             AlphaISA::swap_palshadow(&regs, false);
 175
 176         AlphaISA::check_interrupts = true;
 177     }
 178
 179     // FIXME: XXX check for interrupts? XXX
 180     return No_Fault;
 181 }
 182
 183 uint64_t
 184 ExecContext::readIpr(int idx, Fault &fault)
 185 {
 186     uint64_t *ipr = regs.ipr;
 187     uint64_t retval = 0;        // return value, default 0
 188
 189     switch (idx) {
 190       case AlphaISA::IPR_PALtemp0:
 191       case AlphaISA::IPR_PALtemp1:
 192       case AlphaISA::IPR_PALtemp2:
 193       case AlphaISA::IPR_PALtemp3:
 194       case AlphaISA::IPR_PALtemp4:
 195       case AlphaISA::IPR_PALtemp5:
 196       case AlphaISA::IPR_PALtemp6:
 197       case AlphaISA::IPR_PALtemp7:
 198       case AlphaISA::IPR_PALtemp8:
 199       case AlphaISA::IPR_PALtemp9:
 200       case AlphaISA::IPR_PALtemp10:
 201       case AlphaISA::IPR_PALtemp11:
 202       case AlphaISA::IPR_PALtemp12:
 203       case AlphaISA::IPR_PALtemp13:
 204       case AlphaISA::IPR_PALtemp14:
 205       case AlphaISA::IPR_PALtemp15:
 206       case AlphaISA::IPR_PALtemp16:
 207       case AlphaISA::IPR_PALtemp17:
 208       case AlphaISA::IPR_PALtemp18:
 209       case AlphaISA::IPR_PALtemp19:
 210       case AlphaISA::IPR_PALtemp20:
 211       case AlphaISA::IPR_PALtemp21:
 212       case AlphaISA::IPR_PALtemp22:
 213       case AlphaISA::IPR_PALtemp23:
 214       case AlphaISA::IPR_PAL_BASE:
 215
 216       case AlphaISA::IPR_IVPTBR:
 217       case AlphaISA::IPR_DC_MODE:
 218       case AlphaISA::IPR_MAF_MODE:
 219       case AlphaISA::IPR_ISR:
 220       case AlphaISA::IPR_EXC_ADDR:
 221       case AlphaISA::IPR_IC_PERR_STAT:
 222       case AlphaISA::IPR_DC_PERR_STAT:
 223       case AlphaISA::IPR_MCSR:
 224       case AlphaISA::IPR_ASTRR:
 225       case AlphaISA::IPR_ASTER:
 226       case AlphaISA::IPR_SIRR:
 227       case AlphaISA::IPR_ICSR:
 228       case AlphaISA::IPR_ICM:
 229       case AlphaISA::IPR_DTB_CM:
 230       case AlphaISA::IPR_IPLR:
 231       case AlphaISA::IPR_INTID:
 232       case AlphaISA::IPR_PMCTR:
 233         // no side-effect
 234         retval = ipr[idx];
 235         break;
 236
 237       case AlphaISA::IPR_CC:
 238         retval |= ipr[idx] & ULL(0xffffffff00000000);
 239         retval |= curTick  & ULL(0x00000000ffffffff);
 240         break;
 241
 242       case AlphaISA::IPR_VA:
 243         // SFX: unlocks interrupt status registers
 244         retval = ipr[idx];
 245
 246         if (!misspeculating())
 247             regs.intrlock = false;
 248         break;
 249
 250       case AlphaISA::IPR_VA_FORM:
 251       case AlphaISA::IPR_MM_STAT:
 252       case AlphaISA::IPR_IFAULT_VA_FORM:
 253       case AlphaISA::IPR_EXC_MASK:
 254       case AlphaISA::IPR_EXC_SUM:
 255         retval = ipr[idx];
 256         break;
 257
 258       case AlphaISA::IPR_DTB_PTE:
 259         {
 260             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 261
 262             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 263             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 264             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 265             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 266             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 267             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 268             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 269         }
 270         break;
 271
 272         // write only registers
 273       case AlphaISA::IPR_HWINT_CLR:
 274       case AlphaISA::IPR_SL_XMIT:
 275       case AlphaISA::IPR_DC_FLUSH:
 276       case AlphaISA::IPR_IC_FLUSH:
 277       case AlphaISA::IPR_ALT_MODE:
 278       case AlphaISA::IPR_DTB_IA:
 279       case AlphaISA::IPR_DTB_IAP:
 280       case AlphaISA::IPR_ITB_IA:
 281       case AlphaISA::IPR_ITB_IAP:
 282         fault = Unimplemented_Opcode_Fault;
 283         break;
 284
 285       default:
 286         // invalid IPR
 287         fault = Unimplemented_Opcode_Fault;
 288         break;
 289     }
 290
 291     return retval;
 292 }
 293
 294 #ifdef DEBUG
 295 // Cause the simulator to break when changing to the following IPL
 296 int break_ipl = -1;
 297 #endif
 298
 299 Fault
 300 ExecContext::setIpr(int idx, uint64_t val)
 301 {
 302     uint64_t *ipr = regs.ipr;
 303     uint64_t old;
 304
 305     if (misspeculating())
 306         return No_Fault;
 307
 308     switch (idx) {
 309       case AlphaISA::IPR_PALtemp0:
 310       case AlphaISA::IPR_PALtemp1:
 311       case AlphaISA::IPR_PALtemp2:
 312       case AlphaISA::IPR_PALtemp3:
 313       case AlphaISA::IPR_PALtemp4:
 314       case AlphaISA::IPR_PALtemp5:
 315       case AlphaISA::IPR_PALtemp6:
 316       case AlphaISA::IPR_PALtemp7:
 317       case AlphaISA::IPR_PALtemp8:
 318       case AlphaISA::IPR_PALtemp9:
 319       case AlphaISA::IPR_PALtemp10:
 320       case AlphaISA::IPR_PALtemp11:
 321       case AlphaISA::IPR_PALtemp12:
 322       case AlphaISA::IPR_PALtemp13:
 323       case AlphaISA::IPR_PALtemp14:
 324       case AlphaISA::IPR_PALtemp15:
 325       case AlphaISA::IPR_PALtemp16:
 326       case AlphaISA::IPR_PALtemp17:
 327       case AlphaISA::IPR_PALtemp18:
 328       case AlphaISA::IPR_PALtemp19:
 329       case AlphaISA::IPR_PALtemp20:
 330       case AlphaISA::IPR_PALtemp21:
 331       case AlphaISA::IPR_PALtemp22:
 332       case AlphaISA::IPR_PAL_BASE:
 333       case AlphaISA::IPR_IC_PERR_STAT:
 334       case AlphaISA::IPR_DC_PERR_STAT:
 335       case AlphaISA::IPR_PMCTR:
 336         // write entire quad w/ no side-effect
 337         ipr[idx] = val;
 338         break;
 339
 340       case AlphaISA::IPR_CC_CTL:
 341         // This IPR resets the cycle counter.  We assume this only
 342         // happens once... let's verify that.
 343         assert(ipr[idx] == 0);
 344         ipr[idx] = 1;
 345         break;
 346
 347       case AlphaISA::IPR_CC:
 348         // This IPR only writes the upper 64 bits.  It's ok to write
 349         // all 64 here since we mask out the lower 32 in rpcc (see
 350         // isa_desc).
 351         ipr[idx] = val;
 352         break;
 353
 354       case AlphaISA::IPR_PALtemp23:
 355         // write entire quad w/ no side-effect
 356         old = ipr[idx];
 357         ipr[idx] = val;
 358         kernelStats.context(old, val);
 359         break;
 360
 361       case AlphaISA::IPR_DTB_PTE:
 362         // write entire quad w/ no side-effect, tag is forthcoming
 363         ipr[idx] = val;
 364         break;
 365
 366       case AlphaISA::IPR_EXC_ADDR:
 367         // second least significant bit in PC is always zero
 368         ipr[idx] = val & ~2;
 369         break;
 370
 371       case AlphaISA::IPR_ASTRR:
 372       case AlphaISA::IPR_ASTER:
 373         // only write least significant four bits - privilege mask
 374         ipr[idx] = val & 0xf;
 375         break;
 376
 377       case AlphaISA::IPR_IPLR:
 378 #ifdef DEBUG
 379         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 380             debug_break();
 381 #endif
 382
 383         // only write least significant five bits - interrupt level
 384         ipr[idx] = val & 0x1f;
 385         kernelStats.swpipl(ipr[idx]);
 386         break;
 387
 388       case AlphaISA::IPR_DTB_CM:
 389         kernelStats.mode((val & 0x18) != 0);
 390
 391       case AlphaISA::IPR_ICM:
 392         // only write two mode bits - processor mode
 393         ipr[idx] = val & 0x18;
 394         break;
 395
 396       case AlphaISA::IPR_ALT_MODE:
 397         // only write two mode bits - processor mode
 398         ipr[idx] = val & 0x18;
 399         break;
 400
 401       case AlphaISA::IPR_MCSR:
 402         // more here after optimization...
 403         ipr[idx] = val;
 404         break;
 405
 406       case AlphaISA::IPR_SIRR:
 407         // only write software interrupt mask
 408         ipr[idx] = val & 0x7fff0;
 409         break;
 410
 411       case AlphaISA::IPR_ICSR:
 412         ipr[idx] = val & ULL(0xffffff0300);
 413         break;
 414
 415       case AlphaISA::IPR_IVPTBR:
 416       case AlphaISA::IPR_MVPTBR:
 417         ipr[idx] = val & ULL(0xffffffffc0000000);
 418         break;
 419
 420       case AlphaISA::IPR_DC_TEST_CTL:
 421         ipr[idx] = val & 0x1ffb;
 422         break;
 423
 424       case AlphaISA::IPR_DC_MODE:
 425       case AlphaISA::IPR_MAF_MODE:
 426         ipr[idx] = val & 0x3f;
 427         break;
 428
 429       case AlphaISA::IPR_ITB_ASN:
 430         ipr[idx] = val & 0x7f0;
 431         break;
 432
 433       case AlphaISA::IPR_DTB_ASN:
 434         ipr[idx] = val & ULL(0xfe00000000000000);
 435         break;
 436
 437       case AlphaISA::IPR_EXC_SUM:
 438       case AlphaISA::IPR_EXC_MASK:
 439         // any write to this register clears it
 440         ipr[idx] = 0;
 441         break;
 442
 443       case AlphaISA::IPR_INTID:
 444       case AlphaISA::IPR_SL_RCV:
 445       case AlphaISA::IPR_MM_STAT:
 446       case AlphaISA::IPR_ITB_PTE_TEMP:
 447       case AlphaISA::IPR_DTB_PTE_TEMP:
 448         // read-only registers
 449         return Unimplemented_Opcode_Fault;
 450
 451       case AlphaISA::IPR_HWINT_CLR:
 452       case AlphaISA::IPR_SL_XMIT:
 453       case AlphaISA::IPR_DC_FLUSH:
 454       case AlphaISA::IPR_IC_FLUSH:
 455         // the following are write only
 456         ipr[idx] = val;
 457         break;
 458
 459       case AlphaISA::IPR_DTB_IA:
 460         // really a control write
 461         ipr[idx] = 0;
 462
 463         dtb->flushAll();
 464         break;
 465
 466       case AlphaISA::IPR_DTB_IAP:
 467         // really a control write
 468         ipr[idx] = 0;
 469
 470         dtb->flushProcesses();
 471         break;
 472
 473       case AlphaISA::IPR_DTB_IS:
 474         // really a control write
 475         ipr[idx] = val;
 476
 477         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 478         break;
 479
 480       case AlphaISA::IPR_DTB_TAG: {
 481           struct AlphaISA::PTE pte;
 482
 483           // FIXME: granularity hints NYI...
 484           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 485               panic("PTE GH field != 0");
 486
 487           // write entire quad
 488           ipr[idx] = val;
 489
 490           // construct PTE for new entry
 491           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 492           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 493           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 494           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 495           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 496           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 497           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 498
 499           // insert new TAG/PTE value into data TLB
 500           dtb->insert(val, pte);
 501       }
 502         break;
 503
 504       case AlphaISA::IPR_ITB_PTE: {
 505           struct AlphaISA::PTE pte;
 506
 507           // FIXME: granularity hints NYI...
 508           if (ITB_PTE_GH(val) != 0)
 509               panic("PTE GH field != 0");
 510
 511           // write entire quad
 512           ipr[idx] = val;
 513
 514           // construct PTE for new entry
 515           pte.ppn = ITB_PTE_PPN(val);
 516           pte.xre = ITB_PTE_XRE(val);
 517           pte.xwe = 0;
 518           pte.fonr = ITB_PTE_FONR(val);
 519           pte.fonw = ITB_PTE_FONW(val);
 520           pte.asma = ITB_PTE_ASMA(val);
 521           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 522
 523           // insert new TAG/PTE value into data TLB
 524           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 525       }
 526         break;
 527
 528       case AlphaISA::IPR_ITB_IA:
 529         // really a control write
 530         ipr[idx] = 0;
 531
 532         itb->flushAll();
 533         break;
 534
 535       case AlphaISA::IPR_ITB_IAP:
 536         // really a control write
 537         ipr[idx] = 0;
 538
 539         itb->flushProcesses();
 540         break;
 541
 542       case AlphaISA::IPR_ITB_IS:
 543         // really a control write
 544         ipr[idx] = val;
 545
 546         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 547         break;
 548
 549       default:
 550         // invalid IPR
 551         return Unimplemented_Opcode_Fault;
 552     }
 553
 554     // no error...
 555     return No_Fault;
 556 }
 557
 558 /**
 559  * Check for special simulator handling of specific PAL calls.
 560  * If return value is false, actual PAL call will be suppressed.
 561  */
 562 bool
 563 ExecContext::simPalCheck(int palFunc)
 564 {
 565     kernelStats.callpal(palFunc);
 566
 567     switch (palFunc) {
 568       case PAL::halt:
 569         halt();
 570         if (--System::numSystemsRunning == 0)
 571             new SimExitEvent("all cpus halted");
 572         break;
 573
 574       case PAL::bpt:
 575       case PAL::bugchk:
 576         if (system->breakpoint())
 577             return false;
 578         break;
 579     }
 580
 581     return true;
 582 }
 583
 584 #endif // FULL_SYSTEM