arch/alpha/ev5.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/alpha/tlb.hh"
  30 #include "arch/alpha/isa_traits.hh"
  31 #include "arch/alpha/osfpal.hh"
  32 #include "base/kgdb.h"
  33 #include "base/remote_gdb.hh"
  34 #include "base/stats/events.hh"
  35 #include "config/full_system.hh"
  36 #include "cpu/base.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/fast/cpu.hh"
  39 #include "kern/kernel_stats.hh"
  40 #include "sim/debug.hh"
  41 #include "sim/sim_events.hh"
  42
  43 #if FULL_SYSTEM
  44
  45 using namespace EV5;
  46
  47 ////////////////////////////////////////////////////////////////////////
  48 //
  49 //
  50 //
  51 void
  52 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  53 {
  54     if (regs->pal_shadow == use_shadow)
  55         panic("swap_palshadow: wrong PAL shadow state");
  56
  57     regs->pal_shadow = use_shadow;
  58
  59     for (int i = 0; i < NumIntRegs; i++) {
  60         if (reg_redir[i]) {
  61             IntReg temp = regs->intRegFile[i];
  62             regs->intRegFile[i] = regs->palregs[i];
  63             regs->palregs[i] = temp;
  64         }
  65     }
  66 }
  67
  68 ////////////////////////////////////////////////////////////////////////
  69 //
  70 //  Machine dependent functions
  71 //
  72 void
  73 AlphaISA::initCPU(RegFile *regs, int cpuId)
  74 {
  75     initIPRs(regs, cpuId);
  76     // CPU comes up with PAL regs enabled
  77     swap_palshadow(regs, true);
  78
  79     regs->intRegFile[16] = cpuId;
  80     regs->intRegFile[0] = cpuId;
  81
  82     regs->pc = regs->ipr[IPR_PAL_BASE] + (new ResetFault)->vect();
  83     regs->npc = regs->pc + sizeof(MachInst);
  84 }
  85
  86 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  87     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  88     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  89     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  90     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  91
  92 ////////////////////////////////////////////////////////////////////////
  93 //
  94 //
  95 //
  96 void
  97 AlphaISA::initIPRs(RegFile *regs, int cpuId)
  98 {
  99     uint64_t *ipr = regs->ipr;
 100
 101     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
 102     ipr[IPR_PAL_BASE] = PalBase;
 103     ipr[IPR_MCSR] = 0x6;
 104     ipr[IPR_PALtemp16] = cpuId;
 105 }
 106
 107
 108 template <class CPU>
 109 void
 110 AlphaISA::processInterrupts(CPU *cpu)
 111 {
 112     //Check if there are any outstanding interrupts
 113     //Handle the interrupts
 114     int ipl = 0;
 115     int summary = 0;
 116     IntReg *ipr = cpu->getIprPtr();
 117
 118     cpu->checkInterrupts = false;
 119
 120     if (ipr[IPR_ASTRR])
 121         panic("asynchronous traps not implemented\n");
 122
 123     if (ipr[IPR_SIRR]) {
 124         for (int i = INTLEVEL_SOFTWARE_MIN;
 125              i < INTLEVEL_SOFTWARE_MAX; i++) {
 126             if (ipr[IPR_SIRR] & (ULL(1) << i)) {
 127                 // See table 4-19 of the 21164 hardware reference
 128                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 129                 summary |= (ULL(1) << i);
 130             }
 131         }
 132     }
 133
 134     uint64_t interrupts = cpu->intr_status();
 135
 136     if (interrupts) {
 137         for (int i = INTLEVEL_EXTERNAL_MIN;
 138              i < INTLEVEL_EXTERNAL_MAX; i++) {
 139             if (interrupts & (ULL(1) << i)) {
 140                 // See table 4-19 of the 21164 hardware reference
 141                 ipl = i;
 142                 summary |= (ULL(1) << i);
 143             }
 144         }
 145     }
 146
 147     if (ipl && ipl > ipr[IPR_IPLR]) {
 148         ipr[IPR_ISR] = summary;
 149         ipr[IPR_INTID] = ipl;
 150         cpu->trap(new InterruptFault);
 151         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 152                 ipr[IPR_IPLR], ipl, summary);
 153     }
 154
 155 }
 156
 157 template <class CPU>
 158 void
 159 AlphaISA::zeroRegisters(CPU *cpu)
 160 {
 161     // Insure ISA semantics
 162     // (no longer very clean due to the change in setIntReg() in the
 163     // cpu model.  Consider changing later.)
 164     cpu->xc->setIntReg(ZeroReg, 0);
 165     cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 166 }
 167
 168 void
 169 ExecContext::ev5_temp_trap(Fault fault)
 170 {
 171     DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc);
 172     cpu->recordEvent(csprintf("Fault %s", fault->name()));
 173
 174     assert(!misspeculating());
 175     kernelStats->fault(fault);
 176
 177     if (fault->isA<ArithmeticFault>())
 178         panic("Arithmetic traps are unimplemented!");
 179
 180     AlphaISA::InternalProcReg *ipr = regs.ipr;
 181
 182     // exception restart address
 183     if (!fault->isA<InterruptFault>() || !inPalMode())
 184         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 185
 186     if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
 187         fault == InterruptFault && !inPalMode() */) {
 188         // traps...  skip faulting instruction.
 189         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 190     }
 191
 192     if (!inPalMode())
 193         AlphaISA::swap_palshadow(&regs, true);
 194
 195     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + ((AlphaFault *)(fault.get()))->vect();
 196     regs.npc = regs.pc + sizeof(MachInst);
 197 }
 198
 199
 200 void
 201 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 202 {
 203     InternalProcReg *ipr = regs->ipr;
 204     bool use_pc = (fault == NoFault);
 205
 206     if (fault->isA<ArithmeticFault>())
 207         panic("arithmetic faults NYI...");
 208
 209     // compute exception restart address
 210     if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
 211         // traps...  skip faulting instruction
 212         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 213     } else {
 214         // fault, post fault at excepting instruction
 215         ipr[IPR_EXC_ADDR] = regs->pc;
 216     }
 217
 218     // jump to expection address (PAL PC bit set here as well...)
 219     if (!use_pc)
 220         regs->npc = ipr[IPR_PAL_BASE] + ((AlphaFault *)(fault.get()))->vect();
 221     else
 222         regs->npc = ipr[IPR_PAL_BASE] + pc;
 223
 224     // that's it! (orders of magnitude less painful than x86)
 225 }
 226
 227 Fault
 228 ExecContext::hwrei()
 229 {
 230     uint64_t *ipr = regs.ipr;
 231
 232     if (!inPalMode())
 233         return new UnimplementedOpcodeFault;
 234
 235     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 236
 237     if (!misspeculating()) {
 238         kernelStats->hwrei();
 239
 240         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 241             AlphaISA::swap_palshadow(&regs, false);
 242
 243         cpu->checkInterrupts = true;
 244     }
 245
 246     // FIXME: XXX check for interrupts? XXX
 247     return NoFault;
 248 }
 249
 250 uint64_t
 251 ExecContext::readIpr(int idx, Fault &fault)
 252 {
 253     uint64_t *ipr = regs.ipr;
 254     uint64_t retval = 0;        // return value, default 0
 255
 256     switch (idx) {
 257       case AlphaISA::IPR_PALtemp0:
 258       case AlphaISA::IPR_PALtemp1:
 259       case AlphaISA::IPR_PALtemp2:
 260       case AlphaISA::IPR_PALtemp3:
 261       case AlphaISA::IPR_PALtemp4:
 262       case AlphaISA::IPR_PALtemp5:
 263       case AlphaISA::IPR_PALtemp6:
 264       case AlphaISA::IPR_PALtemp7:
 265       case AlphaISA::IPR_PALtemp8:
 266       case AlphaISA::IPR_PALtemp9:
 267       case AlphaISA::IPR_PALtemp10:
 268       case AlphaISA::IPR_PALtemp11:
 269       case AlphaISA::IPR_PALtemp12:
 270       case AlphaISA::IPR_PALtemp13:
 271       case AlphaISA::IPR_PALtemp14:
 272       case AlphaISA::IPR_PALtemp15:
 273       case AlphaISA::IPR_PALtemp16:
 274       case AlphaISA::IPR_PALtemp17:
 275       case AlphaISA::IPR_PALtemp18:
 276       case AlphaISA::IPR_PALtemp19:
 277       case AlphaISA::IPR_PALtemp20:
 278       case AlphaISA::IPR_PALtemp21:
 279       case AlphaISA::IPR_PALtemp22:
 280       case AlphaISA::IPR_PALtemp23:
 281       case AlphaISA::IPR_PAL_BASE:
 282
 283       case AlphaISA::IPR_IVPTBR:
 284       case AlphaISA::IPR_DC_MODE:
 285       case AlphaISA::IPR_MAF_MODE:
 286       case AlphaISA::IPR_ISR:
 287       case AlphaISA::IPR_EXC_ADDR:
 288       case AlphaISA::IPR_IC_PERR_STAT:
 289       case AlphaISA::IPR_DC_PERR_STAT:
 290       case AlphaISA::IPR_MCSR:
 291       case AlphaISA::IPR_ASTRR:
 292       case AlphaISA::IPR_ASTER:
 293       case AlphaISA::IPR_SIRR:
 294       case AlphaISA::IPR_ICSR:
 295       case AlphaISA::IPR_ICM:
 296       case AlphaISA::IPR_DTB_CM:
 297       case AlphaISA::IPR_IPLR:
 298       case AlphaISA::IPR_INTID:
 299       case AlphaISA::IPR_PMCTR:
 300         // no side-effect
 301         retval = ipr[idx];
 302         break;
 303
 304       case AlphaISA::IPR_CC:
 305         retval |= ipr[idx] & ULL(0xffffffff00000000);
 306         retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
 307         break;
 308
 309       case AlphaISA::IPR_VA:
 310         retval = ipr[idx];
 311         break;
 312
 313       case AlphaISA::IPR_VA_FORM:
 314       case AlphaISA::IPR_MM_STAT:
 315       case AlphaISA::IPR_IFAULT_VA_FORM:
 316       case AlphaISA::IPR_EXC_MASK:
 317       case AlphaISA::IPR_EXC_SUM:
 318         retval = ipr[idx];
 319         break;
 320
 321       case AlphaISA::IPR_DTB_PTE:
 322         {
 323             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 324
 325             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 326             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 327             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 328             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 329             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 330             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 331             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 332         }
 333         break;
 334
 335         // write only registers
 336       case AlphaISA::IPR_HWINT_CLR:
 337       case AlphaISA::IPR_SL_XMIT:
 338       case AlphaISA::IPR_DC_FLUSH:
 339       case AlphaISA::IPR_IC_FLUSH:
 340       case AlphaISA::IPR_ALT_MODE:
 341       case AlphaISA::IPR_DTB_IA:
 342       case AlphaISA::IPR_DTB_IAP:
 343       case AlphaISA::IPR_ITB_IA:
 344       case AlphaISA::IPR_ITB_IAP:
 345         fault = new UnimplementedOpcodeFault;
 346         break;
 347
 348       default:
 349         // invalid IPR
 350         fault = new UnimplementedOpcodeFault;
 351         break;
 352     }
 353
 354     return retval;
 355 }
 356
 357 #ifdef DEBUG
 358 // Cause the simulator to break when changing to the following IPL
 359 int break_ipl = -1;
 360 #endif
 361
 362 Fault
 363 ExecContext::setIpr(int idx, uint64_t val)
 364 {
 365     uint64_t *ipr = regs.ipr;
 366     uint64_t old;
 367
 368     if (misspeculating())
 369         return NoFault;
 370
 371     switch (idx) {
 372       case AlphaISA::IPR_PALtemp0:
 373       case AlphaISA::IPR_PALtemp1:
 374       case AlphaISA::IPR_PALtemp2:
 375       case AlphaISA::IPR_PALtemp3:
 376       case AlphaISA::IPR_PALtemp4:
 377       case AlphaISA::IPR_PALtemp5:
 378       case AlphaISA::IPR_PALtemp6:
 379       case AlphaISA::IPR_PALtemp7:
 380       case AlphaISA::IPR_PALtemp8:
 381       case AlphaISA::IPR_PALtemp9:
 382       case AlphaISA::IPR_PALtemp10:
 383       case AlphaISA::IPR_PALtemp11:
 384       case AlphaISA::IPR_PALtemp12:
 385       case AlphaISA::IPR_PALtemp13:
 386       case AlphaISA::IPR_PALtemp14:
 387       case AlphaISA::IPR_PALtemp15:
 388       case AlphaISA::IPR_PALtemp16:
 389       case AlphaISA::IPR_PALtemp17:
 390       case AlphaISA::IPR_PALtemp18:
 391       case AlphaISA::IPR_PALtemp19:
 392       case AlphaISA::IPR_PALtemp20:
 393       case AlphaISA::IPR_PALtemp21:
 394       case AlphaISA::IPR_PALtemp22:
 395       case AlphaISA::IPR_PAL_BASE:
 396       case AlphaISA::IPR_IC_PERR_STAT:
 397       case AlphaISA::IPR_DC_PERR_STAT:
 398       case AlphaISA::IPR_PMCTR:
 399         // write entire quad w/ no side-effect
 400         ipr[idx] = val;
 401         break;
 402
 403       case AlphaISA::IPR_CC_CTL:
 404         // This IPR resets the cycle counter.  We assume this only
 405         // happens once... let's verify that.
 406         assert(ipr[idx] == 0);
 407         ipr[idx] = 1;
 408         break;
 409
 410       case AlphaISA::IPR_CC:
 411         // This IPR only writes the upper 64 bits.  It's ok to write
 412         // all 64 here since we mask out the lower 32 in rpcc (see
 413         // isa_desc).
 414         ipr[idx] = val;
 415         break;
 416
 417       case AlphaISA::IPR_PALtemp23:
 418         // write entire quad w/ no side-effect
 419         old = ipr[idx];
 420         ipr[idx] = val;
 421         kernelStats->context(old, val);
 422         break;
 423
 424       case AlphaISA::IPR_DTB_PTE:
 425         // write entire quad w/ no side-effect, tag is forthcoming
 426         ipr[idx] = val;
 427         break;
 428
 429       case AlphaISA::IPR_EXC_ADDR:
 430         // second least significant bit in PC is always zero
 431         ipr[idx] = val & ~2;
 432         break;
 433
 434       case AlphaISA::IPR_ASTRR:
 435       case AlphaISA::IPR_ASTER:
 436         // only write least significant four bits - privilege mask
 437         ipr[idx] = val & 0xf;
 438         break;
 439
 440       case AlphaISA::IPR_IPLR:
 441 #ifdef DEBUG
 442         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 443             debug_break();
 444 #endif
 445
 446         // only write least significant five bits - interrupt level
 447         ipr[idx] = val & 0x1f;
 448         kernelStats->swpipl(ipr[idx]);
 449         break;
 450
 451       case AlphaISA::IPR_DTB_CM:
 452         if (val & 0x18)
 453             kernelStats->mode(Kernel::user);
 454         else
 455             kernelStats->mode(Kernel::kernel);
 456
 457       case AlphaISA::IPR_ICM:
 458         // only write two mode bits - processor mode
 459         ipr[idx] = val & 0x18;
 460         break;
 461
 462       case AlphaISA::IPR_ALT_MODE:
 463         // only write two mode bits - processor mode
 464         ipr[idx] = val & 0x18;
 465         break;
 466
 467       case AlphaISA::IPR_MCSR:
 468         // more here after optimization...
 469         ipr[idx] = val;
 470         break;
 471
 472       case AlphaISA::IPR_SIRR:
 473         // only write software interrupt mask
 474         ipr[idx] = val & 0x7fff0;
 475         break;
 476
 477       case AlphaISA::IPR_ICSR:
 478         ipr[idx] = val & ULL(0xffffff0300);
 479         break;
 480
 481       case AlphaISA::IPR_IVPTBR:
 482       case AlphaISA::IPR_MVPTBR:
 483         ipr[idx] = val & ULL(0xffffffffc0000000);
 484         break;
 485
 486       case AlphaISA::IPR_DC_TEST_CTL:
 487         ipr[idx] = val & 0x1ffb;
 488         break;
 489
 490       case AlphaISA::IPR_DC_MODE:
 491       case AlphaISA::IPR_MAF_MODE:
 492         ipr[idx] = val & 0x3f;
 493         break;
 494
 495       case AlphaISA::IPR_ITB_ASN:
 496         ipr[idx] = val & 0x7f0;
 497         break;
 498
 499       case AlphaISA::IPR_DTB_ASN:
 500         ipr[idx] = val & ULL(0xfe00000000000000);
 501         break;
 502
 503       case AlphaISA::IPR_EXC_SUM:
 504       case AlphaISA::IPR_EXC_MASK:
 505         // any write to this register clears it
 506         ipr[idx] = 0;
 507         break;
 508
 509       case AlphaISA::IPR_INTID:
 510       case AlphaISA::IPR_SL_RCV:
 511       case AlphaISA::IPR_MM_STAT:
 512       case AlphaISA::IPR_ITB_PTE_TEMP:
 513       case AlphaISA::IPR_DTB_PTE_TEMP:
 514         // read-only registers
 515         return new UnimplementedOpcodeFault;
 516
 517       case AlphaISA::IPR_HWINT_CLR:
 518       case AlphaISA::IPR_SL_XMIT:
 519       case AlphaISA::IPR_DC_FLUSH:
 520       case AlphaISA::IPR_IC_FLUSH:
 521         // the following are write only
 522         ipr[idx] = val;
 523         break;
 524
 525       case AlphaISA::IPR_DTB_IA:
 526         // really a control write
 527         ipr[idx] = 0;
 528
 529         dtb->flushAll();
 530         break;
 531
 532       case AlphaISA::IPR_DTB_IAP:
 533         // really a control write
 534         ipr[idx] = 0;
 535
 536         dtb->flushProcesses();
 537         break;
 538
 539       case AlphaISA::IPR_DTB_IS:
 540         // really a control write
 541         ipr[idx] = val;
 542
 543         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 544         break;
 545
 546       case AlphaISA::IPR_DTB_TAG: {
 547           struct AlphaISA::PTE pte;
 548
 549           // FIXME: granularity hints NYI...
 550           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 551               panic("PTE GH field != 0");
 552
 553           // write entire quad
 554           ipr[idx] = val;
 555
 556           // construct PTE for new entry
 557           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 558           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 559           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 560           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 561           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 562           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 563           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 564
 565           // insert new TAG/PTE value into data TLB
 566           dtb->insert(val, pte);
 567       }
 568         break;
 569
 570       case AlphaISA::IPR_ITB_PTE: {
 571           struct AlphaISA::PTE pte;
 572
 573           // FIXME: granularity hints NYI...
 574           if (ITB_PTE_GH(val) != 0)
 575               panic("PTE GH field != 0");
 576
 577           // write entire quad
 578           ipr[idx] = val;
 579
 580           // construct PTE for new entry
 581           pte.ppn = ITB_PTE_PPN(val);
 582           pte.xre = ITB_PTE_XRE(val);
 583           pte.xwe = 0;
 584           pte.fonr = ITB_PTE_FONR(val);
 585           pte.fonw = ITB_PTE_FONW(val);
 586           pte.asma = ITB_PTE_ASMA(val);
 587           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 588
 589           // insert new TAG/PTE value into data TLB
 590           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 591       }
 592         break;
 593
 594       case AlphaISA::IPR_ITB_IA:
 595         // really a control write
 596         ipr[idx] = 0;
 597
 598         itb->flushAll();
 599         break;
 600
 601       case AlphaISA::IPR_ITB_IAP:
 602         // really a control write
 603         ipr[idx] = 0;
 604
 605         itb->flushProcesses();
 606         break;
 607
 608       case AlphaISA::IPR_ITB_IS:
 609         // really a control write
 610         ipr[idx] = val;
 611
 612         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 613         break;
 614
 615       default:
 616         // invalid IPR
 617         return new UnimplementedOpcodeFault;
 618     }
 619
 620     // no error...
 621     return NoFault;
 622 }
 623
 624 /**
 625  * Check for special simulator handling of specific PAL calls.
 626  * If return value is false, actual PAL call will be suppressed.
 627  */
 628 bool
 629 ExecContext::simPalCheck(int palFunc)
 630 {
 631     kernelStats->callpal(palFunc);
 632
 633     switch (palFunc) {
 634       case PAL::halt:
 635         halt();
 636         if (--System::numSystemsRunning == 0)
 637             new SimExitEvent("all cpus halted");
 638         break;
 639
 640       case PAL::bpt:
 641       case PAL::bugchk:
 642         if (system->breakpoint())
 643             return false;
 644         break;
 645     }
 646
 647     return true;
 648 }
 649
 650 //Forward instantiation for FastCPU object
 651 template
 652 void AlphaISA::processInterrupts(FastCPU *xc);
 653
 654 //Forward instantiation for FastCPU object
 655 template
 656 void AlphaISA::zeroRegisters(FastCPU *xc);
 657
 658 #endif // FULL_SYSTEM