arch/alpha/ev5.cc

   1 /* $Id$ */
   2
   3 #include "arch/alpha/alpha_memory.hh"
   4 #include "arch/alpha/isa_traits.hh"
   5 #include "arch/alpha/osfpal.hh"
   6 #include "base/kgdb.h"
   7 #include "base/remote_gdb.hh"
   8 #include "base/stats/events.hh"
   9 #include "cpu/exec_context.hh"
  10 #include "cpu/fast_cpu/fast_cpu.hh"
  11 #include "sim/debug.hh"
  12 #include "sim/sim_events.hh"
  13
  14 #ifdef FULL_SYSTEM
  15
  16 #ifndef SYSTEM_EV5
  17 #error This code is only valid for EV5 systems
  18 #endif
  19
  20 ////////////////////////////////////////////////////////////////////////
  21 //
  22 //
  23 //
  24 void
  25 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  26 {
  27     if (regs->pal_shadow == use_shadow)
  28         panic("swap_palshadow: wrong PAL shadow state");
  29
  30     regs->pal_shadow = use_shadow;
  31
  32     for (int i = 0; i < NumIntRegs; i++) {
  33         if (reg_redir[i]) {
  34             IntReg temp = regs->intRegFile[i];
  35             regs->intRegFile[i] = regs->palregs[i];
  36             regs->palregs[i] = temp;
  37         }
  38     }
  39 }
  40
  41 ////////////////////////////////////////////////////////////////////////
  42 //
  43 //  Machine dependent functions
  44 //
  45 void
  46 AlphaISA::initCPU(RegFile *regs)
  47 {
  48     initIPRs(regs);
  49     // CPU comes up with PAL regs enabled
  50     swap_palshadow(regs, true);
  51
  52     regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
  53     regs->npc = regs->pc + sizeof(MachInst);
  54 }
  55
  56 ////////////////////////////////////////////////////////////////////////
  57 //
  58 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
  59 //
  60 Addr
  61 AlphaISA::fault_addr[Num_Faults] = {
  62     0x0000,     /* No_Fault */
  63     0x0001,     /* Reset_Fault */
  64     0x0401,     /* Machine_Check_Fault */
  65     0x0501,     /* Arithmetic_Fault */
  66     0x0101,     /* Interrupt_Fault */
  67     0x0201,     /* Ndtb_Miss_Fault */
  68     0x0281,     /* Pdtb_Miss_Fault */
  69     0x0301,     /* Alignment_Fault */
  70     0x0381,     /* DTB_Fault_Fault */
  71     0x0381,     /* DTB_Acv_Fault */
  72     0x0181,     /* ITB_Miss_Fault */
  73     0x0181,     /* ITB_Fault_Fault */
  74     0x0081,     /* ITB_Acv_Fault */
  75     0x0481,     /* Unimplemented_Opcode_Fault */
  76     0x0581,     /* Fen_Fault */
  77     0x2001,     /* Pal_Fault */
  78     0x0501,     /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
  79 };
  80
  81 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  82     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  83     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  84     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  85     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  86
  87 ////////////////////////////////////////////////////////////////////////
  88 //
  89 //
  90 //
  91 void
  92 AlphaISA::initIPRs(RegFile *regs)
  93 {
  94     uint64_t *ipr = regs->ipr;
  95
  96     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
  97     ipr[IPR_PAL_BASE] = PAL_BASE;
  98     ipr[IPR_MCSR] = 0x6;
  99 }
 100
 101
 102 template <class XC>
 103 void
 104 AlphaISA::processInterrupts(XC *xc)
 105 {
 106     //Check if there are any outstanding interrupts
 107     //Handle the interrupts
 108     int ipl = 0;
 109     int summary = 0;
 110     IntReg *ipr = xc->getIprPtr();
 111
 112     check_interrupts = 0;
 113
 114     if (ipr[IPR_ASTRR])
 115         panic("asynchronous traps not implemented\n");
 116
 117     if (ipr[IPR_SIRR]) {
 118         for (int i = INTLEVEL_SOFTWARE_MIN;
 119              i < INTLEVEL_SOFTWARE_MAX; i++) {
 120             if (ipr[IPR_SIRR] & (ULL(1) << i)) {
 121                 // See table 4-19 of the 21164 hardware reference
 122                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 123                 summary |= (ULL(1) << i);
 124             }
 125         }
 126     }
 127
 128     uint64_t interrupts = xc->intr_status();
 129
 130     if (interrupts) {
 131         for (int i = INTLEVEL_EXTERNAL_MIN;
 132              i < INTLEVEL_EXTERNAL_MAX; i++) {
 133             if (interrupts & (ULL(1) << i)) {
 134                 // See table 4-19 of the 21164 hardware reference
 135                 ipl = i;
 136                 summary |= (ULL(1) << i);
 137             }
 138         }
 139     }
 140
 141     if (ipl && ipl > ipr[IPR_IPLR]) {
 142         ipr[IPR_ISR] = summary;
 143         ipr[IPR_INTID] = ipl;
 144         xc->trap(Interrupt_Fault);
 145         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 146                 ipr[IPR_IPLR], ipl, summary);
 147     }
 148
 149 }
 150
 151 template <class XC>
 152 void
 153 AlphaISA::zeroRegisters(XC *xc)
 154 {
 155     // Insure ISA semantics
 156     // (no longer very clean due to the change in setIntReg() in the
 157     // cpu model.  Consider changing later.)
 158     xc->xc->setIntReg(ZeroReg, 0);
 159     xc->xc->setFloatRegDouble(ZeroReg, 0.0);
 160 }
 161
 162 void
 163 ExecContext::ev5_trap(Fault fault)
 164 {
 165     Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
 166
 167     assert(!misspeculating());
 168     kernelStats.fault(fault);
 169
 170     if (fault == Arithmetic_Fault)
 171         panic("Arithmetic traps are unimplemented!");
 172
 173     AlphaISA::InternalProcReg *ipr = regs.ipr;
 174
 175     // exception restart address
 176     if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
 177         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 178
 179     if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
 180         fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
 181         // traps...  skip faulting instruction
 182         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 183     }
 184
 185     if (!PC_PAL(regs.pc))
 186         AlphaISA::swap_palshadow(&regs, true);
 187
 188     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
 189     regs.npc = regs.pc + sizeof(MachInst);
 190 }
 191
 192
 193 void
 194 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 195 {
 196     InternalProcReg *ipr = regs->ipr;
 197     bool use_pc = (fault == No_Fault);
 198
 199     if (fault == Arithmetic_Fault)
 200         panic("arithmetic faults NYI...");
 201
 202     // compute exception restart address
 203     if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
 204         // traps...  skip faulting instruction
 205         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 206     } else {
 207         // fault, post fault at excepting instruction
 208         ipr[IPR_EXC_ADDR] = regs->pc;
 209     }
 210
 211     // jump to expection address (PAL PC bit set here as well...)
 212     if (!use_pc)
 213         regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
 214     else
 215         regs->npc = ipr[IPR_PAL_BASE] + pc;
 216
 217     // that's it! (orders of magnitude less painful than x86)
 218 }
 219
 220 bool AlphaISA::check_interrupts = false;
 221
 222 Fault
 223 ExecContext::hwrei()
 224 {
 225     uint64_t *ipr = regs.ipr;
 226
 227     if (!PC_PAL(regs.pc))
 228         return Unimplemented_Opcode_Fault;
 229
 230     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 231
 232     if (!misspeculating()) {
 233         kernelStats.hwrei();
 234
 235         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 236             AlphaISA::swap_palshadow(&regs, false);
 237
 238         AlphaISA::check_interrupts = true;
 239     }
 240
 241     // FIXME: XXX check for interrupts? XXX
 242     return No_Fault;
 243 }
 244
 245 uint64_t
 246 ExecContext::readIpr(int idx, Fault &fault)
 247 {
 248     uint64_t *ipr = regs.ipr;
 249     uint64_t retval = 0;        // return value, default 0
 250
 251     switch (idx) {
 252       case AlphaISA::IPR_PALtemp0:
 253       case AlphaISA::IPR_PALtemp1:
 254       case AlphaISA::IPR_PALtemp2:
 255       case AlphaISA::IPR_PALtemp3:
 256       case AlphaISA::IPR_PALtemp4:
 257       case AlphaISA::IPR_PALtemp5:
 258       case AlphaISA::IPR_PALtemp6:
 259       case AlphaISA::IPR_PALtemp7:
 260       case AlphaISA::IPR_PALtemp8:
 261       case AlphaISA::IPR_PALtemp9:
 262       case AlphaISA::IPR_PALtemp10:
 263       case AlphaISA::IPR_PALtemp11:
 264       case AlphaISA::IPR_PALtemp12:
 265       case AlphaISA::IPR_PALtemp13:
 266       case AlphaISA::IPR_PALtemp14:
 267       case AlphaISA::IPR_PALtemp15:
 268       case AlphaISA::IPR_PALtemp16:
 269       case AlphaISA::IPR_PALtemp17:
 270       case AlphaISA::IPR_PALtemp18:
 271       case AlphaISA::IPR_PALtemp19:
 272       case AlphaISA::IPR_PALtemp20:
 273       case AlphaISA::IPR_PALtemp21:
 274       case AlphaISA::IPR_PALtemp22:
 275       case AlphaISA::IPR_PALtemp23:
 276       case AlphaISA::IPR_PAL_BASE:
 277
 278       case AlphaISA::IPR_IVPTBR:
 279       case AlphaISA::IPR_DC_MODE:
 280       case AlphaISA::IPR_MAF_MODE:
 281       case AlphaISA::IPR_ISR:
 282       case AlphaISA::IPR_EXC_ADDR:
 283       case AlphaISA::IPR_IC_PERR_STAT:
 284       case AlphaISA::IPR_DC_PERR_STAT:
 285       case AlphaISA::IPR_MCSR:
 286       case AlphaISA::IPR_ASTRR:
 287       case AlphaISA::IPR_ASTER:
 288       case AlphaISA::IPR_SIRR:
 289       case AlphaISA::IPR_ICSR:
 290       case AlphaISA::IPR_ICM:
 291       case AlphaISA::IPR_DTB_CM:
 292       case AlphaISA::IPR_IPLR:
 293       case AlphaISA::IPR_INTID:
 294       case AlphaISA::IPR_PMCTR:
 295         // no side-effect
 296         retval = ipr[idx];
 297         break;
 298
 299       case AlphaISA::IPR_CC:
 300         retval |= ipr[idx] & ULL(0xffffffff00000000);
 301         retval |= curTick  & ULL(0x00000000ffffffff);
 302         break;
 303
 304       case AlphaISA::IPR_VA:
 305         // SFX: unlocks interrupt status registers
 306         retval = ipr[idx];
 307
 308         if (!misspeculating())
 309             regs.intrlock = false;
 310         break;
 311
 312       case AlphaISA::IPR_VA_FORM:
 313       case AlphaISA::IPR_MM_STAT:
 314       case AlphaISA::IPR_IFAULT_VA_FORM:
 315       case AlphaISA::IPR_EXC_MASK:
 316       case AlphaISA::IPR_EXC_SUM:
 317         retval = ipr[idx];
 318         break;
 319
 320       case AlphaISA::IPR_DTB_PTE:
 321         {
 322             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 323
 324             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 325             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 326             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 327             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 328             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 329             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 330             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 331         }
 332         break;
 333
 334         // write only registers
 335       case AlphaISA::IPR_HWINT_CLR:
 336       case AlphaISA::IPR_SL_XMIT:
 337       case AlphaISA::IPR_DC_FLUSH:
 338       case AlphaISA::IPR_IC_FLUSH:
 339       case AlphaISA::IPR_ALT_MODE:
 340       case AlphaISA::IPR_DTB_IA:
 341       case AlphaISA::IPR_DTB_IAP:
 342       case AlphaISA::IPR_ITB_IA:
 343       case AlphaISA::IPR_ITB_IAP:
 344         fault = Unimplemented_Opcode_Fault;
 345         break;
 346
 347       default:
 348         // invalid IPR
 349         fault = Unimplemented_Opcode_Fault;
 350         break;
 351     }
 352
 353     return retval;
 354 }
 355
 356 #ifdef DEBUG
 357 // Cause the simulator to break when changing to the following IPL
 358 int break_ipl = -1;
 359 #endif
 360
 361 Fault
 362 ExecContext::setIpr(int idx, uint64_t val)
 363 {
 364     uint64_t *ipr = regs.ipr;
 365     uint64_t old;
 366
 367     if (misspeculating())
 368         return No_Fault;
 369
 370     switch (idx) {
 371       case AlphaISA::IPR_PALtemp0:
 372       case AlphaISA::IPR_PALtemp1:
 373       case AlphaISA::IPR_PALtemp2:
 374       case AlphaISA::IPR_PALtemp3:
 375       case AlphaISA::IPR_PALtemp4:
 376       case AlphaISA::IPR_PALtemp5:
 377       case AlphaISA::IPR_PALtemp6:
 378       case AlphaISA::IPR_PALtemp7:
 379       case AlphaISA::IPR_PALtemp8:
 380       case AlphaISA::IPR_PALtemp9:
 381       case AlphaISA::IPR_PALtemp10:
 382       case AlphaISA::IPR_PALtemp11:
 383       case AlphaISA::IPR_PALtemp12:
 384       case AlphaISA::IPR_PALtemp13:
 385       case AlphaISA::IPR_PALtemp14:
 386       case AlphaISA::IPR_PALtemp15:
 387       case AlphaISA::IPR_PALtemp16:
 388       case AlphaISA::IPR_PALtemp17:
 389       case AlphaISA::IPR_PALtemp18:
 390       case AlphaISA::IPR_PALtemp19:
 391       case AlphaISA::IPR_PALtemp20:
 392       case AlphaISA::IPR_PALtemp21:
 393       case AlphaISA::IPR_PALtemp22:
 394       case AlphaISA::IPR_PAL_BASE:
 395       case AlphaISA::IPR_IC_PERR_STAT:
 396       case AlphaISA::IPR_DC_PERR_STAT:
 397       case AlphaISA::IPR_PMCTR:
 398         // write entire quad w/ no side-effect
 399         ipr[idx] = val;
 400         break;
 401
 402       case AlphaISA::IPR_CC_CTL:
 403         // This IPR resets the cycle counter.  We assume this only
 404         // happens once... let's verify that.
 405         assert(ipr[idx] == 0);
 406         ipr[idx] = 1;
 407         break;
 408
 409       case AlphaISA::IPR_CC:
 410         // This IPR only writes the upper 64 bits.  It's ok to write
 411         // all 64 here since we mask out the lower 32 in rpcc (see
 412         // isa_desc).
 413         ipr[idx] = val;
 414         break;
 415
 416       case AlphaISA::IPR_PALtemp23:
 417         // write entire quad w/ no side-effect
 418         old = ipr[idx];
 419         ipr[idx] = val;
 420         kernelStats.context(old, val);
 421         break;
 422
 423       case AlphaISA::IPR_DTB_PTE:
 424         // write entire quad w/ no side-effect, tag is forthcoming
 425         ipr[idx] = val;
 426         break;
 427
 428       case AlphaISA::IPR_EXC_ADDR:
 429         // second least significant bit in PC is always zero
 430         ipr[idx] = val & ~2;
 431         break;
 432
 433       case AlphaISA::IPR_ASTRR:
 434       case AlphaISA::IPR_ASTER:
 435         // only write least significant four bits - privilege mask
 436         ipr[idx] = val & 0xf;
 437         break;
 438
 439       case AlphaISA::IPR_IPLR:
 440 #ifdef DEBUG
 441         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 442             debug_break();
 443 #endif
 444
 445         // only write least significant five bits - interrupt level
 446         ipr[idx] = val & 0x1f;
 447         kernelStats.swpipl(ipr[idx]);
 448         break;
 449
 450       case AlphaISA::IPR_DTB_CM:
 451         kernelStats.mode((val & 0x18) != 0);
 452
 453       case AlphaISA::IPR_ICM:
 454         // only write two mode bits - processor mode
 455         ipr[idx] = val & 0x18;
 456         break;
 457
 458       case AlphaISA::IPR_ALT_MODE:
 459         // only write two mode bits - processor mode
 460         ipr[idx] = val & 0x18;
 461         break;
 462
 463       case AlphaISA::IPR_MCSR:
 464         // more here after optimization...
 465         ipr[idx] = val;
 466         break;
 467
 468       case AlphaISA::IPR_SIRR:
 469         // only write software interrupt mask
 470         ipr[idx] = val & 0x7fff0;
 471         break;
 472
 473       case AlphaISA::IPR_ICSR:
 474         ipr[idx] = val & ULL(0xffffff0300);
 475         break;
 476
 477       case AlphaISA::IPR_IVPTBR:
 478       case AlphaISA::IPR_MVPTBR:
 479         ipr[idx] = val & ULL(0xffffffffc0000000);
 480         break;
 481
 482       case AlphaISA::IPR_DC_TEST_CTL:
 483         ipr[idx] = val & 0x1ffb;
 484         break;
 485
 486       case AlphaISA::IPR_DC_MODE:
 487       case AlphaISA::IPR_MAF_MODE:
 488         ipr[idx] = val & 0x3f;
 489         break;
 490
 491       case AlphaISA::IPR_ITB_ASN:
 492         ipr[idx] = val & 0x7f0;
 493         break;
 494
 495       case AlphaISA::IPR_DTB_ASN:
 496         ipr[idx] = val & ULL(0xfe00000000000000);
 497         break;
 498
 499       case AlphaISA::IPR_EXC_SUM:
 500       case AlphaISA::IPR_EXC_MASK:
 501         // any write to this register clears it
 502         ipr[idx] = 0;
 503         break;
 504
 505       case AlphaISA::IPR_INTID:
 506       case AlphaISA::IPR_SL_RCV:
 507       case AlphaISA::IPR_MM_STAT:
 508       case AlphaISA::IPR_ITB_PTE_TEMP:
 509       case AlphaISA::IPR_DTB_PTE_TEMP:
 510         // read-only registers
 511         return Unimplemented_Opcode_Fault;
 512
 513       case AlphaISA::IPR_HWINT_CLR:
 514       case AlphaISA::IPR_SL_XMIT:
 515       case AlphaISA::IPR_DC_FLUSH:
 516       case AlphaISA::IPR_IC_FLUSH:
 517         // the following are write only
 518         ipr[idx] = val;
 519         break;
 520
 521       case AlphaISA::IPR_DTB_IA:
 522         // really a control write
 523         ipr[idx] = 0;
 524
 525         dtb->flushAll();
 526         break;
 527
 528       case AlphaISA::IPR_DTB_IAP:
 529         // really a control write
 530         ipr[idx] = 0;
 531
 532         dtb->flushProcesses();
 533         break;
 534
 535       case AlphaISA::IPR_DTB_IS:
 536         // really a control write
 537         ipr[idx] = val;
 538
 539         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 540         break;
 541
 542       case AlphaISA::IPR_DTB_TAG: {
 543           struct AlphaISA::PTE pte;
 544
 545           // FIXME: granularity hints NYI...
 546           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 547               panic("PTE GH field != 0");
 548
 549           // write entire quad
 550           ipr[idx] = val;
 551
 552           // construct PTE for new entry
 553           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 554           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 555           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 556           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 557           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 558           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 559           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 560
 561           // insert new TAG/PTE value into data TLB
 562           dtb->insert(val, pte);
 563       }
 564         break;
 565
 566       case AlphaISA::IPR_ITB_PTE: {
 567           struct AlphaISA::PTE pte;
 568
 569           // FIXME: granularity hints NYI...
 570           if (ITB_PTE_GH(val) != 0)
 571               panic("PTE GH field != 0");
 572
 573           // write entire quad
 574           ipr[idx] = val;
 575
 576           // construct PTE for new entry
 577           pte.ppn = ITB_PTE_PPN(val);
 578           pte.xre = ITB_PTE_XRE(val);
 579           pte.xwe = 0;
 580           pte.fonr = ITB_PTE_FONR(val);
 581           pte.fonw = ITB_PTE_FONW(val);
 582           pte.asma = ITB_PTE_ASMA(val);
 583           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 584
 585           // insert new TAG/PTE value into data TLB
 586           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 587       }
 588         break;
 589
 590       case AlphaISA::IPR_ITB_IA:
 591         // really a control write
 592         ipr[idx] = 0;
 593
 594         itb->flushAll();
 595         break;
 596
 597       case AlphaISA::IPR_ITB_IAP:
 598         // really a control write
 599         ipr[idx] = 0;
 600
 601         itb->flushProcesses();
 602         break;
 603
 604       case AlphaISA::IPR_ITB_IS:
 605         // really a control write
 606         ipr[idx] = val;
 607
 608         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 609         break;
 610
 611       default:
 612         // invalid IPR
 613         return Unimplemented_Opcode_Fault;
 614     }
 615
 616     // no error...
 617     return No_Fault;
 618 }
 619
 620 /**
 621  * Check for special simulator handling of specific PAL calls.
 622  * If return value is false, actual PAL call will be suppressed.
 623  */
 624 bool
 625 ExecContext::simPalCheck(int palFunc)
 626 {
 627     kernelStats.callpal(palFunc);
 628
 629     switch (palFunc) {
 630       case PAL::halt:
 631         halt();
 632         if (--System::numSystemsRunning == 0)
 633             new SimExitEvent("all cpus halted");
 634         break;
 635
 636       case PAL::bpt:
 637       case PAL::bugchk:
 638         if (system->breakpoint())
 639             return false;
 640         break;
 641     }
 642
 643     return true;
 644 }
 645
 646 //Forward instantiation for FastCPU object
 647 template
 648 void AlphaISA::processInterrupts(FastCPU *xc);
 649
 650 //Forward instantiation for FastCPU object
 651 template
 652 void AlphaISA::zeroRegisters(FastCPU *xc);
 653
 654 #endif // FULL_SYSTEM