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29 #include "arch/alpha/alpha_memory.hh"
30 #include "arch/alpha/isa_traits.hh"
31 #include "arch/alpha/osfpal.hh"
32 #include "base/kgdb.h"
33 #include "base/remote_gdb.hh"
34 #include "base/stats/events.hh"
35 #include "cpu/base.hh"
36 #include "cpu/exec_context.hh"
37 #include "cpu/fast/cpu.hh"
38 #include "kern/kernel_stats.hh"
39 #include "sim/debug.hh"
40 #include "sim/sim_events.hh"
46 ////////////////////////////////////////////////////////////////////////
51 AlphaISA::swap_palshadow(RegFile
*regs
, bool use_shadow
)
53 if (regs
->pal_shadow
== use_shadow
)
54 panic("swap_palshadow: wrong PAL shadow state");
56 regs
->pal_shadow
= use_shadow
;
58 for (int i
= 0; i
< NumIntRegs
; i
++) {
60 IntReg temp
= regs
->intRegFile
[i
];
61 regs
->intRegFile
[i
] = regs
->palregs
[i
];
62 regs
->palregs
[i
] = temp
;
67 ////////////////////////////////////////////////////////////////////////
69 // Machine dependent functions
72 AlphaISA::initCPU(RegFile
*regs
)
75 // CPU comes up with PAL regs enabled
76 swap_palshadow(regs
, true);
78 regs
->pc
= regs
->ipr
[IPR_PAL_BASE
] + fault_addr
[Reset_Fault
];
79 regs
->npc
= regs
->pc
+ sizeof(MachInst
);
82 ////////////////////////////////////////////////////////////////////////
84 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
87 AlphaISA::fault_addr
[Num_Faults
] = {
88 0x0000, /* No_Fault */
89 0x0001, /* Reset_Fault */
90 0x0401, /* Machine_Check_Fault */
91 0x0501, /* Arithmetic_Fault */
92 0x0101, /* Interrupt_Fault */
93 0x0201, /* Ndtb_Miss_Fault */
94 0x0281, /* Pdtb_Miss_Fault */
95 0x0301, /* Alignment_Fault */
96 0x0381, /* DTB_Fault_Fault */
97 0x0381, /* DTB_Acv_Fault */
98 0x0181, /* ITB_Miss_Fault */
99 0x0181, /* ITB_Fault_Fault */
100 0x0081, /* ITB_Acv_Fault */
101 0x0481, /* Unimplemented_Opcode_Fault */
102 0x0581, /* Fen_Fault */
103 0x2001, /* Pal_Fault */
104 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
107 const int AlphaISA::reg_redir
[AlphaISA::NumIntRegs
] = {
108 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
109 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
110 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
111 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
113 ////////////////////////////////////////////////////////////////////////
118 AlphaISA::initIPRs(RegFile
*regs
)
120 uint64_t *ipr
= regs
->ipr
;
122 bzero((char *)ipr
, NumInternalProcRegs
* sizeof(InternalProcReg
));
123 ipr
[IPR_PAL_BASE
] = PalBase
;
130 AlphaISA::processInterrupts(CPU
*cpu
)
132 //Check if there are any outstanding interrupts
133 //Handle the interrupts
136 IntReg
*ipr
= cpu
->getIprPtr();
138 cpu
->checkInterrupts
= false;
141 panic("asynchronous traps not implemented\n");
144 for (int i
= INTLEVEL_SOFTWARE_MIN
;
145 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
146 if (ipr
[IPR_SIRR
] & (ULL(1) << i
)) {
147 // See table 4-19 of the 21164 hardware reference
148 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
149 summary
|= (ULL(1) << i
);
154 uint64_t interrupts
= cpu
->intr_status();
157 for (int i
= INTLEVEL_EXTERNAL_MIN
;
158 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
159 if (interrupts
& (ULL(1) << i
)) {
160 // See table 4-19 of the 21164 hardware reference
162 summary
|= (ULL(1) << i
);
167 if (ipl
&& ipl
> ipr
[IPR_IPLR
]) {
168 ipr
[IPR_ISR
] = summary
;
169 ipr
[IPR_INTID
] = ipl
;
170 cpu
->trap(Interrupt_Fault
);
171 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
172 ipr
[IPR_IPLR
], ipl
, summary
);
179 AlphaISA::zeroRegisters(CPU
*cpu
)
181 // Insure ISA semantics
182 // (no longer very clean due to the change in setIntReg() in the
183 // cpu model. Consider changing later.)
184 cpu
->xc
->setIntReg(ZeroReg
, 0);
185 cpu
->xc
->setFloatRegDouble(ZeroReg
, 0.0);
189 ExecContext::ev5_trap(Fault fault
)
191 DPRINTF(Fault
, "Fault %s at PC: %#x\n", FaultName(fault
), regs
.pc
);
192 cpu
->recordEvent(csprintf("Fault %s", FaultName(fault
)));
194 assert(!misspeculating());
195 kernelStats
->fault(fault
);
197 if (fault
== Arithmetic_Fault
)
198 panic("Arithmetic traps are unimplemented!");
200 AlphaISA::InternalProcReg
*ipr
= regs
.ipr
;
202 // exception restart address
203 if (fault
!= Interrupt_Fault
|| !inPalMode())
204 ipr
[AlphaISA::IPR_EXC_ADDR
] = regs
.pc
;
206 if (fault
== Pal_Fault
|| fault
== Arithmetic_Fault
/* ||
207 fault == Interrupt_Fault && !inPalMode() */) {
208 // traps... skip faulting instruction
209 ipr
[AlphaISA::IPR_EXC_ADDR
] += 4;
213 AlphaISA::swap_palshadow(®s
, true);
215 regs
.pc
= ipr
[AlphaISA::IPR_PAL_BASE
] + AlphaISA::fault_addr
[fault
];
216 regs
.npc
= regs
.pc
+ sizeof(MachInst
);
221 AlphaISA::intr_post(RegFile
*regs
, Fault fault
, Addr pc
)
223 InternalProcReg
*ipr
= regs
->ipr
;
224 bool use_pc
= (fault
== No_Fault
);
226 if (fault
== Arithmetic_Fault
)
227 panic("arithmetic faults NYI...");
229 // compute exception restart address
230 if (use_pc
|| fault
== Pal_Fault
|| fault
== Arithmetic_Fault
) {
231 // traps... skip faulting instruction
232 ipr
[IPR_EXC_ADDR
] = regs
->pc
+ 4;
234 // fault, post fault at excepting instruction
235 ipr
[IPR_EXC_ADDR
] = regs
->pc
;
238 // jump to expection address (PAL PC bit set here as well...)
240 regs
->npc
= ipr
[IPR_PAL_BASE
] + fault_addr
[fault
];
242 regs
->npc
= ipr
[IPR_PAL_BASE
] + pc
;
244 // that's it! (orders of magnitude less painful than x86)
250 uint64_t *ipr
= regs
.ipr
;
253 return Unimplemented_Opcode_Fault
;
255 setNextPC(ipr
[AlphaISA::IPR_EXC_ADDR
]);
257 if (!misspeculating()) {
258 kernelStats
->hwrei();
260 if ((ipr
[AlphaISA::IPR_EXC_ADDR
] & 1) == 0)
261 AlphaISA::swap_palshadow(®s
, false);
263 cpu
->checkInterrupts
= true;
266 // FIXME: XXX check for interrupts? XXX
271 ExecContext::readIpr(int idx
, Fault
&fault
)
273 uint64_t *ipr
= regs
.ipr
;
274 uint64_t retval
= 0; // return value, default 0
277 case AlphaISA::IPR_PALtemp0
:
278 case AlphaISA::IPR_PALtemp1
:
279 case AlphaISA::IPR_PALtemp2
:
280 case AlphaISA::IPR_PALtemp3
:
281 case AlphaISA::IPR_PALtemp4
:
282 case AlphaISA::IPR_PALtemp5
:
283 case AlphaISA::IPR_PALtemp6
:
284 case AlphaISA::IPR_PALtemp7
:
285 case AlphaISA::IPR_PALtemp8
:
286 case AlphaISA::IPR_PALtemp9
:
287 case AlphaISA::IPR_PALtemp10
:
288 case AlphaISA::IPR_PALtemp11
:
289 case AlphaISA::IPR_PALtemp12
:
290 case AlphaISA::IPR_PALtemp13
:
291 case AlphaISA::IPR_PALtemp14
:
292 case AlphaISA::IPR_PALtemp15
:
293 case AlphaISA::IPR_PALtemp16
:
294 case AlphaISA::IPR_PALtemp17
:
295 case AlphaISA::IPR_PALtemp18
:
296 case AlphaISA::IPR_PALtemp19
:
297 case AlphaISA::IPR_PALtemp20
:
298 case AlphaISA::IPR_PALtemp21
:
299 case AlphaISA::IPR_PALtemp22
:
300 case AlphaISA::IPR_PALtemp23
:
301 case AlphaISA::IPR_PAL_BASE
:
303 case AlphaISA::IPR_IVPTBR
:
304 case AlphaISA::IPR_DC_MODE
:
305 case AlphaISA::IPR_MAF_MODE
:
306 case AlphaISA::IPR_ISR
:
307 case AlphaISA::IPR_EXC_ADDR
:
308 case AlphaISA::IPR_IC_PERR_STAT
:
309 case AlphaISA::IPR_DC_PERR_STAT
:
310 case AlphaISA::IPR_MCSR
:
311 case AlphaISA::IPR_ASTRR
:
312 case AlphaISA::IPR_ASTER
:
313 case AlphaISA::IPR_SIRR
:
314 case AlphaISA::IPR_ICSR
:
315 case AlphaISA::IPR_ICM
:
316 case AlphaISA::IPR_DTB_CM
:
317 case AlphaISA::IPR_IPLR
:
318 case AlphaISA::IPR_INTID
:
319 case AlphaISA::IPR_PMCTR
:
324 case AlphaISA::IPR_CC
:
325 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
326 retval
|= cpu
->curCycle() & ULL(0x00000000ffffffff);
329 case AlphaISA::IPR_VA
:
333 case AlphaISA::IPR_VA_FORM
:
334 case AlphaISA::IPR_MM_STAT
:
335 case AlphaISA::IPR_IFAULT_VA_FORM
:
336 case AlphaISA::IPR_EXC_MASK
:
337 case AlphaISA::IPR_EXC_SUM
:
341 case AlphaISA::IPR_DTB_PTE
:
343 AlphaISA::PTE
&pte
= dtb
->index(!misspeculating());
345 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
346 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
347 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
348 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
349 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
350 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
351 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
355 // write only registers
356 case AlphaISA::IPR_HWINT_CLR
:
357 case AlphaISA::IPR_SL_XMIT
:
358 case AlphaISA::IPR_DC_FLUSH
:
359 case AlphaISA::IPR_IC_FLUSH
:
360 case AlphaISA::IPR_ALT_MODE
:
361 case AlphaISA::IPR_DTB_IA
:
362 case AlphaISA::IPR_DTB_IAP
:
363 case AlphaISA::IPR_ITB_IA
:
364 case AlphaISA::IPR_ITB_IAP
:
365 fault
= Unimplemented_Opcode_Fault
;
370 fault
= Unimplemented_Opcode_Fault
;
378 // Cause the simulator to break when changing to the following IPL
383 ExecContext::setIpr(int idx
, uint64_t val
)
385 uint64_t *ipr
= regs
.ipr
;
388 if (misspeculating())
392 case AlphaISA::IPR_PALtemp0
:
393 case AlphaISA::IPR_PALtemp1
:
394 case AlphaISA::IPR_PALtemp2
:
395 case AlphaISA::IPR_PALtemp3
:
396 case AlphaISA::IPR_PALtemp4
:
397 case AlphaISA::IPR_PALtemp5
:
398 case AlphaISA::IPR_PALtemp6
:
399 case AlphaISA::IPR_PALtemp7
:
400 case AlphaISA::IPR_PALtemp8
:
401 case AlphaISA::IPR_PALtemp9
:
402 case AlphaISA::IPR_PALtemp10
:
403 case AlphaISA::IPR_PALtemp11
:
404 case AlphaISA::IPR_PALtemp12
:
405 case AlphaISA::IPR_PALtemp13
:
406 case AlphaISA::IPR_PALtemp14
:
407 case AlphaISA::IPR_PALtemp15
:
408 case AlphaISA::IPR_PALtemp16
:
409 case AlphaISA::IPR_PALtemp17
:
410 case AlphaISA::IPR_PALtemp18
:
411 case AlphaISA::IPR_PALtemp19
:
412 case AlphaISA::IPR_PALtemp20
:
413 case AlphaISA::IPR_PALtemp21
:
414 case AlphaISA::IPR_PALtemp22
:
415 case AlphaISA::IPR_PAL_BASE
:
416 case AlphaISA::IPR_IC_PERR_STAT
:
417 case AlphaISA::IPR_DC_PERR_STAT
:
418 case AlphaISA::IPR_PMCTR
:
419 // write entire quad w/ no side-effect
423 case AlphaISA::IPR_CC_CTL
:
424 // This IPR resets the cycle counter. We assume this only
425 // happens once... let's verify that.
426 assert(ipr
[idx
] == 0);
430 case AlphaISA::IPR_CC
:
431 // This IPR only writes the upper 64 bits. It's ok to write
432 // all 64 here since we mask out the lower 32 in rpcc (see
437 case AlphaISA::IPR_PALtemp23
:
438 // write entire quad w/ no side-effect
441 kernelStats
->context(old
, val
);
444 case AlphaISA::IPR_DTB_PTE
:
445 // write entire quad w/ no side-effect, tag is forthcoming
449 case AlphaISA::IPR_EXC_ADDR
:
450 // second least significant bit in PC is always zero
454 case AlphaISA::IPR_ASTRR
:
455 case AlphaISA::IPR_ASTER
:
456 // only write least significant four bits - privilege mask
457 ipr
[idx
] = val
& 0xf;
460 case AlphaISA::IPR_IPLR
:
462 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
466 // only write least significant five bits - interrupt level
467 ipr
[idx
] = val
& 0x1f;
468 kernelStats
->swpipl(ipr
[idx
]);
471 case AlphaISA::IPR_DTB_CM
:
473 kernelStats
->mode(Kernel::user
);
475 kernelStats
->mode(Kernel::kernel
);
477 case AlphaISA::IPR_ICM
:
478 // only write two mode bits - processor mode
479 ipr
[idx
] = val
& 0x18;
482 case AlphaISA::IPR_ALT_MODE
:
483 // only write two mode bits - processor mode
484 ipr
[idx
] = val
& 0x18;
487 case AlphaISA::IPR_MCSR
:
488 // more here after optimization...
492 case AlphaISA::IPR_SIRR
:
493 // only write software interrupt mask
494 ipr
[idx
] = val
& 0x7fff0;
497 case AlphaISA::IPR_ICSR
:
498 ipr
[idx
] = val
& ULL(0xffffff0300);
501 case AlphaISA::IPR_IVPTBR
:
502 case AlphaISA::IPR_MVPTBR
:
503 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
506 case AlphaISA::IPR_DC_TEST_CTL
:
507 ipr
[idx
] = val
& 0x1ffb;
510 case AlphaISA::IPR_DC_MODE
:
511 case AlphaISA::IPR_MAF_MODE
:
512 ipr
[idx
] = val
& 0x3f;
515 case AlphaISA::IPR_ITB_ASN
:
516 ipr
[idx
] = val
& 0x7f0;
519 case AlphaISA::IPR_DTB_ASN
:
520 ipr
[idx
] = val
& ULL(0xfe00000000000000);
523 case AlphaISA::IPR_EXC_SUM
:
524 case AlphaISA::IPR_EXC_MASK
:
525 // any write to this register clears it
529 case AlphaISA::IPR_INTID
:
530 case AlphaISA::IPR_SL_RCV
:
531 case AlphaISA::IPR_MM_STAT
:
532 case AlphaISA::IPR_ITB_PTE_TEMP
:
533 case AlphaISA::IPR_DTB_PTE_TEMP
:
534 // read-only registers
535 return Unimplemented_Opcode_Fault
;
537 case AlphaISA::IPR_HWINT_CLR
:
538 case AlphaISA::IPR_SL_XMIT
:
539 case AlphaISA::IPR_DC_FLUSH
:
540 case AlphaISA::IPR_IC_FLUSH
:
541 // the following are write only
545 case AlphaISA::IPR_DTB_IA
:
546 // really a control write
552 case AlphaISA::IPR_DTB_IAP
:
553 // really a control write
556 dtb
->flushProcesses();
559 case AlphaISA::IPR_DTB_IS
:
560 // really a control write
563 dtb
->flushAddr(val
, DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
566 case AlphaISA::IPR_DTB_TAG
: {
567 struct AlphaISA::PTE pte
;
569 // FIXME: granularity hints NYI...
570 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
571 panic("PTE GH field != 0");
576 // construct PTE for new entry
577 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
578 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
579 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
580 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
581 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
582 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
583 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
585 // insert new TAG/PTE value into data TLB
586 dtb
->insert(val
, pte
);
590 case AlphaISA::IPR_ITB_PTE
: {
591 struct AlphaISA::PTE pte
;
593 // FIXME: granularity hints NYI...
594 if (ITB_PTE_GH(val
) != 0)
595 panic("PTE GH field != 0");
600 // construct PTE for new entry
601 pte
.ppn
= ITB_PTE_PPN(val
);
602 pte
.xre
= ITB_PTE_XRE(val
);
604 pte
.fonr
= ITB_PTE_FONR(val
);
605 pte
.fonw
= ITB_PTE_FONW(val
);
606 pte
.asma
= ITB_PTE_ASMA(val
);
607 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
609 // insert new TAG/PTE value into data TLB
610 itb
->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
614 case AlphaISA::IPR_ITB_IA
:
615 // really a control write
621 case AlphaISA::IPR_ITB_IAP
:
622 // really a control write
625 itb
->flushProcesses();
628 case AlphaISA::IPR_ITB_IS
:
629 // really a control write
632 itb
->flushAddr(val
, ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
637 return Unimplemented_Opcode_Fault
;
645 * Check for special simulator handling of specific PAL calls.
646 * If return value is false, actual PAL call will be suppressed.
649 ExecContext::simPalCheck(int palFunc
)
651 kernelStats
->callpal(palFunc
);
656 if (--System::numSystemsRunning
== 0)
657 new SimExitEvent("all cpus halted");
662 if (system
->breakpoint())
670 //Forward instantiation for FastCPU object
672 void AlphaISA::processInterrupts(FastCPU
*xc
);
674 //Forward instantiation for FastCPU object
676 void AlphaISA::zeroRegisters(FastCPU
*xc
);
678 #endif // FULL_SYSTEM