arch/alpha/ev5.cc

   1 /* $Id$ */
   2
   3 #include "arch/alpha/alpha_memory.hh"
   4 #include "arch/alpha/isa_traits.hh"
   5 #include "arch/alpha/osfpal.hh"
   6 #include "base/kgdb.h"
   7 #include "base/remote_gdb.hh"
   8 #include "base/stats/events.hh"
   9 #include "cpu/base_cpu.hh"
  10 #include "cpu/exec_context.hh"
  11 #include "cpu/fast_cpu/fast_cpu.hh"
  12 #include "sim/debug.hh"
  13 #include "sim/sim_events.hh"
  14
  15 #ifdef FULL_SYSTEM
  16
  17 #ifndef SYSTEM_EV5
  18 #error This code is only valid for EV5 systems
  19 #endif
  20
  21 ////////////////////////////////////////////////////////////////////////
  22 //
  23 //
  24 //
  25 void
  26 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  27 {
  28     if (regs->pal_shadow == use_shadow)
  29         panic("swap_palshadow: wrong PAL shadow state");
  30
  31     regs->pal_shadow = use_shadow;
  32
  33     for (int i = 0; i < NumIntRegs; i++) {
  34         if (reg_redir[i]) {
  35             IntReg temp = regs->intRegFile[i];
  36             regs->intRegFile[i] = regs->palregs[i];
  37             regs->palregs[i] = temp;
  38         }
  39     }
  40 }
  41
  42 ////////////////////////////////////////////////////////////////////////
  43 //
  44 //  Machine dependent functions
  45 //
  46 void
  47 AlphaISA::initCPU(RegFile *regs)
  48 {
  49     initIPRs(regs);
  50     // CPU comes up with PAL regs enabled
  51     swap_palshadow(regs, true);
  52
  53     regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
  54     regs->npc = regs->pc + sizeof(MachInst);
  55 }
  56
  57 ////////////////////////////////////////////////////////////////////////
  58 //
  59 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
  60 //
  61 Addr
  62 AlphaISA::fault_addr[Num_Faults] = {
  63     0x0000,     /* No_Fault */
  64     0x0001,     /* Reset_Fault */
  65     0x0401,     /* Machine_Check_Fault */
  66     0x0501,     /* Arithmetic_Fault */
  67     0x0101,     /* Interrupt_Fault */
  68     0x0201,     /* Ndtb_Miss_Fault */
  69     0x0281,     /* Pdtb_Miss_Fault */
  70     0x0301,     /* Alignment_Fault */
  71     0x0381,     /* DTB_Fault_Fault */
  72     0x0381,     /* DTB_Acv_Fault */
  73     0x0181,     /* ITB_Miss_Fault */
  74     0x0181,     /* ITB_Fault_Fault */
  75     0x0081,     /* ITB_Acv_Fault */
  76     0x0481,     /* Unimplemented_Opcode_Fault */
  77     0x0581,     /* Fen_Fault */
  78     0x2001,     /* Pal_Fault */
  79     0x0501,     /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
  80 };
  81
  82 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  83     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  84     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  85     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  86     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  87
  88 ////////////////////////////////////////////////////////////////////////
  89 //
  90 //
  91 //
  92 void
  93 AlphaISA::initIPRs(RegFile *regs)
  94 {
  95     uint64_t *ipr = regs->ipr;
  96
  97     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
  98     ipr[IPR_PAL_BASE] = PAL_BASE;
  99     ipr[IPR_MCSR] = 0x6;
 100 }
 101
 102
 103 template <class XC>
 104 void
 105 AlphaISA::processInterrupts(XC *xc)
 106 {
 107     //Check if there are any outstanding interrupts
 108     //Handle the interrupts
 109     int ipl = 0;
 110     int summary = 0;
 111     IntReg *ipr = xc->getIprPtr();
 112
 113     check_interrupts = 0;
 114
 115     if (ipr[IPR_ASTRR])
 116         panic("asynchronous traps not implemented\n");
 117
 118     if (ipr[IPR_SIRR]) {
 119         for (int i = INTLEVEL_SOFTWARE_MIN;
 120              i < INTLEVEL_SOFTWARE_MAX; i++) {
 121             if (ipr[IPR_SIRR] & (ULL(1) << i)) {
 122                 // See table 4-19 of the 21164 hardware reference
 123                 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 124                 summary |= (ULL(1) << i);
 125             }
 126         }
 127     }
 128
 129     uint64_t interrupts = xc->intr_status();
 130
 131     if (interrupts) {
 132         for (int i = INTLEVEL_EXTERNAL_MIN;
 133              i < INTLEVEL_EXTERNAL_MAX; i++) {
 134             if (interrupts & (ULL(1) << i)) {
 135                 // See table 4-19 of the 21164 hardware reference
 136                 ipl = i;
 137                 summary |= (ULL(1) << i);
 138             }
 139         }
 140     }
 141
 142     if (ipl && ipl > ipr[IPR_IPLR]) {
 143         ipr[IPR_ISR] = summary;
 144         ipr[IPR_INTID] = ipl;
 145         xc->trap(Interrupt_Fault);
 146         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 147                 ipr[IPR_IPLR], ipl, summary);
 148     }
 149
 150 }
 151
 152 template <class XC>
 153 void
 154 AlphaISA::zeroRegisters(XC *xc)
 155 {
 156     // Insure ISA semantics
 157     // (no longer very clean due to the change in setIntReg() in the
 158     // cpu model.  Consider changing later.)
 159     xc->xc->setIntReg(ZeroReg, 0);
 160     xc->xc->setFloatRegDouble(ZeroReg, 0.0);
 161 }
 162
 163 void
 164 ExecContext::ev5_trap(Fault fault)
 165 {
 166     DPRINTF(Fault, "Fault %s\n", FaultName(fault));
 167     cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
 168
 169     assert(!misspeculating());
 170     kernelStats.fault(fault);
 171
 172     if (fault == Arithmetic_Fault)
 173         panic("Arithmetic traps are unimplemented!");
 174
 175     AlphaISA::InternalProcReg *ipr = regs.ipr;
 176
 177     // exception restart address
 178     if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
 179         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 180
 181     if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
 182         fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
 183         // traps...  skip faulting instruction
 184         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 185     }
 186
 187     if (!PC_PAL(regs.pc))
 188         AlphaISA::swap_palshadow(&regs, true);
 189
 190     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
 191     regs.npc = regs.pc + sizeof(MachInst);
 192 }
 193
 194
 195 void
 196 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 197 {
 198     InternalProcReg *ipr = regs->ipr;
 199     bool use_pc = (fault == No_Fault);
 200
 201     if (fault == Arithmetic_Fault)
 202         panic("arithmetic faults NYI...");
 203
 204     // compute exception restart address
 205     if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
 206         // traps...  skip faulting instruction
 207         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 208     } else {
 209         // fault, post fault at excepting instruction
 210         ipr[IPR_EXC_ADDR] = regs->pc;
 211     }
 212
 213     // jump to expection address (PAL PC bit set here as well...)
 214     if (!use_pc)
 215         regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
 216     else
 217         regs->npc = ipr[IPR_PAL_BASE] + pc;
 218
 219     // that's it! (orders of magnitude less painful than x86)
 220 }
 221
 222 bool AlphaISA::check_interrupts = false;
 223
 224 Fault
 225 ExecContext::hwrei()
 226 {
 227     uint64_t *ipr = regs.ipr;
 228
 229     if (!PC_PAL(regs.pc))
 230         return Unimplemented_Opcode_Fault;
 231
 232     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 233
 234     if (!misspeculating()) {
 235         kernelStats.hwrei();
 236
 237         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 238             AlphaISA::swap_palshadow(&regs, false);
 239
 240         AlphaISA::check_interrupts = true;
 241     }
 242
 243     // FIXME: XXX check for interrupts? XXX
 244     return No_Fault;
 245 }
 246
 247 uint64_t
 248 ExecContext::readIpr(int idx, Fault &fault)
 249 {
 250     uint64_t *ipr = regs.ipr;
 251     uint64_t retval = 0;        // return value, default 0
 252
 253     switch (idx) {
 254       case AlphaISA::IPR_PALtemp0:
 255       case AlphaISA::IPR_PALtemp1:
 256       case AlphaISA::IPR_PALtemp2:
 257       case AlphaISA::IPR_PALtemp3:
 258       case AlphaISA::IPR_PALtemp4:
 259       case AlphaISA::IPR_PALtemp5:
 260       case AlphaISA::IPR_PALtemp6:
 261       case AlphaISA::IPR_PALtemp7:
 262       case AlphaISA::IPR_PALtemp8:
 263       case AlphaISA::IPR_PALtemp9:
 264       case AlphaISA::IPR_PALtemp10:
 265       case AlphaISA::IPR_PALtemp11:
 266       case AlphaISA::IPR_PALtemp12:
 267       case AlphaISA::IPR_PALtemp13:
 268       case AlphaISA::IPR_PALtemp14:
 269       case AlphaISA::IPR_PALtemp15:
 270       case AlphaISA::IPR_PALtemp16:
 271       case AlphaISA::IPR_PALtemp17:
 272       case AlphaISA::IPR_PALtemp18:
 273       case AlphaISA::IPR_PALtemp19:
 274       case AlphaISA::IPR_PALtemp20:
 275       case AlphaISA::IPR_PALtemp21:
 276       case AlphaISA::IPR_PALtemp22:
 277       case AlphaISA::IPR_PALtemp23:
 278       case AlphaISA::IPR_PAL_BASE:
 279
 280       case AlphaISA::IPR_IVPTBR:
 281       case AlphaISA::IPR_DC_MODE:
 282       case AlphaISA::IPR_MAF_MODE:
 283       case AlphaISA::IPR_ISR:
 284       case AlphaISA::IPR_EXC_ADDR:
 285       case AlphaISA::IPR_IC_PERR_STAT:
 286       case AlphaISA::IPR_DC_PERR_STAT:
 287       case AlphaISA::IPR_MCSR:
 288       case AlphaISA::IPR_ASTRR:
 289       case AlphaISA::IPR_ASTER:
 290       case AlphaISA::IPR_SIRR:
 291       case AlphaISA::IPR_ICSR:
 292       case AlphaISA::IPR_ICM:
 293       case AlphaISA::IPR_DTB_CM:
 294       case AlphaISA::IPR_IPLR:
 295       case AlphaISA::IPR_INTID:
 296       case AlphaISA::IPR_PMCTR:
 297         // no side-effect
 298         retval = ipr[idx];
 299         break;
 300
 301       case AlphaISA::IPR_CC:
 302         retval |= ipr[idx] & ULL(0xffffffff00000000);
 303         retval |= curTick  & ULL(0x00000000ffffffff);
 304         break;
 305
 306       case AlphaISA::IPR_VA:
 307         retval = ipr[idx];
 308         break;
 309
 310       case AlphaISA::IPR_VA_FORM:
 311       case AlphaISA::IPR_MM_STAT:
 312       case AlphaISA::IPR_IFAULT_VA_FORM:
 313       case AlphaISA::IPR_EXC_MASK:
 314       case AlphaISA::IPR_EXC_SUM:
 315         retval = ipr[idx];
 316         break;
 317
 318       case AlphaISA::IPR_DTB_PTE:
 319         {
 320             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 321
 322             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 323             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 324             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 325             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 326             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 327             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 328             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 329         }
 330         break;
 331
 332         // write only registers
 333       case AlphaISA::IPR_HWINT_CLR:
 334       case AlphaISA::IPR_SL_XMIT:
 335       case AlphaISA::IPR_DC_FLUSH:
 336       case AlphaISA::IPR_IC_FLUSH:
 337       case AlphaISA::IPR_ALT_MODE:
 338       case AlphaISA::IPR_DTB_IA:
 339       case AlphaISA::IPR_DTB_IAP:
 340       case AlphaISA::IPR_ITB_IA:
 341       case AlphaISA::IPR_ITB_IAP:
 342         fault = Unimplemented_Opcode_Fault;
 343         break;
 344
 345       default:
 346         // invalid IPR
 347         fault = Unimplemented_Opcode_Fault;
 348         break;
 349     }
 350
 351     return retval;
 352 }
 353
 354 #ifdef DEBUG
 355 // Cause the simulator to break when changing to the following IPL
 356 int break_ipl = -1;
 357 #endif
 358
 359 Fault
 360 ExecContext::setIpr(int idx, uint64_t val)
 361 {
 362     uint64_t *ipr = regs.ipr;
 363     uint64_t old;
 364
 365     if (misspeculating())
 366         return No_Fault;
 367
 368     switch (idx) {
 369       case AlphaISA::IPR_PALtemp0:
 370       case AlphaISA::IPR_PALtemp1:
 371       case AlphaISA::IPR_PALtemp2:
 372       case AlphaISA::IPR_PALtemp3:
 373       case AlphaISA::IPR_PALtemp4:
 374       case AlphaISA::IPR_PALtemp5:
 375       case AlphaISA::IPR_PALtemp6:
 376       case AlphaISA::IPR_PALtemp7:
 377       case AlphaISA::IPR_PALtemp8:
 378       case AlphaISA::IPR_PALtemp9:
 379       case AlphaISA::IPR_PALtemp10:
 380       case AlphaISA::IPR_PALtemp11:
 381       case AlphaISA::IPR_PALtemp12:
 382       case AlphaISA::IPR_PALtemp13:
 383       case AlphaISA::IPR_PALtemp14:
 384       case AlphaISA::IPR_PALtemp15:
 385       case AlphaISA::IPR_PALtemp16:
 386       case AlphaISA::IPR_PALtemp17:
 387       case AlphaISA::IPR_PALtemp18:
 388       case AlphaISA::IPR_PALtemp19:
 389       case AlphaISA::IPR_PALtemp20:
 390       case AlphaISA::IPR_PALtemp21:
 391       case AlphaISA::IPR_PALtemp22:
 392       case AlphaISA::IPR_PAL_BASE:
 393       case AlphaISA::IPR_IC_PERR_STAT:
 394       case AlphaISA::IPR_DC_PERR_STAT:
 395       case AlphaISA::IPR_PMCTR:
 396         // write entire quad w/ no side-effect
 397         ipr[idx] = val;
 398         break;
 399
 400       case AlphaISA::IPR_CC_CTL:
 401         // This IPR resets the cycle counter.  We assume this only
 402         // happens once... let's verify that.
 403         assert(ipr[idx] == 0);
 404         ipr[idx] = 1;
 405         break;
 406
 407       case AlphaISA::IPR_CC:
 408         // This IPR only writes the upper 64 bits.  It's ok to write
 409         // all 64 here since we mask out the lower 32 in rpcc (see
 410         // isa_desc).
 411         ipr[idx] = val;
 412         break;
 413
 414       case AlphaISA::IPR_PALtemp23:
 415         // write entire quad w/ no side-effect
 416         old = ipr[idx];
 417         ipr[idx] = val;
 418         kernelStats.context(old, val);
 419         break;
 420
 421       case AlphaISA::IPR_DTB_PTE:
 422         // write entire quad w/ no side-effect, tag is forthcoming
 423         ipr[idx] = val;
 424         break;
 425
 426       case AlphaISA::IPR_EXC_ADDR:
 427         // second least significant bit in PC is always zero
 428         ipr[idx] = val & ~2;
 429         break;
 430
 431       case AlphaISA::IPR_ASTRR:
 432       case AlphaISA::IPR_ASTER:
 433         // only write least significant four bits - privilege mask
 434         ipr[idx] = val & 0xf;
 435         break;
 436
 437       case AlphaISA::IPR_IPLR:
 438 #ifdef DEBUG
 439         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 440             debug_break();
 441 #endif
 442
 443         // only write least significant five bits - interrupt level
 444         ipr[idx] = val & 0x1f;
 445         kernelStats.swpipl(ipr[idx]);
 446         break;
 447
 448       case AlphaISA::IPR_DTB_CM:
 449         kernelStats.mode((val & 0x18) != 0);
 450
 451       case AlphaISA::IPR_ICM:
 452         // only write two mode bits - processor mode
 453         ipr[idx] = val & 0x18;
 454         break;
 455
 456       case AlphaISA::IPR_ALT_MODE:
 457         // only write two mode bits - processor mode
 458         ipr[idx] = val & 0x18;
 459         break;
 460
 461       case AlphaISA::IPR_MCSR:
 462         // more here after optimization...
 463         ipr[idx] = val;
 464         break;
 465
 466       case AlphaISA::IPR_SIRR:
 467         // only write software interrupt mask
 468         ipr[idx] = val & 0x7fff0;
 469         break;
 470
 471       case AlphaISA::IPR_ICSR:
 472         ipr[idx] = val & ULL(0xffffff0300);
 473         break;
 474
 475       case AlphaISA::IPR_IVPTBR:
 476       case AlphaISA::IPR_MVPTBR:
 477         ipr[idx] = val & ULL(0xffffffffc0000000);
 478         break;
 479
 480       case AlphaISA::IPR_DC_TEST_CTL:
 481         ipr[idx] = val & 0x1ffb;
 482         break;
 483
 484       case AlphaISA::IPR_DC_MODE:
 485       case AlphaISA::IPR_MAF_MODE:
 486         ipr[idx] = val & 0x3f;
 487         break;
 488
 489       case AlphaISA::IPR_ITB_ASN:
 490         ipr[idx] = val & 0x7f0;
 491         break;
 492
 493       case AlphaISA::IPR_DTB_ASN:
 494         ipr[idx] = val & ULL(0xfe00000000000000);
 495         break;
 496
 497       case AlphaISA::IPR_EXC_SUM:
 498       case AlphaISA::IPR_EXC_MASK:
 499         // any write to this register clears it
 500         ipr[idx] = 0;
 501         break;
 502
 503       case AlphaISA::IPR_INTID:
 504       case AlphaISA::IPR_SL_RCV:
 505       case AlphaISA::IPR_MM_STAT:
 506       case AlphaISA::IPR_ITB_PTE_TEMP:
 507       case AlphaISA::IPR_DTB_PTE_TEMP:
 508         // read-only registers
 509         return Unimplemented_Opcode_Fault;
 510
 511       case AlphaISA::IPR_HWINT_CLR:
 512       case AlphaISA::IPR_SL_XMIT:
 513       case AlphaISA::IPR_DC_FLUSH:
 514       case AlphaISA::IPR_IC_FLUSH:
 515         // the following are write only
 516         ipr[idx] = val;
 517         break;
 518
 519       case AlphaISA::IPR_DTB_IA:
 520         // really a control write
 521         ipr[idx] = 0;
 522
 523         dtb->flushAll();
 524         break;
 525
 526       case AlphaISA::IPR_DTB_IAP:
 527         // really a control write
 528         ipr[idx] = 0;
 529
 530         dtb->flushProcesses();
 531         break;
 532
 533       case AlphaISA::IPR_DTB_IS:
 534         // really a control write
 535         ipr[idx] = val;
 536
 537         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 538         break;
 539
 540       case AlphaISA::IPR_DTB_TAG: {
 541           struct AlphaISA::PTE pte;
 542
 543           // FIXME: granularity hints NYI...
 544           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 545               panic("PTE GH field != 0");
 546
 547           // write entire quad
 548           ipr[idx] = val;
 549
 550           // construct PTE for new entry
 551           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 552           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 553           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 554           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 555           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 556           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 557           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 558
 559           // insert new TAG/PTE value into data TLB
 560           dtb->insert(val, pte);
 561       }
 562         break;
 563
 564       case AlphaISA::IPR_ITB_PTE: {
 565           struct AlphaISA::PTE pte;
 566
 567           // FIXME: granularity hints NYI...
 568           if (ITB_PTE_GH(val) != 0)
 569               panic("PTE GH field != 0");
 570
 571           // write entire quad
 572           ipr[idx] = val;
 573
 574           // construct PTE for new entry
 575           pte.ppn = ITB_PTE_PPN(val);
 576           pte.xre = ITB_PTE_XRE(val);
 577           pte.xwe = 0;
 578           pte.fonr = ITB_PTE_FONR(val);
 579           pte.fonw = ITB_PTE_FONW(val);
 580           pte.asma = ITB_PTE_ASMA(val);
 581           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 582
 583           // insert new TAG/PTE value into data TLB
 584           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 585       }
 586         break;
 587
 588       case AlphaISA::IPR_ITB_IA:
 589         // really a control write
 590         ipr[idx] = 0;
 591
 592         itb->flushAll();
 593         break;
 594
 595       case AlphaISA::IPR_ITB_IAP:
 596         // really a control write
 597         ipr[idx] = 0;
 598
 599         itb->flushProcesses();
 600         break;
 601
 602       case AlphaISA::IPR_ITB_IS:
 603         // really a control write
 604         ipr[idx] = val;
 605
 606         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 607         break;
 608
 609       default:
 610         // invalid IPR
 611         return Unimplemented_Opcode_Fault;
 612     }
 613
 614     // no error...
 615     return No_Fault;
 616 }
 617
 618 /**
 619  * Check for special simulator handling of specific PAL calls.
 620  * If return value is false, actual PAL call will be suppressed.
 621  */
 622 bool
 623 ExecContext::simPalCheck(int palFunc)
 624 {
 625     kernelStats.callpal(palFunc);
 626
 627     switch (palFunc) {
 628       case PAL::halt:
 629         halt();
 630         if (--System::numSystemsRunning == 0)
 631             new SimExitEvent("all cpus halted");
 632         break;
 633
 634       case PAL::bpt:
 635       case PAL::bugchk:
 636         if (system->breakpoint())
 637             return false;
 638         break;
 639     }
 640
 641     return true;
 642 }
 643
 644 //Forward instantiation for FastCPU object
 645 template
 646 void AlphaISA::processInterrupts(FastCPU *xc);
 647
 648 //Forward instantiation for FastCPU object
 649 template
 650 void AlphaISA::zeroRegisters(FastCPU *xc);
 651
 652 #endif // FULL_SYSTEM