3 #include "targetarch/alpha_memory.hh"
4 #include "sim/annotation.hh"
6 #include "sim/debug.hh"
8 #include "cpu/exec_context.hh"
9 #include "sim/sim_events.hh"
10 #include "targetarch/isa_traits.hh"
11 #include "base/remote_gdb.hh"
12 #include "base/kgdb.h" // for ALPHA_KENTRY_IF
13 #include "targetarch/osfpal.hh"
18 #error This code is only valid for EV5 systems
21 ////////////////////////////////////////////////////////////////////////
26 AlphaISA::swap_palshadow(RegFile
*regs
, bool use_shadow
)
28 if (regs
->pal_shadow
== use_shadow
)
29 panic("swap_palshadow: wrong PAL shadow state");
31 regs
->pal_shadow
= use_shadow
;
33 for (int i
= 0; i
< NumIntRegs
; i
++) {
35 IntReg temp
= regs
->intRegFile
[i
];
36 regs
->intRegFile
[i
] = regs
->palregs
[i
];
37 regs
->palregs
[i
] = temp
;
42 ////////////////////////////////////////////////////////////////////////
44 // Machine dependent functions
47 AlphaISA::initCPU(RegFile
*regs
)
50 // CPU comes up with PAL regs enabled
51 swap_palshadow(regs
, true);
53 regs
->pc
= regs
->ipr
[IPR_PAL_BASE
] + fault_addr
[Reset_Fault
];
54 regs
->npc
= regs
->pc
+ sizeof(MachInst
);
57 ////////////////////////////////////////////////////////////////////////
59 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
62 AlphaISA::fault_addr
[Num_Faults
] = {
63 0x0000, /* No_Fault */
64 0x0001, /* Reset_Fault */
65 0x0401, /* Machine_Check_Fault */
66 0x0501, /* Arithmetic_Fault */
67 0x0101, /* Interrupt_Fault */
68 0x0201, /* Ndtb_Miss_Fault */
69 0x0281, /* Pdtb_Miss_Fault */
70 0x0301, /* Alignment_Fault */
71 0x0381, /* Dtb_Fault_Fault */
72 0x0381, /* Dtb_Acv_Fault */
73 0x0181, /* Itb_Miss_Fault */
74 0x0181, /* Itb_Fault_Fault */
75 0x0081, /* Itb_Acv_Fault */
76 0x0481, /* Unimplemented_Opcode_Fault */
77 0x0581, /* Fen_Fault */
78 0x2001, /* Pal_Fault */
79 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
82 const int AlphaISA::reg_redir
[AlphaISA::NumIntRegs
] = {
83 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
84 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
85 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
86 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
88 ////////////////////////////////////////////////////////////////////////
93 AlphaISA::initIPRs(RegFile
*regs
)
95 uint64_t *ipr
= regs
->ipr
;
97 bzero((char *)ipr
, NumInternalProcRegs
* sizeof(InternalProcReg
));
98 ipr
[IPR_PAL_BASE
] = PAL_BASE
;
104 ExecContext::ev5_trap(Fault fault
)
106 assert(!misspeculating());
107 kernelStats
.fault(fault
);
109 if (fault
== Arithmetic_Fault
)
110 panic("Arithmetic traps are unimplemented!");
112 AlphaISA::InternalProcReg
*ipr
= regs
.ipr
;
114 // exception restart address
115 if (fault
!= Interrupt_Fault
|| !PC_PAL(regs
.pc
))
116 ipr
[AlphaISA::IPR_EXC_ADDR
] = regs
.pc
;
118 if (fault
== Pal_Fault
|| fault
== Arithmetic_Fault
/* ||
119 fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
120 // traps... skip faulting instruction
121 ipr
[AlphaISA::IPR_EXC_ADDR
] += 4;
124 if (!PC_PAL(regs
.pc
))
125 AlphaISA::swap_palshadow(®s
, true);
127 regs
.pc
= ipr
[AlphaISA::IPR_PAL_BASE
] + AlphaISA::fault_addr
[fault
];
128 regs
.npc
= regs
.pc
+ sizeof(MachInst
);
130 Annotate::Ev5Trap(this, fault
);
135 AlphaISA::intr_post(RegFile
*regs
, Fault fault
, Addr pc
)
137 InternalProcReg
*ipr
= regs
->ipr
;
138 bool use_pc
= (fault
== No_Fault
);
140 if (fault
== Arithmetic_Fault
)
141 panic("arithmetic faults NYI...");
143 // compute exception restart address
144 if (use_pc
|| fault
== Pal_Fault
|| fault
== Arithmetic_Fault
) {
145 // traps... skip faulting instruction
146 ipr
[IPR_EXC_ADDR
] = regs
->pc
+ 4;
148 // fault, post fault at excepting instruction
149 ipr
[IPR_EXC_ADDR
] = regs
->pc
;
152 // jump to expection address (PAL PC bit set here as well...)
154 regs
->npc
= ipr
[IPR_PAL_BASE
] + fault_addr
[fault
];
156 regs
->npc
= ipr
[IPR_PAL_BASE
] + pc
;
158 // that's it! (orders of magnitude less painful than x86)
161 bool AlphaISA::check_interrupts
= false;
166 uint64_t *ipr
= regs
.ipr
;
168 if (!PC_PAL(regs
.pc
))
169 return Unimplemented_Opcode_Fault
;
171 setNextPC(ipr
[AlphaISA::IPR_EXC_ADDR
]);
173 if (!misspeculating()) {
176 if ((ipr
[AlphaISA::IPR_EXC_ADDR
] & 1) == 0)
177 AlphaISA::swap_palshadow(®s
, false);
179 AlphaISA::check_interrupts
= true;
182 // FIXME: XXX check for interrupts? XXX
187 ExecContext::readIpr(int idx
, Fault
&fault
)
189 uint64_t *ipr
= regs
.ipr
;
190 uint64_t retval
= 0; // return value, default 0
193 case AlphaISA::IPR_PALtemp0
:
194 case AlphaISA::IPR_PALtemp1
:
195 case AlphaISA::IPR_PALtemp2
:
196 case AlphaISA::IPR_PALtemp3
:
197 case AlphaISA::IPR_PALtemp4
:
198 case AlphaISA::IPR_PALtemp5
:
199 case AlphaISA::IPR_PALtemp6
:
200 case AlphaISA::IPR_PALtemp7
:
201 case AlphaISA::IPR_PALtemp8
:
202 case AlphaISA::IPR_PALtemp9
:
203 case AlphaISA::IPR_PALtemp10
:
204 case AlphaISA::IPR_PALtemp11
:
205 case AlphaISA::IPR_PALtemp12
:
206 case AlphaISA::IPR_PALtemp13
:
207 case AlphaISA::IPR_PALtemp14
:
208 case AlphaISA::IPR_PALtemp15
:
209 case AlphaISA::IPR_PALtemp16
:
210 case AlphaISA::IPR_PALtemp17
:
211 case AlphaISA::IPR_PALtemp18
:
212 case AlphaISA::IPR_PALtemp19
:
213 case AlphaISA::IPR_PALtemp20
:
214 case AlphaISA::IPR_PALtemp21
:
215 case AlphaISA::IPR_PALtemp22
:
216 case AlphaISA::IPR_PALtemp23
:
217 case AlphaISA::IPR_PAL_BASE
:
219 case AlphaISA::IPR_IVPTBR
:
220 case AlphaISA::IPR_DC_MODE
:
221 case AlphaISA::IPR_MAF_MODE
:
222 case AlphaISA::IPR_ISR
:
223 case AlphaISA::IPR_EXC_ADDR
:
224 case AlphaISA::IPR_IC_PERR_STAT
:
225 case AlphaISA::IPR_DC_PERR_STAT
:
226 case AlphaISA::IPR_MCSR
:
227 case AlphaISA::IPR_ASTRR
:
228 case AlphaISA::IPR_ASTER
:
229 case AlphaISA::IPR_SIRR
:
230 case AlphaISA::IPR_ICSR
:
231 case AlphaISA::IPR_ICM
:
232 case AlphaISA::IPR_DTB_CM
:
233 case AlphaISA::IPR_IPLR
:
234 case AlphaISA::IPR_INTID
:
235 case AlphaISA::IPR_PMCTR
:
240 case AlphaISA::IPR_VA
:
241 // SFX: unlocks interrupt status registers
244 if (!misspeculating())
245 regs
.intrlock
= false;
248 case AlphaISA::IPR_VA_FORM
:
249 case AlphaISA::IPR_MM_STAT
:
250 case AlphaISA::IPR_IFAULT_VA_FORM
:
251 case AlphaISA::IPR_EXC_MASK
:
252 case AlphaISA::IPR_EXC_SUM
:
256 case AlphaISA::IPR_DTB_PTE
:
258 AlphaISA::PTE
&pte
= dtb
->index(!misspeculating());
260 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
261 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
262 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
263 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
264 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
265 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
266 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
270 // write only registers
271 case AlphaISA::IPR_HWINT_CLR
:
272 case AlphaISA::IPR_SL_XMIT
:
273 case AlphaISA::IPR_DC_FLUSH
:
274 case AlphaISA::IPR_IC_FLUSH
:
275 case AlphaISA::IPR_ALT_MODE
:
276 case AlphaISA::IPR_DTB_IA
:
277 case AlphaISA::IPR_DTB_IAP
:
278 case AlphaISA::IPR_ITB_IA
:
279 case AlphaISA::IPR_ITB_IAP
:
280 fault
= Unimplemented_Opcode_Fault
;
285 fault
= Unimplemented_Opcode_Fault
;
293 // Cause the simulator to break when changing to the following IPL
298 ExecContext::setIpr(int idx
, uint64_t val
)
300 uint64_t *ipr
= regs
.ipr
;
302 if (misspeculating())
306 case AlphaISA::IPR_PALtemp0
:
307 case AlphaISA::IPR_PALtemp1
:
308 case AlphaISA::IPR_PALtemp2
:
309 case AlphaISA::IPR_PALtemp3
:
310 case AlphaISA::IPR_PALtemp4
:
311 case AlphaISA::IPR_PALtemp5
:
312 case AlphaISA::IPR_PALtemp6
:
313 case AlphaISA::IPR_PALtemp7
:
314 case AlphaISA::IPR_PALtemp8
:
315 case AlphaISA::IPR_PALtemp9
:
316 case AlphaISA::IPR_PALtemp10
:
317 case AlphaISA::IPR_PALtemp11
:
318 case AlphaISA::IPR_PALtemp12
:
319 case AlphaISA::IPR_PALtemp13
:
320 case AlphaISA::IPR_PALtemp14
:
321 case AlphaISA::IPR_PALtemp15
:
322 case AlphaISA::IPR_PALtemp16
:
323 case AlphaISA::IPR_PALtemp17
:
324 case AlphaISA::IPR_PALtemp18
:
325 case AlphaISA::IPR_PALtemp19
:
326 case AlphaISA::IPR_PALtemp20
:
327 case AlphaISA::IPR_PALtemp21
:
328 case AlphaISA::IPR_PALtemp22
:
329 case AlphaISA::IPR_PAL_BASE
:
330 case AlphaISA::IPR_IC_PERR_STAT
:
331 case AlphaISA::IPR_DC_PERR_STAT
:
332 case AlphaISA::IPR_PMCTR
:
333 // write entire quad w/ no side-effect
337 case AlphaISA::IPR_CC_CTL
:
338 // This IPR resets the cycle counter. We assume this only
339 // happens once... let's verify that.
340 assert(ipr
[idx
] == 0);
344 case AlphaISA::IPR_CC
:
345 // This IPR only writes the upper 64 bits. It's ok to write
346 // all 64 here since we mask out the lower 32 in rpcc (see
351 case AlphaISA::IPR_PALtemp23
:
352 // write entire quad w/ no side-effect
354 kernelStats
.context(ipr
[idx
]);
355 Annotate::Context(this);
358 case AlphaISA::IPR_DTB_PTE
:
359 // write entire quad w/ no side-effect, tag is forthcoming
363 case AlphaISA::IPR_EXC_ADDR
:
364 // second least significant bit in PC is always zero
368 case AlphaISA::IPR_ASTRR
:
369 case AlphaISA::IPR_ASTER
:
370 // only write least significant four bits - privilege mask
371 ipr
[idx
] = val
& 0xf;
374 case AlphaISA::IPR_IPLR
:
376 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
380 // only write least significant five bits - interrupt level
381 ipr
[idx
] = val
& 0x1f;
382 kernelStats
.swpipl(ipr
[idx
]);
383 Annotate::IPL(this, val
& 0x1f);
386 case AlphaISA::IPR_DTB_CM
:
387 Annotate::ChangeMode(this, (val
& 0x18) != 0);
388 kernelStats
.mode((val
& 0x18) != 0);
390 case AlphaISA::IPR_ICM
:
391 // only write two mode bits - processor mode
392 ipr
[idx
] = val
& 0x18;
395 case AlphaISA::IPR_ALT_MODE
:
396 // only write two mode bits - processor mode
397 ipr
[idx
] = val
& 0x18;
400 case AlphaISA::IPR_MCSR
:
401 // more here after optimization...
405 case AlphaISA::IPR_SIRR
:
406 // only write software interrupt mask
407 ipr
[idx
] = val
& 0x7fff0;
410 case AlphaISA::IPR_ICSR
:
411 ipr
[idx
] = val
& ULL(0xffffff0300);
414 case AlphaISA::IPR_IVPTBR
:
415 case AlphaISA::IPR_MVPTBR
:
416 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
419 case AlphaISA::IPR_DC_TEST_CTL
:
420 ipr
[idx
] = val
& 0x1ffb;
423 case AlphaISA::IPR_DC_MODE
:
424 case AlphaISA::IPR_MAF_MODE
:
425 ipr
[idx
] = val
& 0x3f;
428 case AlphaISA::IPR_ITB_ASN
:
429 ipr
[idx
] = val
& 0x7f0;
432 case AlphaISA::IPR_DTB_ASN
:
433 ipr
[idx
] = val
& ULL(0xfe00000000000000);
436 case AlphaISA::IPR_EXC_SUM
:
437 case AlphaISA::IPR_EXC_MASK
:
438 // any write to this register clears it
442 case AlphaISA::IPR_INTID
:
443 case AlphaISA::IPR_SL_RCV
:
444 case AlphaISA::IPR_MM_STAT
:
445 case AlphaISA::IPR_ITB_PTE_TEMP
:
446 case AlphaISA::IPR_DTB_PTE_TEMP
:
447 // read-only registers
448 return Unimplemented_Opcode_Fault
;
450 case AlphaISA::IPR_HWINT_CLR
:
451 case AlphaISA::IPR_SL_XMIT
:
452 case AlphaISA::IPR_DC_FLUSH
:
453 case AlphaISA::IPR_IC_FLUSH
:
454 // the following are write only
458 case AlphaISA::IPR_DTB_IA
:
459 // really a control write
465 case AlphaISA::IPR_DTB_IAP
:
466 // really a control write
469 dtb
->flushProcesses();
472 case AlphaISA::IPR_DTB_IS
:
473 // really a control write
476 dtb
->flushAddr(val
, DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
479 case AlphaISA::IPR_DTB_TAG
: {
480 struct AlphaISA::PTE pte
;
482 // FIXME: granularity hints NYI...
483 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
484 panic("PTE GH field != 0");
489 // construct PTE for new entry
490 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
491 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
492 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
493 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
494 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
495 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
496 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
498 // insert new TAG/PTE value into data TLB
499 dtb
->insert(val
, pte
);
503 case AlphaISA::IPR_ITB_PTE
: {
504 struct AlphaISA::PTE pte
;
506 // FIXME: granularity hints NYI...
507 if (ITB_PTE_GH(val
) != 0)
508 panic("PTE GH field != 0");
513 // construct PTE for new entry
514 pte
.ppn
= ITB_PTE_PPN(val
);
515 pte
.xre
= ITB_PTE_XRE(val
);
517 pte
.fonr
= ITB_PTE_FONR(val
);
518 pte
.fonw
= ITB_PTE_FONW(val
);
519 pte
.asma
= ITB_PTE_ASMA(val
);
520 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
522 // insert new TAG/PTE value into data TLB
523 itb
->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
527 case AlphaISA::IPR_ITB_IA
:
528 // really a control write
534 case AlphaISA::IPR_ITB_IAP
:
535 // really a control write
538 itb
->flushProcesses();
541 case AlphaISA::IPR_ITB_IS
:
542 // really a control write
545 itb
->flushAddr(val
, ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
550 return Unimplemented_Opcode_Fault
;
558 * Check for special simulator handling of specific PAL calls.
559 * If return value is false, actual PAL call will be suppressed.
562 ExecContext::simPalCheck(int palFunc
)
564 kernelStats
.callpal(palFunc
);
569 if (--System::numSystemsRunning
== 0)
570 new SimExitEvent("all cpus halted");
575 if (system
->breakpoint())
583 #endif // FULL_SYSTEM