arch/alpha/ev5.cc

   1 /* $Id$ */
   2
   3 #include "targetarch/alpha_memory.hh"
   4 #include "sim/annotation.hh"
   5 #ifdef DEBUG
   6 #include "sim/debug.hh"
   7 #endif
   8 #include "cpu/exec_context.hh"
   9 #include "sim/sim_events.hh"
  10 #include "targetarch/isa_traits.hh"
  11 #include "base/remote_gdb.hh"
  12 #include "base/kgdb.h"  // for ALPHA_KENTRY_IF
  13 #include "targetarch/osfpal.hh"
  14
  15 #ifdef FULL_SYSTEM
  16
  17 #ifndef SYSTEM_EV5
  18 #error This code is only valid for EV5 systems
  19 #endif
  20
  21 ////////////////////////////////////////////////////////////////////////
  22 //
  23 //
  24 //
  25 void
  26 AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
  27 {
  28     if (regs->pal_shadow == use_shadow)
  29         panic("swap_palshadow: wrong PAL shadow state");
  30
  31     regs->pal_shadow = use_shadow;
  32
  33     for (int i = 0; i < NumIntRegs; i++) {
  34         if (reg_redir[i]) {
  35             IntReg temp = regs->intRegFile[i];
  36             regs->intRegFile[i] = regs->palregs[i];
  37             regs->palregs[i] = temp;
  38         }
  39     }
  40 }
  41
  42 ////////////////////////////////////////////////////////////////////////
  43 //
  44 //  Machine dependent functions
  45 //
  46 void
  47 AlphaISA::initCPU(RegFile *regs)
  48 {
  49     initIPRs(regs);
  50     // CPU comes up with PAL regs enabled
  51     swap_palshadow(regs, true);
  52
  53     regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
  54     regs->npc = regs->pc + sizeof(MachInst);
  55 }
  56
  57 ////////////////////////////////////////////////////////////////////////
  58 //
  59 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
  60 //
  61 Addr
  62 AlphaISA::fault_addr[Num_Faults] = {
  63     0x0000,     /* No_Fault */
  64     0x0001,     /* Reset_Fault */
  65     0x0401,     /* Machine_Check_Fault */
  66     0x0501,     /* Arithmetic_Fault */
  67     0x0101,     /* Interrupt_Fault */
  68     0x0201,     /* Ndtb_Miss_Fault */
  69     0x0281,     /* Pdtb_Miss_Fault */
  70     0x0301,     /* Alignment_Fault */
  71     0x0381,     /* Dtb_Fault_Fault */
  72     0x0381,     /* Dtb_Acv_Fault */
  73     0x0181,     /* Itb_Miss_Fault */
  74     0x0181,     /* Itb_Fault_Fault */
  75     0x0081,     /* Itb_Acv_Fault */
  76     0x0481,     /* Unimplemented_Opcode_Fault */
  77     0x0581,     /* Fen_Fault */
  78     0x2001,     /* Pal_Fault */
  79     0x0501,     /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
  80 };
  81
  82 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
  83     /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
  84     /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
  85     /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
  86     /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
  87
  88 ////////////////////////////////////////////////////////////////////////
  89 //
  90 //
  91 //
  92 void
  93 AlphaISA::initIPRs(RegFile *regs)
  94 {
  95     uint64_t *ipr = regs->ipr;
  96
  97     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
  98     ipr[IPR_PAL_BASE] = PAL_BASE;
  99     ipr[IPR_MCSR] = 0x6;
 100 }
 101
 102
 103 void
 104 ExecContext::ev5_trap(Fault fault)
 105 {
 106     assert(!misspeculating());
 107     kernelStats.fault(fault);
 108
 109     if (fault == Arithmetic_Fault)
 110         panic("Arithmetic traps are unimplemented!");
 111
 112     AlphaISA::InternalProcReg *ipr = regs.ipr;
 113
 114     // exception restart address
 115     if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
 116         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 117
 118     if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
 119         fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
 120         // traps...  skip faulting instruction
 121         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
 122     }
 123
 124     if (!PC_PAL(regs.pc))
 125         AlphaISA::swap_palshadow(&regs, true);
 126
 127     regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
 128     regs.npc = regs.pc + sizeof(MachInst);
 129
 130     Annotate::Ev5Trap(this, fault);
 131 }
 132
 133
 134 void
 135 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 136 {
 137     InternalProcReg *ipr = regs->ipr;
 138     bool use_pc = (fault == No_Fault);
 139
 140     if (fault == Arithmetic_Fault)
 141         panic("arithmetic faults NYI...");
 142
 143     // compute exception restart address
 144     if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
 145         // traps...  skip faulting instruction
 146         ipr[IPR_EXC_ADDR] = regs->pc + 4;
 147     } else {
 148         // fault, post fault at excepting instruction
 149         ipr[IPR_EXC_ADDR] = regs->pc;
 150     }
 151
 152     // jump to expection address (PAL PC bit set here as well...)
 153     if (!use_pc)
 154         regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
 155     else
 156         regs->npc = ipr[IPR_PAL_BASE] + pc;
 157
 158     // that's it! (orders of magnitude less painful than x86)
 159 }
 160
 161 bool AlphaISA::check_interrupts = false;
 162
 163 Fault
 164 ExecContext::hwrei()
 165 {
 166     uint64_t *ipr = regs.ipr;
 167
 168     if (!PC_PAL(regs.pc))
 169         return Unimplemented_Opcode_Fault;
 170
 171     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 172
 173     if (!misspeculating()) {
 174         kernelStats.hwrei();
 175
 176         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
 177             AlphaISA::swap_palshadow(&regs, false);
 178
 179         AlphaISA::check_interrupts = true;
 180     }
 181
 182     // FIXME: XXX check for interrupts? XXX
 183     return No_Fault;
 184 }
 185
 186 uint64_t
 187 ExecContext::readIpr(int idx, Fault &fault)
 188 {
 189     uint64_t *ipr = regs.ipr;
 190     uint64_t retval = 0;        // return value, default 0
 191
 192     switch (idx) {
 193       case AlphaISA::IPR_PALtemp0:
 194       case AlphaISA::IPR_PALtemp1:
 195       case AlphaISA::IPR_PALtemp2:
 196       case AlphaISA::IPR_PALtemp3:
 197       case AlphaISA::IPR_PALtemp4:
 198       case AlphaISA::IPR_PALtemp5:
 199       case AlphaISA::IPR_PALtemp6:
 200       case AlphaISA::IPR_PALtemp7:
 201       case AlphaISA::IPR_PALtemp8:
 202       case AlphaISA::IPR_PALtemp9:
 203       case AlphaISA::IPR_PALtemp10:
 204       case AlphaISA::IPR_PALtemp11:
 205       case AlphaISA::IPR_PALtemp12:
 206       case AlphaISA::IPR_PALtemp13:
 207       case AlphaISA::IPR_PALtemp14:
 208       case AlphaISA::IPR_PALtemp15:
 209       case AlphaISA::IPR_PALtemp16:
 210       case AlphaISA::IPR_PALtemp17:
 211       case AlphaISA::IPR_PALtemp18:
 212       case AlphaISA::IPR_PALtemp19:
 213       case AlphaISA::IPR_PALtemp20:
 214       case AlphaISA::IPR_PALtemp21:
 215       case AlphaISA::IPR_PALtemp22:
 216       case AlphaISA::IPR_PALtemp23:
 217       case AlphaISA::IPR_PAL_BASE:
 218
 219       case AlphaISA::IPR_IVPTBR:
 220       case AlphaISA::IPR_DC_MODE:
 221       case AlphaISA::IPR_MAF_MODE:
 222       case AlphaISA::IPR_ISR:
 223       case AlphaISA::IPR_EXC_ADDR:
 224       case AlphaISA::IPR_IC_PERR_STAT:
 225       case AlphaISA::IPR_DC_PERR_STAT:
 226       case AlphaISA::IPR_MCSR:
 227       case AlphaISA::IPR_ASTRR:
 228       case AlphaISA::IPR_ASTER:
 229       case AlphaISA::IPR_SIRR:
 230       case AlphaISA::IPR_ICSR:
 231       case AlphaISA::IPR_ICM:
 232       case AlphaISA::IPR_DTB_CM:
 233       case AlphaISA::IPR_IPLR:
 234       case AlphaISA::IPR_INTID:
 235       case AlphaISA::IPR_PMCTR:
 236         // no side-effect
 237         retval = ipr[idx];
 238         break;
 239
 240       case AlphaISA::IPR_VA:
 241         // SFX: unlocks interrupt status registers
 242         retval = ipr[idx];
 243
 244         if (!misspeculating())
 245             regs.intrlock = false;
 246         break;
 247
 248       case AlphaISA::IPR_VA_FORM:
 249       case AlphaISA::IPR_MM_STAT:
 250       case AlphaISA::IPR_IFAULT_VA_FORM:
 251       case AlphaISA::IPR_EXC_MASK:
 252       case AlphaISA::IPR_EXC_SUM:
 253         retval = ipr[idx];
 254         break;
 255
 256       case AlphaISA::IPR_DTB_PTE:
 257         {
 258             AlphaISA::PTE &pte = dtb->index(!misspeculating());
 259
 260             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
 261             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
 262             retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
 263             retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
 264             retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
 265             retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
 266             retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
 267         }
 268         break;
 269
 270         // write only registers
 271       case AlphaISA::IPR_HWINT_CLR:
 272       case AlphaISA::IPR_SL_XMIT:
 273       case AlphaISA::IPR_DC_FLUSH:
 274       case AlphaISA::IPR_IC_FLUSH:
 275       case AlphaISA::IPR_ALT_MODE:
 276       case AlphaISA::IPR_DTB_IA:
 277       case AlphaISA::IPR_DTB_IAP:
 278       case AlphaISA::IPR_ITB_IA:
 279       case AlphaISA::IPR_ITB_IAP:
 280         fault = Unimplemented_Opcode_Fault;
 281         break;
 282
 283       default:
 284         // invalid IPR
 285         fault = Unimplemented_Opcode_Fault;
 286         break;
 287     }
 288
 289     return retval;
 290 }
 291
 292 #ifdef DEBUG
 293 // Cause the simulator to break when changing to the following IPL
 294 int break_ipl = -1;
 295 #endif
 296
 297 Fault
 298 ExecContext::setIpr(int idx, uint64_t val)
 299 {
 300     uint64_t *ipr = regs.ipr;
 301
 302     if (misspeculating())
 303         return No_Fault;
 304
 305     switch (idx) {
 306       case AlphaISA::IPR_PALtemp0:
 307       case AlphaISA::IPR_PALtemp1:
 308       case AlphaISA::IPR_PALtemp2:
 309       case AlphaISA::IPR_PALtemp3:
 310       case AlphaISA::IPR_PALtemp4:
 311       case AlphaISA::IPR_PALtemp5:
 312       case AlphaISA::IPR_PALtemp6:
 313       case AlphaISA::IPR_PALtemp7:
 314       case AlphaISA::IPR_PALtemp8:
 315       case AlphaISA::IPR_PALtemp9:
 316       case AlphaISA::IPR_PALtemp10:
 317       case AlphaISA::IPR_PALtemp11:
 318       case AlphaISA::IPR_PALtemp12:
 319       case AlphaISA::IPR_PALtemp13:
 320       case AlphaISA::IPR_PALtemp14:
 321       case AlphaISA::IPR_PALtemp15:
 322       case AlphaISA::IPR_PALtemp16:
 323       case AlphaISA::IPR_PALtemp17:
 324       case AlphaISA::IPR_PALtemp18:
 325       case AlphaISA::IPR_PALtemp19:
 326       case AlphaISA::IPR_PALtemp20:
 327       case AlphaISA::IPR_PALtemp21:
 328       case AlphaISA::IPR_PALtemp22:
 329       case AlphaISA::IPR_PAL_BASE:
 330       case AlphaISA::IPR_IC_PERR_STAT:
 331       case AlphaISA::IPR_DC_PERR_STAT:
 332       case AlphaISA::IPR_CC_CTL:
 333       case AlphaISA::IPR_CC:
 334       case AlphaISA::IPR_PMCTR:
 335         // write entire quad w/ no side-effect
 336         ipr[idx] = val;
 337         break;
 338
 339       case AlphaISA::IPR_PALtemp23:
 340         // write entire quad w/ no side-effect
 341         ipr[idx] = val;
 342         kernelStats.context(ipr[idx]);
 343         Annotate::Context(this);
 344         break;
 345
 346       case AlphaISA::IPR_DTB_PTE:
 347         // write entire quad w/ no side-effect, tag is forthcoming
 348         ipr[idx] = val;
 349         break;
 350
 351       case AlphaISA::IPR_EXC_ADDR:
 352         // second least significant bit in PC is always zero
 353         ipr[idx] = val & ~2;
 354         break;
 355
 356       case AlphaISA::IPR_ASTRR:
 357       case AlphaISA::IPR_ASTER:
 358         // only write least significant four bits - privilege mask
 359         ipr[idx] = val & 0xf;
 360         break;
 361
 362       case AlphaISA::IPR_IPLR:
 363 #ifdef DEBUG
 364         if (break_ipl != -1 && break_ipl == (val & 0x1f))
 365             debug_break();
 366 #endif
 367
 368         // only write least significant five bits - interrupt level
 369         ipr[idx] = val & 0x1f;
 370         kernelStats.swpipl(ipr[idx]);
 371         Annotate::IPL(this, val & 0x1f);
 372         break;
 373
 374       case AlphaISA::IPR_DTB_CM:
 375         Annotate::ChangeMode(this, (val & 0x18) != 0);
 376         kernelStats.mode((val & 0x18) != 0);
 377
 378       case AlphaISA::IPR_ICM:
 379         // only write two mode bits - processor mode
 380         ipr[idx] = val & 0x18;
 381         break;
 382
 383       case AlphaISA::IPR_ALT_MODE:
 384         // only write two mode bits - processor mode
 385         ipr[idx] = val & 0x18;
 386         break;
 387
 388       case AlphaISA::IPR_MCSR:
 389         // more here after optimization...
 390         ipr[idx] = val;
 391         break;
 392
 393       case AlphaISA::IPR_SIRR:
 394         // only write software interrupt mask
 395         ipr[idx] = val & 0x7fff0;
 396         break;
 397
 398       case AlphaISA::IPR_ICSR:
 399         ipr[idx] = val & ULL(0xffffff0300);
 400         break;
 401
 402       case AlphaISA::IPR_IVPTBR:
 403       case AlphaISA::IPR_MVPTBR:
 404         ipr[idx] = val & ULL(0xffffffffc0000000);
 405         break;
 406
 407       case AlphaISA::IPR_DC_TEST_CTL:
 408         ipr[idx] = val & 0x1ffb;
 409         break;
 410
 411       case AlphaISA::IPR_DC_MODE:
 412       case AlphaISA::IPR_MAF_MODE:
 413         ipr[idx] = val & 0x3f;
 414         break;
 415
 416       case AlphaISA::IPR_ITB_ASN:
 417         ipr[idx] = val & 0x7f0;
 418         break;
 419
 420       case AlphaISA::IPR_DTB_ASN:
 421         ipr[idx] = val & ULL(0xfe00000000000000);
 422         break;
 423
 424       case AlphaISA::IPR_EXC_SUM:
 425       case AlphaISA::IPR_EXC_MASK:
 426         // any write to this register clears it
 427         ipr[idx] = 0;
 428         break;
 429
 430       case AlphaISA::IPR_INTID:
 431       case AlphaISA::IPR_SL_RCV:
 432       case AlphaISA::IPR_MM_STAT:
 433       case AlphaISA::IPR_ITB_PTE_TEMP:
 434       case AlphaISA::IPR_DTB_PTE_TEMP:
 435         // read-only registers
 436         return Unimplemented_Opcode_Fault;
 437
 438       case AlphaISA::IPR_HWINT_CLR:
 439       case AlphaISA::IPR_SL_XMIT:
 440       case AlphaISA::IPR_DC_FLUSH:
 441       case AlphaISA::IPR_IC_FLUSH:
 442         // the following are write only
 443         ipr[idx] = val;
 444         break;
 445
 446       case AlphaISA::IPR_DTB_IA:
 447         // really a control write
 448         ipr[idx] = 0;
 449
 450         dtb->flushAll();
 451         break;
 452
 453       case AlphaISA::IPR_DTB_IAP:
 454         // really a control write
 455         ipr[idx] = 0;
 456
 457         dtb->flushProcesses();
 458         break;
 459
 460       case AlphaISA::IPR_DTB_IS:
 461         // really a control write
 462         ipr[idx] = val;
 463
 464         dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
 465         break;
 466
 467       case AlphaISA::IPR_DTB_TAG: {
 468           struct AlphaISA::PTE pte;
 469
 470           // FIXME: granularity hints NYI...
 471           if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
 472               panic("PTE GH field != 0");
 473
 474           // write entire quad
 475           ipr[idx] = val;
 476
 477           // construct PTE for new entry
 478           pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
 479           pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
 480           pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
 481           pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
 482           pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
 483           pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
 484           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 485
 486           // insert new TAG/PTE value into data TLB
 487           dtb->insert(val, pte);
 488       }
 489         break;
 490
 491       case AlphaISA::IPR_ITB_PTE: {
 492           struct AlphaISA::PTE pte;
 493
 494           // FIXME: granularity hints NYI...
 495           if (ITB_PTE_GH(val) != 0)
 496               panic("PTE GH field != 0");
 497
 498           // write entire quad
 499           ipr[idx] = val;
 500
 501           // construct PTE for new entry
 502           pte.ppn = ITB_PTE_PPN(val);
 503           pte.xre = ITB_PTE_XRE(val);
 504           pte.xwe = 0;
 505           pte.fonr = ITB_PTE_FONR(val);
 506           pte.fonw = ITB_PTE_FONW(val);
 507           pte.asma = ITB_PTE_ASMA(val);
 508           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 509
 510           // insert new TAG/PTE value into data TLB
 511           itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
 512       }
 513         break;
 514
 515       case AlphaISA::IPR_ITB_IA:
 516         // really a control write
 517         ipr[idx] = 0;
 518
 519         itb->flushAll();
 520         break;
 521
 522       case AlphaISA::IPR_ITB_IAP:
 523         // really a control write
 524         ipr[idx] = 0;
 525
 526         itb->flushProcesses();
 527         break;
 528
 529       case AlphaISA::IPR_ITB_IS:
 530         // really a control write
 531         ipr[idx] = val;
 532
 533         itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
 534         break;
 535
 536       default:
 537         // invalid IPR
 538         return Unimplemented_Opcode_Fault;
 539     }
 540
 541     // no error...
 542     return No_Fault;
 543 }
 544
 545 /**
 546  * Check for special simulator handling of specific PAL calls.
 547  * If return value is false, actual PAL call will be suppressed.
 548  */
 549 bool
 550 ExecContext::simPalCheck(int palFunc)
 551 {
 552     kernelStats.callpal(palFunc);
 553
 554     switch (palFunc) {
 555       case PAL::halt:
 556         halt();
 557         if (--System::numSystemsRunning == 0)
 558             new SimExitEvent("all cpus halted");
 559         break;
 560
 561       case PAL::bpt:
 562       case PAL::bugchk:
 563         if (system->breakpoint())
 564             return false;
 565         break;
 566     }
 567
 568     return true;
 569 }
 570
 571 #endif // FULL_SYSTEM