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29 #include "arch/alpha/alpha_memory.hh"
30 #include "arch/alpha/isa_traits.hh"
31 #include "arch/alpha/osfpal.hh"
32 #include "base/kgdb.h"
33 #include "base/remote_gdb.hh"
34 #include "base/stats/events.hh"
35 #include "config/full_system.hh"
36 #include "cpu/base.hh"
37 #include "cpu/exec_context.hh"
38 #include "cpu/fast/cpu.hh"
39 #include "kern/kernel_stats.hh"
40 #include "sim/debug.hh"
41 #include "sim/sim_events.hh"
47 ////////////////////////////////////////////////////////////////////////
52 AlphaISA::swap_palshadow(RegFile
*regs
, bool use_shadow
)
54 if (regs
->pal_shadow
== use_shadow
)
55 panic("swap_palshadow: wrong PAL shadow state");
57 regs
->pal_shadow
= use_shadow
;
59 for (int i
= 0; i
< NumIntRegs
; i
++) {
61 IntReg temp
= regs
->intRegFile
[i
];
62 regs
->intRegFile
[i
] = regs
->palregs
[i
];
63 regs
->palregs
[i
] = temp
;
68 ////////////////////////////////////////////////////////////////////////
70 // Machine dependent functions
73 AlphaISA::initCPU(RegFile
*regs
)
76 // CPU comes up with PAL regs enabled
77 swap_palshadow(regs
, true);
79 regs
->pc
= regs
->ipr
[IPR_PAL_BASE
] + fault_addr(ResetFault
);
80 regs
->npc
= regs
->pc
+ sizeof(MachInst
);
83 ////////////////////////////////////////////////////////////////////////
85 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
88 AlphaISA::fault_addr(Fault
* fault
)
90 //Check for the system wide faults
91 if(fault
== NoFault
) return 0x0000;
92 else if(fault
== MachineCheckFault
) return 0x0401;
93 else if(fault
== AlignmentFault
) return 0x0301;
94 //Deal with the alpha specific faults
95 return ((AlphaFault
*)fault
)->vect
;
98 const int AlphaISA::reg_redir
[AlphaISA::NumIntRegs
] = {
99 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
100 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
101 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
102 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
104 ////////////////////////////////////////////////////////////////////////
109 AlphaISA::initIPRs(RegFile
*regs
)
111 uint64_t *ipr
= regs
->ipr
;
113 bzero((char *)ipr
, NumInternalProcRegs
* sizeof(InternalProcReg
));
114 ipr
[IPR_PAL_BASE
] = PalBase
;
121 AlphaISA::processInterrupts(CPU
*cpu
)
123 //Check if there are any outstanding interrupts
124 //Handle the interrupts
127 IntReg
*ipr
= cpu
->getIprPtr();
129 cpu
->checkInterrupts
= false;
132 panic("asynchronous traps not implemented\n");
135 for (int i
= INTLEVEL_SOFTWARE_MIN
;
136 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
137 if (ipr
[IPR_SIRR
] & (ULL(1) << i
)) {
138 // See table 4-19 of the 21164 hardware reference
139 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
140 summary
|= (ULL(1) << i
);
145 uint64_t interrupts
= cpu
->intr_status();
148 for (int i
= INTLEVEL_EXTERNAL_MIN
;
149 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
150 if (interrupts
& (ULL(1) << i
)) {
151 // See table 4-19 of the 21164 hardware reference
153 summary
|= (ULL(1) << i
);
158 if (ipl
&& ipl
> ipr
[IPR_IPLR
]) {
159 ipr
[IPR_ISR
] = summary
;
160 ipr
[IPR_INTID
] = ipl
;
161 cpu
->trap(InterruptFault
);
162 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
163 ipr
[IPR_IPLR
], ipl
, summary
);
170 AlphaISA::zeroRegisters(CPU
*cpu
)
172 // Insure ISA semantics
173 // (no longer very clean due to the change in setIntReg() in the
174 // cpu model. Consider changing later.)
175 cpu
->xc
->setIntReg(ZeroReg
, 0);
176 cpu
->xc
->setFloatRegDouble(ZeroReg
, 0.0);
180 ExecContext::ev5_trap(Fault
* fault
)
182 DPRINTF(Fault
, "Fault %s at PC: %#x\n", fault
->name
, regs
.pc
);
183 cpu
->recordEvent(csprintf("Fault %s", fault
->name
));
185 assert(!misspeculating());
186 kernelStats
->fault(fault
);
188 if (fault
== ArithmeticFault
)
189 panic("Arithmetic traps are unimplemented!");
191 AlphaISA::InternalProcReg
*ipr
= regs
.ipr
;
193 // exception restart address
194 if (fault
!= InterruptFault
|| !inPalMode())
195 ipr
[AlphaISA::IPR_EXC_ADDR
] = regs
.pc
;
197 if (fault
== PalFault
|| fault
== ArithmeticFault
/* ||
198 fault == InterruptFault && !inPalMode() */) {
199 // traps... skip faulting instruction
200 ipr
[AlphaISA::IPR_EXC_ADDR
] += 4;
204 AlphaISA::swap_palshadow(®s
, true);
206 regs
.pc
= ipr
[AlphaISA::IPR_PAL_BASE
] + AlphaISA::fault_addr(fault
);
207 regs
.npc
= regs
.pc
+ sizeof(MachInst
);
212 AlphaISA::intr_post(RegFile
*regs
, Fault
* fault
, Addr pc
)
214 InternalProcReg
*ipr
= regs
->ipr
;
215 bool use_pc
= (fault
== NoFault
);
217 if (fault
== ArithmeticFault
)
218 panic("arithmetic faults NYI...");
220 // compute exception restart address
221 if (use_pc
|| fault
== PalFault
|| fault
== ArithmeticFault
) {
222 // traps... skip faulting instruction
223 ipr
[IPR_EXC_ADDR
] = regs
->pc
+ 4;
225 // fault, post fault at excepting instruction
226 ipr
[IPR_EXC_ADDR
] = regs
->pc
;
229 // jump to expection address (PAL PC bit set here as well...)
231 regs
->npc
= ipr
[IPR_PAL_BASE
] + fault_addr(fault
);
233 regs
->npc
= ipr
[IPR_PAL_BASE
] + pc
;
235 // that's it! (orders of magnitude less painful than x86)
241 uint64_t *ipr
= regs
.ipr
;
244 return UnimplementedOpcodeFault
;
246 setNextPC(ipr
[AlphaISA::IPR_EXC_ADDR
]);
248 if (!misspeculating()) {
249 kernelStats
->hwrei();
251 if ((ipr
[AlphaISA::IPR_EXC_ADDR
] & 1) == 0)
252 AlphaISA::swap_palshadow(®s
, false);
254 cpu
->checkInterrupts
= true;
257 // FIXME: XXX check for interrupts? XXX
262 ExecContext::readIpr(int idx
, Fault
* &fault
)
264 uint64_t *ipr
= regs
.ipr
;
265 uint64_t retval
= 0; // return value, default 0
268 case AlphaISA::IPR_PALtemp0
:
269 case AlphaISA::IPR_PALtemp1
:
270 case AlphaISA::IPR_PALtemp2
:
271 case AlphaISA::IPR_PALtemp3
:
272 case AlphaISA::IPR_PALtemp4
:
273 case AlphaISA::IPR_PALtemp5
:
274 case AlphaISA::IPR_PALtemp6
:
275 case AlphaISA::IPR_PALtemp7
:
276 case AlphaISA::IPR_PALtemp8
:
277 case AlphaISA::IPR_PALtemp9
:
278 case AlphaISA::IPR_PALtemp10
:
279 case AlphaISA::IPR_PALtemp11
:
280 case AlphaISA::IPR_PALtemp12
:
281 case AlphaISA::IPR_PALtemp13
:
282 case AlphaISA::IPR_PALtemp14
:
283 case AlphaISA::IPR_PALtemp15
:
284 case AlphaISA::IPR_PALtemp16
:
285 case AlphaISA::IPR_PALtemp17
:
286 case AlphaISA::IPR_PALtemp18
:
287 case AlphaISA::IPR_PALtemp19
:
288 case AlphaISA::IPR_PALtemp20
:
289 case AlphaISA::IPR_PALtemp21
:
290 case AlphaISA::IPR_PALtemp22
:
291 case AlphaISA::IPR_PALtemp23
:
292 case AlphaISA::IPR_PAL_BASE
:
294 case AlphaISA::IPR_IVPTBR
:
295 case AlphaISA::IPR_DC_MODE
:
296 case AlphaISA::IPR_MAF_MODE
:
297 case AlphaISA::IPR_ISR
:
298 case AlphaISA::IPR_EXC_ADDR
:
299 case AlphaISA::IPR_IC_PERR_STAT
:
300 case AlphaISA::IPR_DC_PERR_STAT
:
301 case AlphaISA::IPR_MCSR
:
302 case AlphaISA::IPR_ASTRR
:
303 case AlphaISA::IPR_ASTER
:
304 case AlphaISA::IPR_SIRR
:
305 case AlphaISA::IPR_ICSR
:
306 case AlphaISA::IPR_ICM
:
307 case AlphaISA::IPR_DTB_CM
:
308 case AlphaISA::IPR_IPLR
:
309 case AlphaISA::IPR_INTID
:
310 case AlphaISA::IPR_PMCTR
:
315 case AlphaISA::IPR_CC
:
316 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
317 retval
|= cpu
->curCycle() & ULL(0x00000000ffffffff);
320 case AlphaISA::IPR_VA
:
324 case AlphaISA::IPR_VA_FORM
:
325 case AlphaISA::IPR_MM_STAT
:
326 case AlphaISA::IPR_IFAULT_VA_FORM
:
327 case AlphaISA::IPR_EXC_MASK
:
328 case AlphaISA::IPR_EXC_SUM
:
332 case AlphaISA::IPR_DTB_PTE
:
334 AlphaISA::PTE
&pte
= dtb
->index(!misspeculating());
336 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
337 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
338 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
339 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
340 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
341 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
342 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
346 // write only registers
347 case AlphaISA::IPR_HWINT_CLR
:
348 case AlphaISA::IPR_SL_XMIT
:
349 case AlphaISA::IPR_DC_FLUSH
:
350 case AlphaISA::IPR_IC_FLUSH
:
351 case AlphaISA::IPR_ALT_MODE
:
352 case AlphaISA::IPR_DTB_IA
:
353 case AlphaISA::IPR_DTB_IAP
:
354 case AlphaISA::IPR_ITB_IA
:
355 case AlphaISA::IPR_ITB_IAP
:
356 fault
= UnimplementedOpcodeFault
;
361 fault
= UnimplementedOpcodeFault
;
369 // Cause the simulator to break when changing to the following IPL
374 ExecContext::setIpr(int idx
, uint64_t val
)
376 uint64_t *ipr
= regs
.ipr
;
379 if (misspeculating())
383 case AlphaISA::IPR_PALtemp0
:
384 case AlphaISA::IPR_PALtemp1
:
385 case AlphaISA::IPR_PALtemp2
:
386 case AlphaISA::IPR_PALtemp3
:
387 case AlphaISA::IPR_PALtemp4
:
388 case AlphaISA::IPR_PALtemp5
:
389 case AlphaISA::IPR_PALtemp6
:
390 case AlphaISA::IPR_PALtemp7
:
391 case AlphaISA::IPR_PALtemp8
:
392 case AlphaISA::IPR_PALtemp9
:
393 case AlphaISA::IPR_PALtemp10
:
394 case AlphaISA::IPR_PALtemp11
:
395 case AlphaISA::IPR_PALtemp12
:
396 case AlphaISA::IPR_PALtemp13
:
397 case AlphaISA::IPR_PALtemp14
:
398 case AlphaISA::IPR_PALtemp15
:
399 case AlphaISA::IPR_PALtemp16
:
400 case AlphaISA::IPR_PALtemp17
:
401 case AlphaISA::IPR_PALtemp18
:
402 case AlphaISA::IPR_PALtemp19
:
403 case AlphaISA::IPR_PALtemp20
:
404 case AlphaISA::IPR_PALtemp21
:
405 case AlphaISA::IPR_PALtemp22
:
406 case AlphaISA::IPR_PAL_BASE
:
407 case AlphaISA::IPR_IC_PERR_STAT
:
408 case AlphaISA::IPR_DC_PERR_STAT
:
409 case AlphaISA::IPR_PMCTR
:
410 // write entire quad w/ no side-effect
414 case AlphaISA::IPR_CC_CTL
:
415 // This IPR resets the cycle counter. We assume this only
416 // happens once... let's verify that.
417 assert(ipr
[idx
] == 0);
421 case AlphaISA::IPR_CC
:
422 // This IPR only writes the upper 64 bits. It's ok to write
423 // all 64 here since we mask out the lower 32 in rpcc (see
428 case AlphaISA::IPR_PALtemp23
:
429 // write entire quad w/ no side-effect
432 kernelStats
->context(old
, val
);
435 case AlphaISA::IPR_DTB_PTE
:
436 // write entire quad w/ no side-effect, tag is forthcoming
440 case AlphaISA::IPR_EXC_ADDR
:
441 // second least significant bit in PC is always zero
445 case AlphaISA::IPR_ASTRR
:
446 case AlphaISA::IPR_ASTER
:
447 // only write least significant four bits - privilege mask
448 ipr
[idx
] = val
& 0xf;
451 case AlphaISA::IPR_IPLR
:
453 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
457 // only write least significant five bits - interrupt level
458 ipr
[idx
] = val
& 0x1f;
459 kernelStats
->swpipl(ipr
[idx
]);
462 case AlphaISA::IPR_DTB_CM
:
464 kernelStats
->mode(Kernel::user
);
466 kernelStats
->mode(Kernel::kernel
);
468 case AlphaISA::IPR_ICM
:
469 // only write two mode bits - processor mode
470 ipr
[idx
] = val
& 0x18;
473 case AlphaISA::IPR_ALT_MODE
:
474 // only write two mode bits - processor mode
475 ipr
[idx
] = val
& 0x18;
478 case AlphaISA::IPR_MCSR
:
479 // more here after optimization...
483 case AlphaISA::IPR_SIRR
:
484 // only write software interrupt mask
485 ipr
[idx
] = val
& 0x7fff0;
488 case AlphaISA::IPR_ICSR
:
489 ipr
[idx
] = val
& ULL(0xffffff0300);
492 case AlphaISA::IPR_IVPTBR
:
493 case AlphaISA::IPR_MVPTBR
:
494 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
497 case AlphaISA::IPR_DC_TEST_CTL
:
498 ipr
[idx
] = val
& 0x1ffb;
501 case AlphaISA::IPR_DC_MODE
:
502 case AlphaISA::IPR_MAF_MODE
:
503 ipr
[idx
] = val
& 0x3f;
506 case AlphaISA::IPR_ITB_ASN
:
507 ipr
[idx
] = val
& 0x7f0;
510 case AlphaISA::IPR_DTB_ASN
:
511 ipr
[idx
] = val
& ULL(0xfe00000000000000);
514 case AlphaISA::IPR_EXC_SUM
:
515 case AlphaISA::IPR_EXC_MASK
:
516 // any write to this register clears it
520 case AlphaISA::IPR_INTID
:
521 case AlphaISA::IPR_SL_RCV
:
522 case AlphaISA::IPR_MM_STAT
:
523 case AlphaISA::IPR_ITB_PTE_TEMP
:
524 case AlphaISA::IPR_DTB_PTE_TEMP
:
525 // read-only registers
526 return UnimplementedOpcodeFault
;
528 case AlphaISA::IPR_HWINT_CLR
:
529 case AlphaISA::IPR_SL_XMIT
:
530 case AlphaISA::IPR_DC_FLUSH
:
531 case AlphaISA::IPR_IC_FLUSH
:
532 // the following are write only
536 case AlphaISA::IPR_DTB_IA
:
537 // really a control write
543 case AlphaISA::IPR_DTB_IAP
:
544 // really a control write
547 dtb
->flushProcesses();
550 case AlphaISA::IPR_DTB_IS
:
551 // really a control write
554 dtb
->flushAddr(val
, DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
557 case AlphaISA::IPR_DTB_TAG
: {
558 struct AlphaISA::PTE pte
;
560 // FIXME: granularity hints NYI...
561 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
562 panic("PTE GH field != 0");
567 // construct PTE for new entry
568 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
569 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
570 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
571 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
572 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
573 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
574 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
576 // insert new TAG/PTE value into data TLB
577 dtb
->insert(val
, pte
);
581 case AlphaISA::IPR_ITB_PTE
: {
582 struct AlphaISA::PTE pte
;
584 // FIXME: granularity hints NYI...
585 if (ITB_PTE_GH(val
) != 0)
586 panic("PTE GH field != 0");
591 // construct PTE for new entry
592 pte
.ppn
= ITB_PTE_PPN(val
);
593 pte
.xre
= ITB_PTE_XRE(val
);
595 pte
.fonr
= ITB_PTE_FONR(val
);
596 pte
.fonw
= ITB_PTE_FONW(val
);
597 pte
.asma
= ITB_PTE_ASMA(val
);
598 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
600 // insert new TAG/PTE value into data TLB
601 itb
->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
605 case AlphaISA::IPR_ITB_IA
:
606 // really a control write
612 case AlphaISA::IPR_ITB_IAP
:
613 // really a control write
616 itb
->flushProcesses();
619 case AlphaISA::IPR_ITB_IS
:
620 // really a control write
623 itb
->flushAddr(val
, ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
628 return UnimplementedOpcodeFault
;
636 * Check for special simulator handling of specific PAL calls.
637 * If return value is false, actual PAL call will be suppressed.
640 ExecContext::simPalCheck(int palFunc
)
642 kernelStats
->callpal(palFunc
);
647 if (--System::numSystemsRunning
== 0)
648 new SimExitEvent("all cpus halted");
653 if (system
->breakpoint())
661 //Forward instantiation for FastCPU object
663 void AlphaISA::processInterrupts(FastCPU
*xc
);
665 //Forward instantiation for FastCPU object
667 void AlphaISA::zeroRegisters(FastCPU
*xc
);
669 #endif // FULL_SYSTEM