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29 #include "arch/alpha/tlb.hh"
30 #include "arch/alpha/isa_traits.hh"
31 #include "arch/alpha/osfpal.hh"
32 #include "base/kgdb.h"
33 #include "base/remote_gdb.hh"
34 #include "base/stats/events.hh"
35 #include "config/full_system.hh"
36 #include "cpu/base.hh"
37 #include "cpu/exec_context.hh"
38 #include "cpu/fast/cpu.hh"
39 #include "kern/kernel_stats.hh"
40 #include "sim/debug.hh"
41 #include "sim/sim_events.hh"
47 ////////////////////////////////////////////////////////////////////////
52 AlphaISA::swap_palshadow(RegFile
*regs
, bool use_shadow
)
54 if (regs
->pal_shadow
== use_shadow
)
55 panic("swap_palshadow: wrong PAL shadow state");
57 regs
->pal_shadow
= use_shadow
;
59 for (int i
= 0; i
< NumIntRegs
; i
++) {
61 IntReg temp
= regs
->intRegFile
[i
];
62 regs
->intRegFile
[i
] = regs
->palregs
[i
];
63 regs
->palregs
[i
] = temp
;
68 ////////////////////////////////////////////////////////////////////////
70 // Machine dependent functions
73 AlphaISA::initCPU(RegFile
*regs
, int cpuId
)
75 initIPRs(regs
, cpuId
);
76 // CPU comes up with PAL regs enabled
77 swap_palshadow(regs
, true);
79 regs
->intRegFile
[16] = cpuId
;
80 regs
->intRegFile
[0] = cpuId
;
82 regs
->pc
= regs
->ipr
[IPR_PAL_BASE
] + (new ResetFault
)->vect();
83 regs
->npc
= regs
->pc
+ sizeof(MachInst
);
86 const int AlphaISA::reg_redir
[AlphaISA::NumIntRegs
] = {
87 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
88 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
89 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
90 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
92 ////////////////////////////////////////////////////////////////////////
97 AlphaISA::initIPRs(RegFile
*regs
, int cpuId
)
99 uint64_t *ipr
= regs
->ipr
;
101 bzero((char *)ipr
, NumInternalProcRegs
* sizeof(InternalProcReg
));
102 ipr
[IPR_PAL_BASE
] = PalBase
;
104 ipr
[IPR_PALtemp16
] = cpuId
;
110 AlphaISA::processInterrupts(CPU
*cpu
)
112 //Check if there are any outstanding interrupts
113 //Handle the interrupts
116 IntReg
*ipr
= cpu
->getIprPtr();
118 cpu
->checkInterrupts
= false;
121 panic("asynchronous traps not implemented\n");
124 for (int i
= INTLEVEL_SOFTWARE_MIN
;
125 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
126 if (ipr
[IPR_SIRR
] & (ULL(1) << i
)) {
127 // See table 4-19 of the 21164 hardware reference
128 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
129 summary
|= (ULL(1) << i
);
134 uint64_t interrupts
= cpu
->intr_status();
137 for (int i
= INTLEVEL_EXTERNAL_MIN
;
138 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
139 if (interrupts
& (ULL(1) << i
)) {
140 // See table 4-19 of the 21164 hardware reference
142 summary
|= (ULL(1) << i
);
147 if (ipl
&& ipl
> ipr
[IPR_IPLR
]) {
148 ipr
[IPR_ISR
] = summary
;
149 ipr
[IPR_INTID
] = ipl
;
150 cpu
->trap(new InterruptFault
);
151 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
152 ipr
[IPR_IPLR
], ipl
, summary
);
159 AlphaISA::zeroRegisters(CPU
*cpu
)
161 // Insure ISA semantics
162 // (no longer very clean due to the change in setIntReg() in the
163 // cpu model. Consider changing later.)
164 cpu
->xc
->setIntReg(ZeroReg
, 0);
165 cpu
->xc
->setFloatRegDouble(ZeroReg
, 0.0);
169 ExecContext::ev5_temp_trap(Fault fault
)
171 DPRINTF(Fault
, "Fault %s at PC: %#x\n", fault
->name(), regs
.pc
);
172 cpu
->recordEvent(csprintf("Fault %s", fault
->name()));
174 assert(!misspeculating());
175 kernelStats
->fault(fault
);
177 if (fault
->isA
<ArithmeticFault
>())
178 panic("Arithmetic traps are unimplemented!");
180 AlphaISA::InternalProcReg
*ipr
= regs
.ipr
;
182 // exception restart address
183 if (!fault
->isA
<InterruptFault
>() || !inPalMode())
184 ipr
[AlphaISA::IPR_EXC_ADDR
] = regs
.pc
;
186 if (fault
->isA
<PalFault
>() || fault
->isA
<ArithmeticFault
>() /* ||
187 fault == InterruptFault && !inPalMode() */) {
188 // traps... skip faulting instruction.
189 ipr
[AlphaISA::IPR_EXC_ADDR
] += 4;
193 AlphaISA::swap_palshadow(®s
, true);
195 regs
.pc
= ipr
[AlphaISA::IPR_PAL_BASE
] +
196 (dynamic_cast<AlphaFault
*>(fault
.get()))->vect();
197 regs
.npc
= regs
.pc
+ sizeof(MachInst
);
202 AlphaISA::intr_post(RegFile
*regs
, Fault fault
, Addr pc
)
204 InternalProcReg
*ipr
= regs
->ipr
;
205 bool use_pc
= (fault
== NoFault
);
207 if (fault
->isA
<ArithmeticFault
>())
208 panic("arithmetic faults NYI...");
210 // compute exception restart address
211 if (use_pc
|| fault
->isA
<PalFault
>() || fault
->isA
<ArithmeticFault
>()) {
212 // traps... skip faulting instruction
213 ipr
[IPR_EXC_ADDR
] = regs
->pc
+ 4;
215 // fault, post fault at excepting instruction
216 ipr
[IPR_EXC_ADDR
] = regs
->pc
;
219 // jump to expection address (PAL PC bit set here as well...)
221 regs
->npc
= ipr
[IPR_PAL_BASE
] +
222 (dynamic_cast<AlphaFault
*>(fault
.get()))->vect();
224 regs
->npc
= ipr
[IPR_PAL_BASE
] + pc
;
226 // that's it! (orders of magnitude less painful than x86)
232 uint64_t *ipr
= regs
.ipr
;
235 return new UnimplementedOpcodeFault
;
237 setNextPC(ipr
[AlphaISA::IPR_EXC_ADDR
]);
239 if (!misspeculating()) {
240 kernelStats
->hwrei();
242 if ((ipr
[AlphaISA::IPR_EXC_ADDR
] & 1) == 0)
243 AlphaISA::swap_palshadow(®s
, false);
245 cpu
->checkInterrupts
= true;
248 // FIXME: XXX check for interrupts? XXX
253 ExecContext::readIpr(int idx
, Fault
&fault
)
255 uint64_t *ipr
= regs
.ipr
;
256 uint64_t retval
= 0; // return value, default 0
259 case AlphaISA::IPR_PALtemp0
:
260 case AlphaISA::IPR_PALtemp1
:
261 case AlphaISA::IPR_PALtemp2
:
262 case AlphaISA::IPR_PALtemp3
:
263 case AlphaISA::IPR_PALtemp4
:
264 case AlphaISA::IPR_PALtemp5
:
265 case AlphaISA::IPR_PALtemp6
:
266 case AlphaISA::IPR_PALtemp7
:
267 case AlphaISA::IPR_PALtemp8
:
268 case AlphaISA::IPR_PALtemp9
:
269 case AlphaISA::IPR_PALtemp10
:
270 case AlphaISA::IPR_PALtemp11
:
271 case AlphaISA::IPR_PALtemp12
:
272 case AlphaISA::IPR_PALtemp13
:
273 case AlphaISA::IPR_PALtemp14
:
274 case AlphaISA::IPR_PALtemp15
:
275 case AlphaISA::IPR_PALtemp16
:
276 case AlphaISA::IPR_PALtemp17
:
277 case AlphaISA::IPR_PALtemp18
:
278 case AlphaISA::IPR_PALtemp19
:
279 case AlphaISA::IPR_PALtemp20
:
280 case AlphaISA::IPR_PALtemp21
:
281 case AlphaISA::IPR_PALtemp22
:
282 case AlphaISA::IPR_PALtemp23
:
283 case AlphaISA::IPR_PAL_BASE
:
285 case AlphaISA::IPR_IVPTBR
:
286 case AlphaISA::IPR_DC_MODE
:
287 case AlphaISA::IPR_MAF_MODE
:
288 case AlphaISA::IPR_ISR
:
289 case AlphaISA::IPR_EXC_ADDR
:
290 case AlphaISA::IPR_IC_PERR_STAT
:
291 case AlphaISA::IPR_DC_PERR_STAT
:
292 case AlphaISA::IPR_MCSR
:
293 case AlphaISA::IPR_ASTRR
:
294 case AlphaISA::IPR_ASTER
:
295 case AlphaISA::IPR_SIRR
:
296 case AlphaISA::IPR_ICSR
:
297 case AlphaISA::IPR_ICM
:
298 case AlphaISA::IPR_DTB_CM
:
299 case AlphaISA::IPR_IPLR
:
300 case AlphaISA::IPR_INTID
:
301 case AlphaISA::IPR_PMCTR
:
306 case AlphaISA::IPR_CC
:
307 retval
|= ipr
[idx
] & ULL(0xffffffff00000000);
308 retval
|= cpu
->curCycle() & ULL(0x00000000ffffffff);
311 case AlphaISA::IPR_VA
:
315 case AlphaISA::IPR_VA_FORM
:
316 case AlphaISA::IPR_MM_STAT
:
317 case AlphaISA::IPR_IFAULT_VA_FORM
:
318 case AlphaISA::IPR_EXC_MASK
:
319 case AlphaISA::IPR_EXC_SUM
:
323 case AlphaISA::IPR_DTB_PTE
:
325 AlphaISA::PTE
&pte
= dtb
->index(!misspeculating());
327 retval
|= ((u_int64_t
)pte
.ppn
& ULL(0x7ffffff)) << 32;
328 retval
|= ((u_int64_t
)pte
.xre
& ULL(0xf)) << 8;
329 retval
|= ((u_int64_t
)pte
.xwe
& ULL(0xf)) << 12;
330 retval
|= ((u_int64_t
)pte
.fonr
& ULL(0x1)) << 1;
331 retval
|= ((u_int64_t
)pte
.fonw
& ULL(0x1))<< 2;
332 retval
|= ((u_int64_t
)pte
.asma
& ULL(0x1)) << 4;
333 retval
|= ((u_int64_t
)pte
.asn
& ULL(0x7f)) << 57;
337 // write only registers
338 case AlphaISA::IPR_HWINT_CLR
:
339 case AlphaISA::IPR_SL_XMIT
:
340 case AlphaISA::IPR_DC_FLUSH
:
341 case AlphaISA::IPR_IC_FLUSH
:
342 case AlphaISA::IPR_ALT_MODE
:
343 case AlphaISA::IPR_DTB_IA
:
344 case AlphaISA::IPR_DTB_IAP
:
345 case AlphaISA::IPR_ITB_IA
:
346 case AlphaISA::IPR_ITB_IAP
:
347 fault
= new UnimplementedOpcodeFault
;
352 fault
= new UnimplementedOpcodeFault
;
360 // Cause the simulator to break when changing to the following IPL
365 ExecContext::setIpr(int idx
, uint64_t val
)
367 uint64_t *ipr
= regs
.ipr
;
370 if (misspeculating())
374 case AlphaISA::IPR_PALtemp0
:
375 case AlphaISA::IPR_PALtemp1
:
376 case AlphaISA::IPR_PALtemp2
:
377 case AlphaISA::IPR_PALtemp3
:
378 case AlphaISA::IPR_PALtemp4
:
379 case AlphaISA::IPR_PALtemp5
:
380 case AlphaISA::IPR_PALtemp6
:
381 case AlphaISA::IPR_PALtemp7
:
382 case AlphaISA::IPR_PALtemp8
:
383 case AlphaISA::IPR_PALtemp9
:
384 case AlphaISA::IPR_PALtemp10
:
385 case AlphaISA::IPR_PALtemp11
:
386 case AlphaISA::IPR_PALtemp12
:
387 case AlphaISA::IPR_PALtemp13
:
388 case AlphaISA::IPR_PALtemp14
:
389 case AlphaISA::IPR_PALtemp15
:
390 case AlphaISA::IPR_PALtemp16
:
391 case AlphaISA::IPR_PALtemp17
:
392 case AlphaISA::IPR_PALtemp18
:
393 case AlphaISA::IPR_PALtemp19
:
394 case AlphaISA::IPR_PALtemp20
:
395 case AlphaISA::IPR_PALtemp21
:
396 case AlphaISA::IPR_PALtemp22
:
397 case AlphaISA::IPR_PAL_BASE
:
398 case AlphaISA::IPR_IC_PERR_STAT
:
399 case AlphaISA::IPR_DC_PERR_STAT
:
400 case AlphaISA::IPR_PMCTR
:
401 // write entire quad w/ no side-effect
405 case AlphaISA::IPR_CC_CTL
:
406 // This IPR resets the cycle counter. We assume this only
407 // happens once... let's verify that.
408 assert(ipr
[idx
] == 0);
412 case AlphaISA::IPR_CC
:
413 // This IPR only writes the upper 64 bits. It's ok to write
414 // all 64 here since we mask out the lower 32 in rpcc (see
419 case AlphaISA::IPR_PALtemp23
:
420 // write entire quad w/ no side-effect
423 kernelStats
->context(old
, val
);
426 case AlphaISA::IPR_DTB_PTE
:
427 // write entire quad w/ no side-effect, tag is forthcoming
431 case AlphaISA::IPR_EXC_ADDR
:
432 // second least significant bit in PC is always zero
436 case AlphaISA::IPR_ASTRR
:
437 case AlphaISA::IPR_ASTER
:
438 // only write least significant four bits - privilege mask
439 ipr
[idx
] = val
& 0xf;
442 case AlphaISA::IPR_IPLR
:
444 if (break_ipl
!= -1 && break_ipl
== (val
& 0x1f))
448 // only write least significant five bits - interrupt level
449 ipr
[idx
] = val
& 0x1f;
450 kernelStats
->swpipl(ipr
[idx
]);
453 case AlphaISA::IPR_DTB_CM
:
455 kernelStats
->mode(Kernel::user
);
457 kernelStats
->mode(Kernel::kernel
);
459 case AlphaISA::IPR_ICM
:
460 // only write two mode bits - processor mode
461 ipr
[idx
] = val
& 0x18;
464 case AlphaISA::IPR_ALT_MODE
:
465 // only write two mode bits - processor mode
466 ipr
[idx
] = val
& 0x18;
469 case AlphaISA::IPR_MCSR
:
470 // more here after optimization...
474 case AlphaISA::IPR_SIRR
:
475 // only write software interrupt mask
476 ipr
[idx
] = val
& 0x7fff0;
479 case AlphaISA::IPR_ICSR
:
480 ipr
[idx
] = val
& ULL(0xffffff0300);
483 case AlphaISA::IPR_IVPTBR
:
484 case AlphaISA::IPR_MVPTBR
:
485 ipr
[idx
] = val
& ULL(0xffffffffc0000000);
488 case AlphaISA::IPR_DC_TEST_CTL
:
489 ipr
[idx
] = val
& 0x1ffb;
492 case AlphaISA::IPR_DC_MODE
:
493 case AlphaISA::IPR_MAF_MODE
:
494 ipr
[idx
] = val
& 0x3f;
497 case AlphaISA::IPR_ITB_ASN
:
498 ipr
[idx
] = val
& 0x7f0;
501 case AlphaISA::IPR_DTB_ASN
:
502 ipr
[idx
] = val
& ULL(0xfe00000000000000);
505 case AlphaISA::IPR_EXC_SUM
:
506 case AlphaISA::IPR_EXC_MASK
:
507 // any write to this register clears it
511 case AlphaISA::IPR_INTID
:
512 case AlphaISA::IPR_SL_RCV
:
513 case AlphaISA::IPR_MM_STAT
:
514 case AlphaISA::IPR_ITB_PTE_TEMP
:
515 case AlphaISA::IPR_DTB_PTE_TEMP
:
516 // read-only registers
517 return new UnimplementedOpcodeFault
;
519 case AlphaISA::IPR_HWINT_CLR
:
520 case AlphaISA::IPR_SL_XMIT
:
521 case AlphaISA::IPR_DC_FLUSH
:
522 case AlphaISA::IPR_IC_FLUSH
:
523 // the following are write only
527 case AlphaISA::IPR_DTB_IA
:
528 // really a control write
534 case AlphaISA::IPR_DTB_IAP
:
535 // really a control write
538 dtb
->flushProcesses();
541 case AlphaISA::IPR_DTB_IS
:
542 // really a control write
545 dtb
->flushAddr(val
, DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]));
548 case AlphaISA::IPR_DTB_TAG
: {
549 struct AlphaISA::PTE pte
;
551 // FIXME: granularity hints NYI...
552 if (DTB_PTE_GH(ipr
[AlphaISA::IPR_DTB_PTE
]) != 0)
553 panic("PTE GH field != 0");
558 // construct PTE for new entry
559 pte
.ppn
= DTB_PTE_PPN(ipr
[AlphaISA::IPR_DTB_PTE
]);
560 pte
.xre
= DTB_PTE_XRE(ipr
[AlphaISA::IPR_DTB_PTE
]);
561 pte
.xwe
= DTB_PTE_XWE(ipr
[AlphaISA::IPR_DTB_PTE
]);
562 pte
.fonr
= DTB_PTE_FONR(ipr
[AlphaISA::IPR_DTB_PTE
]);
563 pte
.fonw
= DTB_PTE_FONW(ipr
[AlphaISA::IPR_DTB_PTE
]);
564 pte
.asma
= DTB_PTE_ASMA(ipr
[AlphaISA::IPR_DTB_PTE
]);
565 pte
.asn
= DTB_ASN_ASN(ipr
[AlphaISA::IPR_DTB_ASN
]);
567 // insert new TAG/PTE value into data TLB
568 dtb
->insert(val
, pte
);
572 case AlphaISA::IPR_ITB_PTE
: {
573 struct AlphaISA::PTE pte
;
575 // FIXME: granularity hints NYI...
576 if (ITB_PTE_GH(val
) != 0)
577 panic("PTE GH field != 0");
582 // construct PTE for new entry
583 pte
.ppn
= ITB_PTE_PPN(val
);
584 pte
.xre
= ITB_PTE_XRE(val
);
586 pte
.fonr
= ITB_PTE_FONR(val
);
587 pte
.fonw
= ITB_PTE_FONW(val
);
588 pte
.asma
= ITB_PTE_ASMA(val
);
589 pte
.asn
= ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]);
591 // insert new TAG/PTE value into data TLB
592 itb
->insert(ipr
[AlphaISA::IPR_ITB_TAG
], pte
);
596 case AlphaISA::IPR_ITB_IA
:
597 // really a control write
603 case AlphaISA::IPR_ITB_IAP
:
604 // really a control write
607 itb
->flushProcesses();
610 case AlphaISA::IPR_ITB_IS
:
611 // really a control write
614 itb
->flushAddr(val
, ITB_ASN_ASN(ipr
[AlphaISA::IPR_ITB_ASN
]));
619 return new UnimplementedOpcodeFault
;
627 * Check for special simulator handling of specific PAL calls.
628 * If return value is false, actual PAL call will be suppressed.
631 ExecContext::simPalCheck(int palFunc
)
633 kernelStats
->callpal(palFunc
);
638 if (--System::numSystemsRunning
== 0)
639 new SimExitEvent("all cpus halted");
644 if (system
->breakpoint())
652 //Forward instantiation for FastCPU object
654 void AlphaISA::processInterrupts(FastCPU
*xc
);
656 //Forward instantiation for FastCPU object
658 void AlphaISA::zeroRegisters(FastCPU
*xc
);
660 #endif // FULL_SYSTEM