arch/alpha/ev5.hh

   1 /* $Id$ */
   2
   3 #ifndef __ARCH_ALPHA_EV5_HH__
   4 #define __ARCH_ALPHA_EV5_HH__
   5
   6 namespace EV5 {
   7
   8 #ifdef ALPHA_TLASER
   9 const uint64_t AsnMask = ULL(0x7f);
  10 #else
  11 const uint64_t AsnMask = ULL(0xff);
  12 #endif
  13
  14 const int VAddrImplBits = 43;
  15 const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
  16 const Addr VAddrUnImplMask = ~VAddrImplMask;
  17 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
  18 inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
  19 inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
  20 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
  21 inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
  22
  23 #ifdef ALPHA_TLASER
  24 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
  25 const int PAddrImplBits = 40;
  26 #else
  27 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
  28 const int PAddrImplBits = 44; // for Tsunami
  29 #endif
  30 const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
  31 const Addr PAddrUncachedBit39 = ULL(0x8000000000);
  32 const Addr PAddrUncachedBit40 = ULL(0x10000000000);
  33 const Addr PAddrUncachedBit43 = ULL(0x80000000000);
  34 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
  35
  36 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
  37 inline Addr DTB_PTE_PPN(uint64_t reg)
  38 { return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
  39 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  40 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
  41 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  42 inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  43 inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  44 inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  45
  46 inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
  47 inline Addr ITB_PTE_PPN(uint64_t reg)
  48 { return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
  49 inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  50 inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  51 inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  52 inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  53 inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  54
  55 inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
  56
  57 inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
  58 inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
  59 inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
  60
  61 inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
  62 inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
  63 inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
  64
  65 const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
  66 const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
  67 const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
  68 const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
  69 const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
  70 const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
  71 inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
  72 inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
  73
  74 const Addr PalBase = 0x4000;
  75 const Addr PalMax = 0x10000;
  76
  77 /* namespace EV5 */ }
  78
  79 #endif // __ARCH_ALPHA_EV5_HH__