arch/alpha/ev5.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_ALPHA_EV5_HH__
  30 #define __ARCH_ALPHA_EV5_HH__
  31
  32 #include "config/alpha_tlaser.hh"
  33 #include "arch/alpha/isa_traits.hh"
  34
  35 namespace EV5 {
  36
  37 //It seems like a safe assumption EV5 only applies to alpha
  38 using namespace AlphaISA;
  39
  40 #if ALPHA_TLASER
  41 const uint64_t AsnMask = ULL(0x7f);
  42 #else
  43 const uint64_t AsnMask = ULL(0xff);
  44 #endif
  45
  46 const int VAddrImplBits = 43;
  47 const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
  48 const Addr VAddrUnImplMask = ~VAddrImplMask;
  49 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
  50 inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
  51 inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
  52 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
  53 inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
  54
  55 #if ALPHA_TLASER
  56 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
  57 const int PAddrImplBits = 40;
  58 #else
  59 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
  60 const int PAddrImplBits = 44; // for Tsunami
  61 #endif
  62 const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
  63 const Addr PAddrUncachedBit39 = ULL(0x8000000000);
  64 const Addr PAddrUncachedBit40 = ULL(0x10000000000);
  65 const Addr PAddrUncachedBit43 = ULL(0x80000000000);
  66 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
  67 inline Addr Phys2K0Seg(Addr addr)
  68 {
  69 #if !ALPHA_TLASER
  70     if (addr & PAddrUncachedBit43) {
  71         addr &= PAddrUncachedMask;
  72         addr |= PAddrUncachedBit40;
  73     }
  74 #endif
  75     return addr | AlphaISA::K0SegBase;
  76 }
  77
  78 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
  79 inline Addr DTB_PTE_PPN(uint64_t reg)
  80 { return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
  81 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  82 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
  83 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  84 inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  85 inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  86 inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  87
  88 inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
  89 inline Addr ITB_PTE_PPN(uint64_t reg)
  90 { return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
  91 inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  92 inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  93 inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  94 inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  95 inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  96
  97 inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
  98
  99 inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
 100 inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
 101 inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
 102
 103 inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
 104 inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
 105 inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
 106
 107 const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
 108 const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
 109 const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
 110 const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
 111 const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
 112 const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
 113 inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
 114 inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
 115
 116 const Addr PalBase = 0x4000;
 117 const Addr PalMax = 0x10000;
 118
 119 /* namespace EV5 */ }
 120
 121 #endif // __ARCH_ALPHA_EV5_HH__