arch/alpha/ev5.hh

   1 /* $Id$ */
   2
   3 #ifndef __EV5_H__
   4 #define __EV5_H__
   5
   6 #ifndef SYSTEM_EV5
   7 #error This code is only valid for EV5 systems
   8 #endif
   9
  10 #include "targetarch/isa_traits.hh"
  11
  12 ////////////////////////////////////////////////////////////////////////
  13 //
  14 //
  15 //
  16
  17 ////////////////////////////////////////////////////////////////////////
  18 //
  19 //
  20 //
  21
  22 #define MODE2MASK(X)                    (1 << (X))
  23
  24 // Alpha IPR register accessors
  25 #define PC_PAL(X)                       ((X) & 0x1)
  26 #define MCSR_SP(X)                      (((X) >> 1) & 0x3)
  27
  28 #define ICSR_SDE(X)                     (((X) >> 30) & 0x1)
  29 #define ICSR_SPE(X)                     (((X) >> 28) & 0x3)
  30 #define ICSR_FPE(X)                     (((X) >> 26) & 0x1)
  31
  32 #define ALT_MODE_AM(X)                  (((X) >> 3) & 0x3)
  33
  34 #define DTB_CM_CM(X)                    (((X) >> 3) & 0x3)
  35 #define DTB_ASN_ASN(X)                  (((X) >> 57) & 0x7f)
  36 #define DTB_PTE_PPN(X)                  (((X) >> 32) & 0x07ffffff)
  37 #define DTB_PTE_XRE(X)                  (((X) >> 8) & 0xf)
  38 #define DTB_PTE_XWE(X)                  (((X) >> 12) & 0xf)
  39 #define DTB_PTE_FONR(X)                 (((X) >> 1) & 0x1)
  40 #define DTB_PTE_FONW(X)                 (((X) >> 2) & 0x1)
  41 #define DTB_PTE_GH(X)                   (((X) >> 5) & 0x3)
  42 #define DTB_PTE_ASMA(X)                 (((X) >> 4) & 0x1)
  43
  44 #define ICM_CM(X)                       (((X) >> 3) & 0x3)
  45 #define ITB_ASN_ASN(X)                  (((X) >> 4) & 0x7f)
  46 #define ITB_PTE_PPN(X)                  (((X) >> 32) & 0x07ffffff)
  47 #define ITB_PTE_XRE(X)                  (((X) >> 8) & 0xf)
  48 #define ITB_PTE_FONR(X)                 (((X) >> 1) & 0x1)
  49 #define ITB_PTE_FONW(X)                 (((X) >> 2) & 0x1)
  50 #define ITB_PTE_GH(X)                   (((X) >> 5) & 0x3)
  51 #define ITB_PTE_ASMA(X)                 (((X) >> 4) & 0x1)
  52
  53 #define VA_UNIMPL_MASK                  ULL(0xfffff80000000000)
  54 #define VA_IMPL_MASK                    ULL(0x000007ffffffffff)
  55 #define VA_IMPL(X)                      ((X) & VA_IMPL_MASK)
  56 #define VA_VPN(X)                       (VA_IMPL(X) >> 13)
  57 #define VA_SPACE(X)                     (((X) >> 41) & 0x3)
  58 #define VA_POFS(X)                      ((X) & 0x1fff)
  59
  60 #define PA_IMPL_MASK                    ULL(0xfffffffffff) // for Tsunami
  61 #define PA_UNCACHED_BIT_39              ULL(0x8000000000)
  62 #define PA_UNCACHED_BIT_40              ULL(0x10000000000)
  63 #define PA_IPR_SPACE(X)                 ((X) >= ULL(0xFFFFFF00000))
  64
  65 #define PA_PFN2PA(X)                    ((X) << 13)
  66
  67
  68 #define MM_STAT_BAD_VA_MASK             0x0020
  69 #define MM_STAT_DTB_MISS_MASK           0x0010
  70 #define MM_STAT_FONW_MASK               0x0008
  71 #define MM_STAT_FONR_MASK               0x0004
  72 #define MM_STAT_ACV_MASK                0x0002
  73 #define MM_STAT_WR_MASK                 0x0001
  74
  75
  76 ////////////////////////////////////////////////////////////////////////
  77 //
  78 //
  79 //
  80
  81 // VPTE size for HW_LD/HW_ST
  82 #define HW_VPTE         ((inst >> 11) & 0x1)
  83
  84 // QWORD size for HW_LD/HW_ST
  85 #define HW_QWORD        ((inst >> 12) & 0x1)
  86
  87 // ALT mode for HW_LD/HW_ST
  88 #define HW_ALT          (((inst >> 14) & 0x1) ? ALTMODE : 0)
  89
  90 // LOCK/COND mode for HW_LD/HW_ST
  91 #define HW_LOCK         (((inst >> 10) & 0x1) ? LOCKED : 0)
  92 #define HW_COND         (((inst >> 10) & 0x1) ? LOCKED : 0)
  93
  94 // PHY size for HW_LD/HW_ST
  95 #define HW_PHY          (((inst >> 15) & 0x1) ? PHYSICAL : 0)
  96
  97 // OFFSET for HW_LD/HW_ST
  98 #define HW_OFS          (inst & 0x3ff)
  99
 100
 101 #define PAL_BASE 0x4000
 102
 103 #endif //__EV5_H__