7 #error This code is only valid for EV5 systems
10 #define MODE2MASK(X) (1 << (X))
12 // Alpha IPR register accessors
13 #define PC_PAL(X) ((X) & 0x1)
14 #define MCSR_SP(X) (((X) >> 1) & 0x3)
16 #define ICSR_SDE(X) (((X) >> 30) & 0x1)
17 #define ICSR_SPE(X) (((X) >> 28) & 0x3)
18 #define ICSR_FPE(X) (((X) >> 26) & 0x1)
20 #define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
22 #define DTB_CM_CM(X) (((X) >> 3) & 0x3)
25 #define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
26 #define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
28 #define DTB_ASN_ASN(X) (((X) >> 57) & 0xff)
29 #define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
32 #define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
33 #define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
34 #define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
35 #define DTB_PTE_FONW(X) (((X) >> 2) & 0x1)
36 #define DTB_PTE_GH(X) (((X) >> 5) & 0x3)
37 #define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
39 #define ICM_CM(X) (((X) >> 3) & 0x3)
42 #define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
43 #define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
45 #define ITB_ASN_ASN(X) (((X) >> 4) & 0xff)
46 #define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
49 #define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
50 #define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
51 #define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
52 #define ITB_PTE_GH(X) (((X) >> 5) & 0x3)
53 #define ITB_PTE_ASMA(X) (((X) >> 4) & 0x1)
55 #define VA_UNIMPL_MASK ULL(0xfffff80000000000)
56 #define VA_IMPL_MASK ULL(0x000007ffffffffff)
57 #define VA_IMPL(X) ((X) & VA_IMPL_MASK)
58 #define VA_VPN(X) (VA_IMPL(X) >> 13)
59 #define VA_SPACE_EV5(X) (((X) >> 41) & 0x3)
60 #define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f)
61 #define VA_POFS(X) ((X) & 0x1fff)
63 #define PA_UNCACHED_BIT_39 ULL(0x8000000000)
64 #define PA_UNCACHED_BIT_40 ULL(0x10000000000)
65 #define PA_UNCACHED_BIT_43 ULL(0x80000000000)
66 #define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35>
68 #define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
69 #define PA_IMPL_MASK ULL(0xffffffffff)
71 #define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
72 #define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
75 #define PA_PFN2PA(X) ((X) << 13)
78 #define MM_STAT_BAD_VA_MASK 0x0020
79 #define MM_STAT_DTB_MISS_MASK 0x0010
80 #define MM_STAT_FONW_MASK 0x0008
81 #define MM_STAT_FONR_MASK 0x0004
82 #define MM_STAT_ACV_MASK 0x0002
83 #define MM_STAT_WR_MASK 0x0001
85 #define OPCODE(X) (X >> 26) & 0x3f
86 #define RA(X) (X >> 21) & 0x1f
88 ////////////////////////////////////////////////////////////////////////
93 // VPTE size for HW_LD/HW_ST
94 #define HW_VPTE ((inst >> 11) & 0x1)
96 // QWORD size for HW_LD/HW_ST
97 #define HW_QWORD ((inst >> 12) & 0x1)
99 // ALT mode for HW_LD/HW_ST
100 #define HW_ALT (((inst >> 14) & 0x1) ? ALTMODE : 0)
102 // LOCK/COND mode for HW_LD/HW_ST
103 #define HW_LOCK (((inst >> 10) & 0x1) ? LOCKED : 0)
104 #define HW_COND (((inst >> 10) & 0x1) ? LOCKED : 0)
106 // PHY size for HW_LD/HW_ST
107 #define HW_PHY (((inst >> 15) & 0x1) ? PHYSICAL : 0)
109 // OFFSET for HW_LD/HW_ST
110 #define HW_OFS (inst & 0x3ff)
113 #define PAL_BASE 0x4000
114 #define PAL_MAX 0x10000