arch/alpha/ev5.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_ALPHA_EV5_HH__
  30 #define __ARCH_ALPHA_EV5_HH__
  31
  32 namespace EV5 {
  33
  34 #ifdef ALPHA_TLASER
  35 const uint64_t AsnMask = ULL(0x7f);
  36 #else
  37 const uint64_t AsnMask = ULL(0xff);
  38 #endif
  39
  40 const int VAddrImplBits = 43;
  41 const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
  42 const Addr VAddrUnImplMask = ~VAddrImplMask;
  43 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
  44 inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
  45 inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
  46 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
  47 inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
  48
  49 #ifdef ALPHA_TLASER
  50 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
  51 const int PAddrImplBits = 40;
  52 #else
  53 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
  54 const int PAddrImplBits = 44; // for Tsunami
  55 #endif
  56 const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
  57 const Addr PAddrUncachedBit39 = ULL(0x8000000000);
  58 const Addr PAddrUncachedBit40 = ULL(0x10000000000);
  59 const Addr PAddrUncachedBit43 = ULL(0x80000000000);
  60 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
  61
  62 inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
  63 inline Addr DTB_PTE_PPN(uint64_t reg)
  64 { return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
  65 inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  66 inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
  67 inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  68 inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  69 inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  70 inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  71
  72 inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
  73 inline Addr ITB_PTE_PPN(uint64_t reg)
  74 { return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
  75 inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
  76 inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
  77 inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
  78 inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
  79 inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
  80
  81 inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
  82
  83 inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
  84 inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
  85 inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
  86
  87 inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
  88 inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
  89 inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
  90
  91 const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
  92 const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
  93 const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
  94 const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
  95 const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
  96 const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
  97 inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
  98 inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
  99
 100 const Addr PalBase = 0x4000;
 101 const Addr PalMax = 0x10000;
 102
 103 /* namespace EV5 */ }
 104
 105 #endif // __ARCH_ALPHA_EV5_HH__