7 #error This code is only valid for EV5 systems
10 #include "targetarch/isa_traits.hh"
12 ////////////////////////////////////////////////////////////////////////
17 ////////////////////////////////////////////////////////////////////////
22 #define MODE2MASK(X) (1 << (X))
24 // Alpha IPR register accessors
25 #define PC_PAL(X) ((X) & 0x1)
26 #define MCSR_SP(X) (((X) >> 1) & 0x3)
28 #define ICSR_SDE(X) (((X) >> 30) & 0x1)
29 #define ICSR_SPE(X) (((X) >> 28) & 0x3)
30 #define ICSR_FPE(X) (((X) >> 26) & 0x1)
32 #define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
34 #define DTB_CM_CM(X) (((X) >> 3) & 0x3)
37 #define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
38 #define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
40 #define DTB_ASN_ASN(X) (((X) >> 57) & 0xff)
41 #define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
44 #define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
45 #define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
46 #define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
47 #define DTB_PTE_FONW(X) (((X) >> 2) & 0x1)
48 #define DTB_PTE_GH(X) (((X) >> 5) & 0x3)
49 #define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
51 #define ICM_CM(X) (((X) >> 3) & 0x3)
54 #define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
55 #define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
57 #define ITB_ASN_ASN(X) (((X) >> 4) & 0xff)
58 #define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
61 #define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
62 #define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
63 #define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
64 #define ITB_PTE_GH(X) (((X) >> 5) & 0x3)
65 #define ITB_PTE_ASMA(X) (((X) >> 4) & 0x1)
67 #define VA_UNIMPL_MASK ULL(0xfffff80000000000)
68 #define VA_IMPL_MASK ULL(0x000007ffffffffff)
69 #define VA_IMPL(X) ((X) & VA_IMPL_MASK)
70 #define VA_VPN(X) (VA_IMPL(X) >> 13)
71 #define VA_SPACE_EV5(X) (((X) >> 41) & 0x3)
72 #define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f)
73 #define VA_POFS(X) ((X) & 0x1fff)
75 #define PA_UNCACHED_BIT_39 ULL(0x8000000000)
76 #define PA_UNCACHED_BIT_40 ULL(0x10000000000)
77 #define PA_UNCACHED_BIT_43 ULL(0x80000000000)
78 #define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35>
80 #define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
81 #define PA_IMPL_MASK ULL(0xffffffffff)
83 #define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
84 #define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
87 #define PA_PFN2PA(X) ((X) << 13)
90 #define MM_STAT_BAD_VA_MASK 0x0020
91 #define MM_STAT_DTB_MISS_MASK 0x0010
92 #define MM_STAT_FONW_MASK 0x0008
93 #define MM_STAT_FONR_MASK 0x0004
94 #define MM_STAT_ACV_MASK 0x0002
95 #define MM_STAT_WR_MASK 0x0001
97 #define OPCODE(X) (X >> 26) & 0x3f
98 #define RA(X) (X >> 21) & 0x1f
100 ////////////////////////////////////////////////////////////////////////
105 // VPTE size for HW_LD/HW_ST
106 #define HW_VPTE ((inst >> 11) & 0x1)
108 // QWORD size for HW_LD/HW_ST
109 #define HW_QWORD ((inst >> 12) & 0x1)
111 // ALT mode for HW_LD/HW_ST
112 #define HW_ALT (((inst >> 14) & 0x1) ? ALTMODE : 0)
114 // LOCK/COND mode for HW_LD/HW_ST
115 #define HW_LOCK (((inst >> 10) & 0x1) ? LOCKED : 0)
116 #define HW_COND (((inst >> 10) & 0x1) ? LOCKED : 0)
118 // PHY size for HW_LD/HW_ST
119 #define HW_PHY (((inst >> 15) & 0x1) ? PHYSICAL : 0)
121 // OFFSET for HW_LD/HW_ST
122 #define HW_OFS (inst & 0x3ff)
125 #define PAL_BASE 0x4000