3 // Copyright (c) 2003-2006 The Regents of The University of Michigan
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
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11 // notice, this list of conditions and the following disclaimer in the
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14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 decode OPCODE default Unknown::unknown() {
32 0x08: lda({{ Ra = Rb + disp; }});
33 0x09: ldah({{ Ra = Rb + (disp << 16); }});
37 0x0a: ldbu({{ Ra.uq = Mem.ub; }});
38 0x0c: ldwu({{ Ra.uq = Mem.uw; }});
39 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
40 0x23: ldt({{ Fa = Mem.df; }});
41 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
42 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
43 0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
44 {{ fault = xc->copySrcTranslate(EA); }},
45 inst_flags = [IsMemRef, IsLoad, IsCopy]);
48 format LoadOrPrefetch {
49 0x28: ldl({{ Ra.sl = Mem.sl; }});
50 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
51 // IsFloating flag on lds gets the prefetch to disassemble
52 // using f31 instead of r31... funcitonally it's unnecessary
53 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
54 pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
58 0x0e: stb({{ Mem.ub = Ra<7:0>; }});
59 0x0d: stw({{ Mem.uw = Ra<15:0>; }});
60 0x2c: stl({{ Mem.ul = Ra<31:0>; }});
61 0x2d: stq({{ Mem.uq = Ra.uq; }});
62 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
63 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
64 0x27: stt({{ Mem.df = Fa; }});
65 0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
66 {{ fault = xc->copy(EA); }},
67 inst_flags = [IsMemRef, IsStore, IsCopy]);
71 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
73 uint64_t tmp = write_result;
75 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
76 }}, mem_flags = LOCKED);
77 0x2f: stq_c({{ Mem.uq = Ra; }},
79 uint64_t tmp = write_result;
80 // If the write operation returns 0 or 1, then
81 // this was a conventional store conditional,
82 // and the value indicates the success/failure
83 // of the operation. If another value is
84 // returned, then this was a Turbolaser
85 // mailbox access, and we don't update the
86 // result register at all.
87 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
88 }}, mem_flags = LOCKED);
91 format IntegerOperate {
93 0x10: decode INTFUNC { // integer arithmetic operations
95 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
97 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
98 // signed overflow occurs when operands have same sign
99 // and sign of result does not match.
100 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
101 fault = new IntegerOverflowFault;
104 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
105 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
107 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
109 uint64_t tmp = Ra + Rb_or_imm;
110 // signed overflow occurs when operands have same sign
111 // and sign of result does not match.
112 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
113 fault = new IntegerOverflowFault;
116 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
117 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
119 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
121 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
122 // signed overflow detection is same as for add,
123 // except we need to look at the *complemented*
124 // sign bit of the subtrahend (Rb), i.e., if the initial
125 // signs are the *same* then no overflow can occur
126 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
127 fault = new IntegerOverflowFault;
130 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
131 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
133 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
135 uint64_t tmp = Ra - Rb_or_imm;
136 // signed overflow detection is same as for add,
137 // except we need to look at the *complemented*
138 // sign bit of the subtrahend (Rb), i.e., if the initial
139 // signs are the *same* then no overflow can occur
140 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
141 fault = new IntegerOverflowFault;
144 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
145 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
147 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
148 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
149 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
150 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
151 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
157 for (int i = 0; i < 8; ++i) {
158 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
166 0x11: decode INTFUNC { // integer logical operations
168 0x00: and({{ Rc = Ra & Rb_or_imm; }});
169 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
170 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
171 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
172 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
173 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
176 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
177 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
178 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
179 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
180 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
181 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
182 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
183 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
185 // For AMASK, RA must be R31.
187 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
190 // For IMPLVER, RA must be R31 and the B operand
191 // must be the immediate value 1.
195 // return EV5 for FULL_SYSTEM and EV6 otherwise
208 // The mysterious 11.25...
209 0x25: WarnUnimpl::eleven25();
213 0x12: decode INTFUNC {
214 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
215 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
216 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
218 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
219 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
220 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
221 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
224 int bv = Rb_or_imm<2:0>;
225 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
228 int bv = Rb_or_imm<2:0>;
229 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
232 int bv = Rb_or_imm<2:0>;
233 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
236 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
237 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
238 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
239 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
242 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
244 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
246 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
248 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
249 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
250 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
251 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
254 int bv = Rb_or_imm<2:0>;
255 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
258 int bv = Rb_or_imm<2:0>;
259 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
262 int bv = Rb_or_imm<2:0>;
263 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
267 uint64_t zapmask = 0;
268 for (int i = 0; i < 8; ++i) {
270 zapmask |= (mask(8) << (i * 8));
275 uint64_t zapmask = 0;
276 for (int i = 0; i < 8; ++i) {
278 zapmask |= (mask(8) << (i * 8));
284 0x13: decode INTFUNC { // integer multiplies
285 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
286 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
289 mul128(Ra, Rb_or_imm, hi, lo);
293 // 32-bit multiply with trap on overflow
294 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
295 int64_t Rbx = Rb_or_imm.sl;
296 int64_t tmp = Rax * Rbx;
297 // To avoid overflow, all the upper 32 bits must match
298 // the sign bit of the lower 32. We code this as
299 // checking the upper 33 bits for all 0s or all 1s.
300 uint64_t sign_bits = tmp<63:31>;
301 if (sign_bits != 0 && sign_bits != mask(33))
302 fault = new IntegerOverflowFault;
306 // 64-bit multiply with trap on overflow
308 mul128(Ra, Rb_or_imm, hi, lo);
309 // all the upper 64 bits must match the sign bit of
311 if (!((hi == 0 && lo<63:> == 0) ||
312 (hi == mask(64) && lo<63:> == 1)))
313 fault = new IntegerOverflowFault;
318 0x1c: decode INTFUNC {
319 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
320 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
324 if (temp<63:32>) temp >>= 32; else count += 32;
325 if (temp<31:16>) temp >>= 16; else count += 16;
326 if (temp<15:8>) temp >>= 8; else count += 8;
327 if (temp<7:4>) temp >>= 4; else count += 4;
328 if (temp<3:2>) temp >>= 2; else count += 2;
329 if (temp<1:1>) temp >>= 1; else count += 1;
330 if ((temp<0:0>) != 0x1) count += 1;
337 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
338 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
339 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
340 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
341 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
342 if (!(temp<0:0> & ULL(0x1))) count += 1;
363 format BasicOperateWithNopCheck {
365 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
368 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
375 // Conditional branches.
377 0x39: beq({{ cond = (Ra == 0); }});
378 0x3d: bne({{ cond = (Ra != 0); }});
379 0x3e: bge({{ cond = (Ra.sq >= 0); }});
380 0x3f: bgt({{ cond = (Ra.sq > 0); }});
381 0x3b: ble({{ cond = (Ra.sq <= 0); }});
382 0x3a: blt({{ cond = (Ra.sq < 0); }});
383 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
384 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
386 0x31: fbeq({{ cond = (Fa == 0); }});
387 0x35: fbne({{ cond = (Fa != 0); }});
388 0x36: fbge({{ cond = (Fa >= 0); }});
389 0x37: fbgt({{ cond = (Fa > 0); }});
390 0x33: fble({{ cond = (Fa <= 0); }});
391 0x32: fblt({{ cond = (Fa < 0); }});
394 // unconditional branches
395 format UncondBranch {
401 0x1a: decode JMPFUNC {
406 3: jsr_coroutine(IsCall, IsReturn);
410 // Square root and integer-to-FP moves
411 0x14: decode FP_SHORTFUNC {
412 // Integer to FP register moves must have RB == 31
414 31: decode FP_FULLFUNC {
415 format BasicOperateWithNopCheck {
416 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
417 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
418 0x014: FailUnimpl::itoff(); // VAX-format conversion
423 // Square root instructions must have FA == 31
425 31: decode FP_TYPEFUNC {
426 format FloatingPointOperate {
430 fault = new ArithmeticFault;
436 fault = new ArithmeticFault;
442 fault = new ArithmeticFault;
449 // VAX-format sqrtf and sqrtg are not implemented
450 0xa: FailUnimpl::sqrtfg();
453 // IEEE floating point
454 0x16: decode FP_SHORTFUNC_TOP2 {
455 // The top two bits of the short function code break this
456 // space into four groups: binary ops, compares, reserved, and
457 // conversions. See Table 4-12 of AHB. There are different
458 // special cases in these different groups, so we decode on
459 // these top two bits first just to select a decode strategy.
460 // Most of these instructions may have various trapping and
461 // rounding mode flags set; these are decoded in the
462 // FloatingPointDecode template used by the
463 // FloatingPointOperate format.
465 // add/sub/mul/div: just decode on the short function code
466 // and source type. All valid trapping and rounding modes apply.
467 0: decode FP_TRAPMODE {
468 // check for valid trapping modes here
469 0,1,5,7: decode FP_TYPEFUNC {
470 format FloatingPointOperate {
472 0x00: adds({{ Fc = Fa + Fb; }});
473 0x01: subs({{ Fc = Fa - Fb; }});
474 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
475 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
477 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
478 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
479 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
480 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
483 0x20: addt({{ Fc = Fa + Fb; }});
484 0x21: subt({{ Fc = Fa - Fb; }});
485 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
486 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
491 // Floating-point compare instructions must have the default
492 // rounding mode, and may use the default trapping mode or
493 // /SU. Both trapping modes are treated the same by M5; the
494 // only difference on the real hardware (as far a I can tell)
495 // is that without /SU you'd get an imprecise trap if you
496 // tried to compare a NaN with something else (instead of an
497 // "unordered" result).
498 1: decode FP_FULLFUNC {
499 format BasicOperateWithNopCheck {
500 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
502 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
504 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
506 0x0a4, 0x5a4: cmptun({{ // unordered
507 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
512 // The FP-to-integer and integer-to-FP conversion insts
513 // require that FA be 31.
515 31: decode FP_TYPEFUNC {
516 format FloatingPointOperate {
517 0x2f: decode FP_ROUNDMODE {
518 format FPFixedRounding {
519 // "chopped" i.e. round toward zero
520 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
522 // round to minus infinity
523 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
526 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
529 // The cvtts opcode is overloaded to be cvtst if the trap
530 // mode is 2 or 6 (which are not valid otherwise)
531 0x2c: decode FP_FULLFUNC {
532 format BasicOperateWithNopCheck {
533 // trap on denorm version "cvtst/s" is
534 // simulated same as cvtst
535 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
537 default: cvtts({{ Fc.sf = Fb; }});
540 // The trapping mode for integer-to-FP conversions
541 // must be /SUI or nothing; /U and /SU are not
542 // allowed. The full set of rounding modes are
544 0x3c: decode FP_TRAPMODE {
545 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
547 0x3e: decode FP_TRAPMODE {
548 0,7: cvtqt({{ Fc = Fb.sq; }});
556 0x17: decode FP_FULLFUNC {
557 format BasicOperateWithNopCheck {
559 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
562 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
565 // We treat the precise & imprecise trapping versions of
566 // cvtql identically.
567 0x130, 0x530: cvtqlv({{
568 // To avoid overflow, all the upper 32 bits must match
569 // the sign bit of the lower 32. We code this as
570 // checking the upper 33 bits for all 0s or all 1s.
571 uint64_t sign_bits = Fb.uq<63:31>;
572 if (sign_bits != 0 && sign_bits != mask(33))
573 fault = new IntegerOverflowFault;
574 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
577 0x020: cpys({{ // copy sign
578 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
580 0x021: cpysn({{ // copy sign negated
581 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
583 0x022: cpyse({{ // copy sign and exponent
584 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
587 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
588 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
589 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
590 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
591 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
592 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
594 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
595 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
599 // miscellaneous mem-format ops
600 0x18: decode MEMFUNC {
607 format MiscPrefetch {
608 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
609 {{ xc->writeHint(EA, 64, memAccessFlags); }},
610 mem_flags = NO_FAULT,
611 inst_flags = [IsMemRef, IsDataPrefetch,
612 IsStore, MemWriteOp]);
615 format BasicOperate {
618 /* Rb is a fake dependency so here is a fun way to get
619 * the parser to understand that.
621 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
628 // All of the barrier instructions below do nothing in
629 // their execute() methods (hence the empty code blocks).
630 // All of their functionality is hard-coded in the
631 // pipeline based on the flags IsSerializing,
632 // IsMemBarrier, and IsWriteBarrier. In the current
633 // detailed CPU model, the execute() function only gets
634 // called at fetch, so there's no way to generate pipeline
635 // behavior at any other stage. Once we go to an
636 // exec-in-exec CPU model we should be able to get rid of
637 // these flags and implement this behavior via the
638 // execute() methods.
640 // trapb is just a barrier on integer traps, where excb is
641 // a barrier on integer and FP traps. "EXCB is thus a
642 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
643 // them the same though.
644 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
645 0x0400: excb({{ }}, IsSerializing, No_OpClass);
646 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
647 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
651 format BasicOperate {
653 Ra = xc->readIntrFlag();
655 }}, IsNonSpeculative);
657 Ra = xc->readIntrFlag();
659 }}, IsNonSpeculative);
670 0x00: CallPal::call_pal({{
673 && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
674 // invalid pal function code, or attempt to do privileged
675 // PAL call in non-kernel mode
676 fault = new UnimplementedOpcodeFault;
679 // check to see if simulator wants to do something special
680 // on this PAL call (including maybe suppress it)
681 bool dopal = xc->simPalCheck(palFunc);
684 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
685 NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
688 }}, IsNonSpeculative);
690 0x00: decode PALFUNC {
691 format EmulatedCallPal {
693 SimExit(curTick, "halt instruction encountered");
694 }}, IsNonSpeculative);
697 }}, IsNonSpeculative);
698 // Read uniq reg into ABI return value register (r0)
699 0x9e: rduniq({{ R0 = Runiq; }});
700 // Write uniq reg with value from ABI arg register (r16)
701 0x9f: wruniq({{ Runiq = R16; }});
707 0x1b: decode PALMODE {
708 0: OpcdecFault::hw_st_quad();
709 1: decode HW_LDST_QUAD {
711 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
712 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
717 0x1f: decode PALMODE {
718 0: OpcdecFault::hw_st_cond();
720 1: decode HW_LDST_COND {
721 0: decode HW_LDST_QUAD {
722 0: hw_st({{ EA = (Rb + disp) & ~3; }},
723 {{ Mem.ul = Ra<31:0>; }}, L);
724 1: hw_st({{ EA = (Rb + disp) & ~7; }},
725 {{ Mem.uq = Ra.uq; }}, Q);
728 1: FailUnimpl::hw_st_cond();
733 0x19: decode PALMODE {
734 0: OpcdecFault::hw_mfpr();
737 Ra = xc->readMiscRegWithEffect(ipr_index, fault);
742 0x1d: decode PALMODE {
743 0: OpcdecFault::hw_mtpr();
746 xc->setMiscRegWithEffect(ipr_index, Ra);
747 if (traceData) { traceData->setData(Ra); }
752 format BasicOperate {
753 0x1e: decode PALMODE {
754 0: OpcdecFault::hw_rei();
755 1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
758 // M5 special opcodes use the reserved 0x01 opcode space
759 0x01: decode M5FUNC {
761 AlphaPseudo::arm(xc->xcBase());
762 }}, IsNonSpeculative);
764 AlphaPseudo::quiesce(xc->xcBase());
765 }}, IsNonSpeculative);
767 AlphaPseudo::quiesceNs(xc->xcBase(), R16);
768 }}, IsNonSpeculative);
769 0x03: quiesceCycles({{
770 AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
771 }}, IsNonSpeculative);
773 R0 = AlphaPseudo::quiesceTime(xc->xcBase());
774 }}, IsNonSpeculative);
776 AlphaPseudo::ivlb(xc->xcBase());
777 }}, No_OpClass, IsNonSpeculative);
779 AlphaPseudo::ivle(xc->xcBase());
780 }}, No_OpClass, IsNonSpeculative);
782 AlphaPseudo::m5exit_old(xc->xcBase());
783 }}, No_OpClass, IsNonSpeculative);
785 AlphaPseudo::m5exit(xc->xcBase(), R16);
786 }}, No_OpClass, IsNonSpeculative);
787 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
789 AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
790 }}, IsNonSpeculative);
792 AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
793 }}, IsNonSpeculative);
794 0x42: dumpresetstats({{
795 AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
796 }}, IsNonSpeculative);
797 0x43: m5checkpoint({{
798 AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
799 }}, IsNonSpeculative);
801 R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
802 }}, IsNonSpeculative);
804 AlphaPseudo::debugbreak(xc->xcBase());
805 }}, IsNonSpeculative);
807 AlphaPseudo::switchcpu(xc->xcBase());
808 }}, IsNonSpeculative);
810 AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
811 }}, IsNonSpeculative);
813 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
814 }}, IsNonSpeculative);