arch/alpha/isa/main.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 output header {{
  30 #include <sstream>
  31 #include <iostream>
  32 #include <iomanip>
  33
  34 #include "config/ss_compatible_fp.hh"
  35 #include "cpu/static_inst.hh"
  36 #include "arch/alpha/faults.hh"
  37 #include "mem/mem_req.hh"  // some constructors use MemReq flags
  38 }};
  39
  40 output decoder {{
  41 #include "base/cprintf.hh"
  42 #include "base/fenv.hh"
  43 #include "base/loader/symtab.hh"
  44 #include "config/ss_compatible_fp.hh"
  45 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
  46
  47 #include <math.h>
  48
  49 using namespace AlphaISA;
  50 }};
  51
  52 output exec {{
  53 #include <math.h>
  54
  55 #if FULL_SYSTEM
  56 #include "sim/pseudo_inst.hh"
  57 #endif
  58 #include "base/fenv.hh"
  59 #include "config/ss_compatible_fp.hh"
  60 #include "cpu/base.hh"
  61 #include "cpu/exetrace.hh"
  62 #include "sim/sim_exit.hh"
  63
  64 using namespace AlphaISA;
  65 }};
  66
  67 ////////////////////////////////////////////////////////////////////
  68 //
  69 // Namespace statement.  Everything below this line will be in the
  70 // AlphaISAInst namespace.
  71 //
  72
  73
  74 namespace AlphaISA;
  75
  76 ////////////////////////////////////////////////////////////////////
  77 //
  78 // Bitfield definitions.
  79 //
  80
  81 // Universal (format-independent) fields
  82 def bitfield OPCODE     <31:26>;
  83 def bitfield RA         <25:21>;
  84 def bitfield RB         <20:16>;
  85
  86 // Memory format
  87 def signed bitfield MEMDISP <15: 0>; // displacement
  88 def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
  89
  90 // Memory-format jumps
  91 def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
  92 def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
  93
  94 // Branch format
  95 def signed bitfield BRDISP <20: 0>; // displacement
  96
  97 // Integer operate format(s>;
  98 def bitfield INTIMM     <20:13>; // integer immediate (literal)
  99 def bitfield IMM        <12:12>; // immediate flag
 100 def bitfield INTFUNC    <11: 5>; // function code
 101 def bitfield RC         < 4: 0>; // dest reg
 102
 103 // Floating-point operate format
 104 def bitfield FA           <25:21>;
 105 def bitfield FB           <20:16>;
 106 def bitfield FP_FULLFUNC  <15: 5>; // complete function code
 107     def bitfield FP_TRAPMODE  <15:13>; // trapping mode
 108     def bitfield FP_ROUNDMODE <12:11>; // rounding mode
 109     def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
 110         def bitfield FP_SRCTYPE   <10: 9>; // source reg type
 111         def bitfield FP_SHORTFUNC < 8: 5>; // short function code
 112         def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
 113 def bitfield FC           < 4: 0>; // dest reg
 114
 115 // PALcode format
 116 def bitfield PALFUNC    <25: 0>; // function code
 117
 118 // EV5 PAL instructions:
 119 // HW_LD/HW_ST
 120 def bitfield HW_LDST_PHYS  <15>; // address is physical
 121 def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
 122 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
 123 def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
 124 def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
 125 def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
 126 def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
 127 def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
 128
 129 // HW_REI
 130 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
 131 def bitfield HW_REI_MBZ <13: 0>; // must be zero
 132
 133 // HW_MTPR/MW_MFPR
 134 def bitfield HW_IPR_IDX <15:0>;  // IPR index
 135
 136 // M5 instructions
 137 def bitfield M5FUNC <7:0>;
 138
 139 def operand_types {{
 140     'sb' : ('signed int', 8),
 141     'ub' : ('unsigned int', 8),
 142     'sw' : ('signed int', 16),
 143     'uw' : ('unsigned int', 16),
 144     'sl' : ('signed int', 32),
 145     'ul' : ('unsigned int', 32),
 146     'sq' : ('signed int', 64),
 147     'uq' : ('unsigned int', 64),
 148     'sf' : ('float', 32),
 149     'df' : ('float', 64)
 150 }};
 151
 152 def operands {{
 153     # Int regs default to unsigned, but code should not count on this.
 154     # For clarity, descriptions that depend on unsigned behavior should
 155     # explicitly specify '.uq'.
 156     'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
 157     'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
 158     'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
 159     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
 160     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
 161     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
 162     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 163     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
 164     'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
 165     'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
 166     # The next two are hacks for non-full-system call-pal emulation
 167     'R0':  ('IntReg', 'uq', '0', None, 1),
 168     'R16': ('IntReg', 'uq', '16', None, 1),
 169     'R17': ('IntReg', 'uq', '17', None, 1),
 170     'R18': ('IntReg', 'uq', '18', None, 1)
 171 }};
 172
 173 ////////////////////////////////////////////////////////////////////
 174 //
 175 // Basic instruction classes/templates/formats etc.
 176 //
 177
 178 output header {{
 179 // uncomment the following to get SimpleScalar-compatible disassembly
 180 // (useful for diffing output traces).
 181 // #define SS_COMPATIBLE_DISASSEMBLY
 182
 183     /**
 184      * Base class for all Alpha static instructions.
 185      */
 186     class AlphaStaticInst : public StaticInst
 187     {
 188       protected:
 189
 190         /// Make AlphaISA register dependence tags directly visible in
 191         /// this class and derived classes.  Maybe these should really
 192         /// live here and not in the AlphaISA namespace.
 193         enum DependenceTags {
 194             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
 195             Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
 196             Uniq_DepTag = AlphaISA::Uniq_DepTag,
 197             Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
 198             Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
 199             IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
 200         };
 201
 202         /// Constructor.
 203         AlphaStaticInst(const char *mnem, MachInst _machInst,
 204                         OpClass __opClass)
 205             : StaticInst(mnem, _machInst, __opClass)
 206         {
 207         }
 208
 209         /// Print a register name for disassembly given the unique
 210         /// dependence tag number (FP or int).
 211         void printReg(std::ostream &os, int reg) const;
 212
 213         std::string
 214         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 215     };
 216 }};
 217
 218 output decoder {{
 219     void
 220     AlphaStaticInst::printReg(std::ostream &os, int reg) const
 221     {
 222         if (reg < FP_Base_DepTag) {
 223             ccprintf(os, "r%d", reg);
 224         }
 225         else {
 226             ccprintf(os, "f%d", reg - FP_Base_DepTag);
 227         }
 228     }
 229
 230     std::string
 231     AlphaStaticInst::generateDisassembly(Addr pc,
 232                                          const SymbolTable *symtab) const
 233     {
 234         std::stringstream ss;
 235
 236         ccprintf(ss, "%-10s ", mnemonic);
 237
 238         // just print the first two source regs... if there's
 239         // a third one, it's a read-modify-write dest (Rc),
 240         // e.g. for CMOVxx
 241         if (_numSrcRegs > 0) {
 242             printReg(ss, _srcRegIdx[0]);
 243         }
 244         if (_numSrcRegs > 1) {
 245             ss << ",";
 246             printReg(ss, _srcRegIdx[1]);
 247         }
 248
 249         // just print the first dest... if there's a second one,
 250         // it's generally implicit
 251         if (_numDestRegs > 0) {
 252             if (_numSrcRegs > 0)
 253                 ss << ",";
 254             printReg(ss, _destRegIdx[0]);
 255         }
 256
 257         return ss.str();
 258     }
 259 }};
 260
 261 // Declarations for execute() methods.
 262 def template BasicExecDeclare {{
 263     Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 264 }};
 265
 266 // Basic instruction class declaration template.
 267 def template BasicDeclare {{
 268     /**
 269      * Static instruction class for "%(mnemonic)s".
 270      */
 271     class %(class_name)s : public %(base_class)s
 272     {
 273       public:
 274         /// Constructor.
 275         %(class_name)s(MachInst machInst);
 276
 277         %(BasicExecDeclare)s
 278     };
 279 }};
 280
 281 // Basic instruction class constructor template.
 282 def template BasicConstructor {{
 283     inline %(class_name)s::%(class_name)s(MachInst machInst)
 284          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 285     {
 286         %(constructor)s;
 287     }
 288 }};
 289
 290 // Basic instruction class execute method template.
 291 def template BasicExecute {{
 292     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 293                                   Trace::InstRecord *traceData) const
 294     {
 295         Fault fault = NoFault;
 296
 297         %(fp_enable_check)s;
 298         %(op_decl)s;
 299         %(op_rd)s;
 300         %(code)s;
 301
 302         if (fault == NoFault) {
 303             %(op_wb)s;
 304         }
 305
 306         return fault;
 307     }
 308 }};
 309
 310 // Basic decode template.
 311 def template BasicDecode {{
 312     return new %(class_name)s(machInst);
 313 }};
 314
 315 // Basic decode template, passing mnemonic in as string arg to constructor.
 316 def template BasicDecodeWithMnemonic {{
 317     return new %(class_name)s("%(mnemonic)s", machInst);
 318 }};
 319
 320 // The most basic instruction format... used only for a few misc. insts
 321 def format BasicOperate(code, *flags) {{
 322     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
 323     header_output = BasicDeclare.subst(iop)
 324     decoder_output = BasicConstructor.subst(iop)
 325     decode_block = BasicDecode.subst(iop)
 326     exec_output = BasicExecute.subst(iop)
 327 }};
 328
 329
 330
 331 ////////////////////////////////////////////////////////////////////
 332 //
 333 // Nop
 334 //
 335
 336 output header {{
 337     /**
 338      * Static instruction class for no-ops.  This is a leaf class.
 339      */
 340     class Nop : public AlphaStaticInst
 341     {
 342         /// Disassembly of original instruction.
 343         const std::string originalDisassembly;
 344
 345       public:
 346         /// Constructor
 347         Nop(const std::string _originalDisassembly, MachInst _machInst)
 348             : AlphaStaticInst("nop", _machInst, No_OpClass),
 349               originalDisassembly(_originalDisassembly)
 350         {
 351             flags[IsNop] = true;
 352         }
 353
 354         ~Nop() { }
 355
 356         std::string
 357         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 358
 359         %(BasicExecDeclare)s
 360     };
 361
 362     /// Helper function for decoding nops.  Substitute Nop object
 363     /// for original inst passed in as arg (and delete latter).
 364     static inline
 365     AlphaStaticInst *
 366     makeNop(AlphaStaticInst *inst)
 367     {
 368         AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
 369         delete inst;
 370         return nop;
 371     }
 372 }};
 373
 374 output decoder {{
 375     std::string Nop::generateDisassembly(Addr pc,
 376                                          const SymbolTable *symtab) const
 377     {
 378 #ifdef SS_COMPATIBLE_DISASSEMBLY
 379         return originalDisassembly;
 380 #else
 381         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 382 #endif
 383     }
 384 }};
 385
 386 output exec {{
 387     Fault
 388     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
 389     {
 390         return NoFault;
 391     }
 392 }};
 393
 394 // integer & FP operate instructions use Rc as dest, so check for
 395 // Rc == 31 to detect nops
 396 def template OperateNopCheckDecode {{
 397  {
 398      AlphaStaticInst *i = new %(class_name)s(machInst);
 399      if (RC == 31) {
 400          i = makeNop(i);
 401      }
 402      return i;
 403  }
 404 }};
 405
 406 // Like BasicOperate format, but generates NOP if RC/FC == 31
 407 def format BasicOperateWithNopCheck(code, *opt_args) {{
 408     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
 409                         opt_args)
 410     header_output = BasicDeclare.subst(iop)
 411     decoder_output = BasicConstructor.subst(iop)
 412     decode_block = OperateNopCheckDecode.subst(iop)
 413     exec_output = BasicExecute.subst(iop)
 414 }};
 415
 416 // Integer instruction templates, formats, etc.
 417 ##include "m5/arch/alpha/isa/int.isa"
 418
 419 // Floating-point instruction templates, formats, etc.
 420 ##include "m5/arch/alpha/isa/fp.isa"
 421
 422 // Memory instruction templates, formats, etc.
 423 ##include "m5/arch/alpha/isa/mem.isa"
 424
 425 // Branch/jump instruction templates, formats, etc.
 426 ##include "m5/arch/alpha/isa/branch.isa"
 427
 428 // PAL instruction templates, formats, etc.
 429 ##include "m5/arch/alpha/isa/pal.isa"
 430
 431 // Unimplemented instruction templates, formats, etc.
 432 ##include "m5/arch/alpha/isa/unimp.isa"
 433
 434 // Unknown instruction templates, formats, etc.
 435 ##include "m5/arch/alpha/isa/unknown.isa"
 436
 437 // Execution utility functions
 438 ##include "m5/arch/alpha/isa/util.isa"
 439
 440 // The actual decoder
 441 ##include "m5/arch/alpha/isa/decoder.isa"