arch/alpha/isa/main.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 output header {{
  30 #include <sstream>
  31 #include <iostream>
  32 #include <iomanip>
  33
  34 #include "config/ss_compatible_fp.hh"
  35 #include "cpu/static_inst.hh"
  36 #include "arch/alpha/faults.hh"
  37 #include "mem/request.hh"  // some constructors use MemReq flags
  38 }};
  39
  40 output decoder {{
  41 #include "base/cprintf.hh"
  42 #include "base/fenv.hh"
  43 #include "base/loader/symtab.hh"
  44 #include "config/ss_compatible_fp.hh"
  45 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
  46
  47 #include <math.h>
  48
  49 using namespace AlphaISA;
  50 }};
  51
  52 output exec {{
  53 #include <math.h>
  54
  55 #if FULL_SYSTEM
  56 #include "sim/pseudo_inst.hh"
  57 #endif
  58 #include "base/fenv.hh"
  59 #include "config/ss_compatible_fp.hh"
  60 #include "cpu/base.hh"
  61 #include "cpu/exetrace.hh"
  62 #include "sim/sim_exit.hh"
  63
  64 using namespace AlphaISA;
  65 }};
  66
  67 ////////////////////////////////////////////////////////////////////
  68 //
  69 // Namespace statement.  Everything below this line will be in the
  70 // AlphaISAInst namespace.
  71 //
  72
  73
  74 namespace AlphaISA;
  75
  76 ////////////////////////////////////////////////////////////////////
  77 //
  78 // Bitfield definitions.
  79 //
  80
  81 // Universal (format-independent) fields
  82 def bitfield PALMODE    <32:32>;
  83 def bitfield OPCODE     <31:26>;
  84 def bitfield RA         <25:21>;
  85 def bitfield RB         <20:16>;
  86
  87 // Memory format
  88 def signed bitfield MEMDISP <15: 0>; // displacement
  89 def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
  90
  91 // Memory-format jumps
  92 def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
  93 def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
  94
  95 // Branch format
  96 def signed bitfield BRDISP <20: 0>; // displacement
  97
  98 // Integer operate format(s>;
  99 def bitfield INTIMM     <20:13>; // integer immediate (literal)
 100 def bitfield IMM        <12:12>; // immediate flag
 101 def bitfield INTFUNC    <11: 5>; // function code
 102 def bitfield RC         < 4: 0>; // dest reg
 103
 104 // Floating-point operate format
 105 def bitfield FA           <25:21>;
 106 def bitfield FB           <20:16>;
 107 def bitfield FP_FULLFUNC  <15: 5>; // complete function code
 108     def bitfield FP_TRAPMODE  <15:13>; // trapping mode
 109     def bitfield FP_ROUNDMODE <12:11>; // rounding mode
 110     def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
 111         def bitfield FP_SRCTYPE   <10: 9>; // source reg type
 112         def bitfield FP_SHORTFUNC < 8: 5>; // short function code
 113         def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
 114 def bitfield FC           < 4: 0>; // dest reg
 115
 116 // PALcode format
 117 def bitfield PALFUNC    <25: 0>; // function code
 118
 119 // EV5 PAL instructions:
 120 // HW_LD/HW_ST
 121 def bitfield HW_LDST_PHYS  <15>; // address is physical
 122 def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
 123 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
 124 def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
 125 def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
 126 def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
 127 def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
 128 def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
 129
 130 // HW_REI
 131 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
 132 def bitfield HW_REI_MBZ <13: 0>; // must be zero
 133
 134 // HW_MTPR/MW_MFPR
 135 def bitfield HW_IPR_IDX <15:0>;  // IPR index
 136
 137 // M5 instructions
 138 def bitfield M5FUNC <7:0>;
 139
 140 def operand_types {{
 141     'sb' : ('signed int', 8),
 142     'ub' : ('unsigned int', 8),
 143     'sw' : ('signed int', 16),
 144     'uw' : ('unsigned int', 16),
 145     'sl' : ('signed int', 32),
 146     'ul' : ('unsigned int', 32),
 147     'sq' : ('signed int', 64),
 148     'uq' : ('unsigned int', 64),
 149     'sf' : ('float', 32),
 150     'df' : ('float', 64)
 151 }};
 152
 153 def operands {{
 154     # Int regs default to unsigned, but code should not count on this.
 155     # For clarity, descriptions that depend on unsigned behavior should
 156     # explicitly specify '.uq'.
 157     'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
 158            'IsInteger', 1),
 159     'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
 160            'IsInteger', 2),
 161     'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
 162            'IsInteger', 3),
 163     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
 164     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
 165     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
 166     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 167     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
 168     'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
 169     'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
 170     # The next two are hacks for non-full-system call-pal emulation
 171     'R0':  ('IntReg', 'uq', '0', None, 1),
 172     'R16': ('IntReg', 'uq', '16', None, 1),
 173     'R17': ('IntReg', 'uq', '17', None, 1),
 174     'R18': ('IntReg', 'uq', '18', None, 1)
 175 }};
 176
 177 ////////////////////////////////////////////////////////////////////
 178 //
 179 // Basic instruction classes/templates/formats etc.
 180 //
 181
 182 output header {{
 183 // uncomment the following to get SimpleScalar-compatible disassembly
 184 // (useful for diffing output traces).
 185 // #define SS_COMPATIBLE_DISASSEMBLY
 186
 187     /**
 188      * Base class for all Alpha static instructions.
 189      */
 190     class AlphaStaticInst : public StaticInst
 191     {
 192       protected:
 193
 194         /// Make AlphaISA register dependence tags directly visible in
 195         /// this class and derived classes.  Maybe these should really
 196         /// live here and not in the AlphaISA namespace.
 197         enum DependenceTags {
 198             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
 199             Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
 200             Uniq_DepTag = AlphaISA::Uniq_DepTag,
 201             Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
 202             Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
 203             IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
 204         };
 205
 206         /// Constructor.
 207         AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
 208                         OpClass __opClass)
 209             : StaticInst(mnem, _machInst, __opClass)
 210         {
 211         }
 212
 213         /// Print a register name for disassembly given the unique
 214         /// dependence tag number (FP or int).
 215         void printReg(std::ostream &os, int reg) const;
 216
 217         std::string
 218         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 219     };
 220 }};
 221
 222 output decoder {{
 223     void
 224     AlphaStaticInst::printReg(std::ostream &os, int reg) const
 225     {
 226         if (reg < FP_Base_DepTag) {
 227             ccprintf(os, "r%d", reg);
 228         }
 229         else {
 230             ccprintf(os, "f%d", reg - FP_Base_DepTag);
 231         }
 232     }
 233
 234     std::string
 235     AlphaStaticInst::generateDisassembly(Addr pc,
 236                                          const SymbolTable *symtab) const
 237     {
 238         std::stringstream ss;
 239
 240         ccprintf(ss, "%-10s ", mnemonic);
 241
 242         // just print the first two source regs... if there's
 243         // a third one, it's a read-modify-write dest (Rc),
 244         // e.g. for CMOVxx
 245         if (_numSrcRegs > 0) {
 246             printReg(ss, _srcRegIdx[0]);
 247         }
 248         if (_numSrcRegs > 1) {
 249             ss << ",";
 250             printReg(ss, _srcRegIdx[1]);
 251         }
 252
 253         // just print the first dest... if there's a second one,
 254         // it's generally implicit
 255         if (_numDestRegs > 0) {
 256             if (_numSrcRegs > 0)
 257                 ss << ",";
 258             printReg(ss, _destRegIdx[0]);
 259         }
 260
 261         return ss.str();
 262     }
 263 }};
 264
 265 // Declarations for execute() methods.
 266 def template BasicExecDeclare {{
 267     Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 268 }};
 269
 270 // Basic instruction class declaration template.
 271 def template BasicDeclare {{
 272     /**
 273      * Static instruction class for "%(mnemonic)s".
 274      */
 275     class %(class_name)s : public %(base_class)s
 276     {
 277       public:
 278         /// Constructor.
 279         %(class_name)s(ExtMachInst machInst);
 280
 281         %(BasicExecDeclare)s
 282     };
 283 }};
 284
 285 // Basic instruction class constructor template.
 286 def template BasicConstructor {{
 287     inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
 288          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 289     {
 290         %(constructor)s;
 291     }
 292 }};
 293
 294 // Basic instruction class execute method template.
 295 def template BasicExecute {{
 296     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 297                                   Trace::InstRecord *traceData) const
 298     {
 299         Fault fault = NoFault;
 300
 301         %(fp_enable_check)s;
 302         %(op_decl)s;
 303         %(op_rd)s;
 304         %(code)s;
 305
 306         if (fault == NoFault) {
 307             %(op_wb)s;
 308         }
 309
 310         return fault;
 311     }
 312 }};
 313
 314 // Basic decode template.
 315 def template BasicDecode {{
 316     return new %(class_name)s(machInst);
 317 }};
 318
 319 // Basic decode template, passing mnemonic in as string arg to constructor.
 320 def template BasicDecodeWithMnemonic {{
 321     return new %(class_name)s("%(mnemonic)s", machInst);
 322 }};
 323
 324 // The most basic instruction format... used only for a few misc. insts
 325 def format BasicOperate(code, *flags) {{
 326     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
 327     header_output = BasicDeclare.subst(iop)
 328     decoder_output = BasicConstructor.subst(iop)
 329     decode_block = BasicDecode.subst(iop)
 330     exec_output = BasicExecute.subst(iop)
 331 }};
 332
 333
 334
 335 ////////////////////////////////////////////////////////////////////
 336 //
 337 // Nop
 338 //
 339
 340 output header {{
 341     /**
 342      * Static instruction class for no-ops.  This is a leaf class.
 343      */
 344     class Nop : public AlphaStaticInst
 345     {
 346         /// Disassembly of original instruction.
 347         const std::string originalDisassembly;
 348
 349       public:
 350         /// Constructor
 351         Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
 352             : AlphaStaticInst("nop", _machInst, No_OpClass),
 353               originalDisassembly(_originalDisassembly)
 354         {
 355             flags[IsNop] = true;
 356         }
 357
 358         ~Nop() { }
 359
 360         std::string
 361         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 362
 363         %(BasicExecDeclare)s
 364     };
 365
 366     /// Helper function for decoding nops.  Substitute Nop object
 367     /// for original inst passed in as arg (and delete latter).
 368     static inline
 369     AlphaStaticInst *
 370     makeNop(AlphaStaticInst *inst)
 371     {
 372         AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
 373         delete inst;
 374         return nop;
 375     }
 376 }};
 377
 378 output decoder {{
 379     std::string Nop::generateDisassembly(Addr pc,
 380                                          const SymbolTable *symtab) const
 381     {
 382 #ifdef SS_COMPATIBLE_DISASSEMBLY
 383         return originalDisassembly;
 384 #else
 385         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 386 #endif
 387     }
 388 }};
 389
 390 output exec {{
 391     Fault
 392     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
 393     {
 394         return NoFault;
 395     }
 396 }};
 397
 398 // integer & FP operate instructions use Rc as dest, so check for
 399 // Rc == 31 to detect nops
 400 def template OperateNopCheckDecode {{
 401  {
 402      AlphaStaticInst *i = new %(class_name)s(machInst);
 403      if (RC == 31) {
 404          i = makeNop(i);
 405      }
 406      return i;
 407  }
 408 }};
 409
 410 // Like BasicOperate format, but generates NOP if RC/FC == 31
 411 def format BasicOperateWithNopCheck(code, *opt_args) {{
 412     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
 413                         opt_args)
 414     header_output = BasicDeclare.subst(iop)
 415     decoder_output = BasicConstructor.subst(iop)
 416     decode_block = OperateNopCheckDecode.subst(iop)
 417     exec_output = BasicExecute.subst(iop)
 418 }};
 419
 420 // Integer instruction templates, formats, etc.
 421 ##include "int.isa"
 422
 423 // Floating-point instruction templates, formats, etc.
 424 ##include "fp.isa"
 425
 426 // Memory instruction templates, formats, etc.
 427 ##include "mem.isa"
 428
 429 // Branch/jump instruction templates, formats, etc.
 430 ##include "branch.isa"
 431
 432 // PAL instruction templates, formats, etc.
 433 ##include "pal.isa"
 434
 435 // Opcdec fault instruction templates, formats, etc.
 436 ##include "opcdec.isa"
 437
 438 // Unimplemented instruction templates, formats, etc.
 439 ##include "unimp.isa"
 440
 441 // Unknown instruction templates, formats, etc.
 442 ##include "unknown.isa"
 443
 444 // Execution utility functions
 445 ##include "util.isa"
 446
 447 // The actual decoder
 448 ##include "decoder.isa"