arch/alpha/isa/main.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 output header {{
  30 #include <sstream>
  31 #include <iostream>
  32 #include <iomanip>
  33
  34 #include "config/ss_compatible_fp.hh"
  35 #include "cpu/static_inst.hh"
  36 #include "mem/mem_req.hh"  // some constructors use MemReq flags
  37 }};
  38
  39 output decoder {{
  40 #include "base/cprintf.hh"
  41 #include "base/fenv.hh"
  42 #include "base/loader/symtab.hh"
  43 #include "config/ss_compatible_fp.hh"
  44 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
  45
  46 #include <math.h>
  47 }};
  48
  49 output exec {{
  50 #include <math.h>
  51
  52 #if FULL_SYSTEM
  53 #include "arch/alpha/pseudo_inst.hh"
  54 #endif
  55 #include "base/fenv.hh"
  56 #include "config/ss_compatible_fp.hh"
  57 #include "cpu/base.hh"
  58 #include "cpu/exetrace.hh"
  59 #include "sim/sim_exit.hh"
  60 }};
  61
  62 ////////////////////////////////////////////////////////////////////
  63 //
  64 // Namespace statement.  Everything below this line will be in the
  65 // AlphaISAInst namespace.
  66 //
  67
  68
  69 namespace AlphaISA;
  70
  71 ////////////////////////////////////////////////////////////////////
  72 //
  73 // Bitfield definitions.
  74 //
  75
  76 // Universal (format-independent) fields
  77 def bitfield OPCODE     <31:26>;
  78 def bitfield RA         <25:21>;
  79 def bitfield RB         <20:16>;
  80
  81 // Memory format
  82 def signed bitfield MEMDISP <15: 0>; // displacement
  83 def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
  84
  85 // Memory-format jumps
  86 def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
  87 def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
  88
  89 // Branch format
  90 def signed bitfield BRDISP <20: 0>; // displacement
  91
  92 // Integer operate format(s>;
  93 def bitfield INTIMM     <20:13>; // integer immediate (literal)
  94 def bitfield IMM        <12:12>; // immediate flag
  95 def bitfield INTFUNC    <11: 5>; // function code
  96 def bitfield RC         < 4: 0>; // dest reg
  97
  98 // Floating-point operate format
  99 def bitfield FA           <25:21>;
 100 def bitfield FB           <20:16>;
 101 def bitfield FP_FULLFUNC  <15: 5>; // complete function code
 102     def bitfield FP_TRAPMODE  <15:13>; // trapping mode
 103     def bitfield FP_ROUNDMODE <12:11>; // rounding mode
 104     def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
 105         def bitfield FP_SRCTYPE   <10: 9>; // source reg type
 106         def bitfield FP_SHORTFUNC < 8: 5>; // short function code
 107         def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
 108 def bitfield FC           < 4: 0>; // dest reg
 109
 110 // PALcode format
 111 def bitfield PALFUNC    <25: 0>; // function code
 112
 113 // EV5 PAL instructions:
 114 // HW_LD/HW_ST
 115 def bitfield HW_LDST_PHYS  <15>; // address is physical
 116 def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
 117 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
 118 def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
 119 def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
 120 def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
 121 def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
 122 def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
 123
 124 // HW_REI
 125 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
 126 def bitfield HW_REI_MBZ <13: 0>; // must be zero
 127
 128 // HW_MTPR/MW_MFPR
 129 def bitfield HW_IPR_IDX <15:0>;  // IPR index
 130
 131 // M5 instructions
 132 def bitfield M5FUNC <7:0>;
 133
 134 def operand_types {{
 135     'sb' : ('signed int', 8),
 136     'ub' : ('unsigned int', 8),
 137     'sw' : ('signed int', 16),
 138     'uw' : ('unsigned int', 16),
 139     'sl' : ('signed int', 32),
 140     'ul' : ('unsigned int', 32),
 141     'sq' : ('signed int', 64),
 142     'uq' : ('unsigned int', 64),
 143     'sf' : ('float', 32),
 144     'df' : ('float', 64)
 145 }};
 146
 147 def operands {{
 148     # Int regs default to unsigned, but code should not count on this.
 149     # For clarity, descriptions that depend on unsigned behavior should
 150     # explicitly specify '.uq'.
 151     'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
 152     'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
 153     'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
 154     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
 155     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
 156     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
 157     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 158     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
 159     'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
 160     'FPCR':  (' ControlReg', 'uq', 'Fpcr', None, 1),
 161     # The next two are hacks for non-full-system call-pal emulation
 162     'R0':  ('IntReg', 'uq', '0', None, 1),
 163     'R16': ('IntReg', 'uq', '16', None, 1)
 164 }};
 165
 166 ////////////////////////////////////////////////////////////////////
 167 //
 168 // Basic instruction classes/templates/formats etc.
 169 //
 170
 171 output header {{
 172 // uncomment the following to get SimpleScalar-compatible disassembly
 173 // (useful for diffing output traces).
 174 // #define SS_COMPATIBLE_DISASSEMBLY
 175
 176     /**
 177      * Base class for all Alpha static instructions.
 178      */
 179     class AlphaStaticInst : public StaticInst<AlphaISA>
 180     {
 181       protected:
 182
 183         /// Make AlphaISA register dependence tags directly visible in
 184         /// this class and derived classes.  Maybe these should really
 185         /// live here and not in the AlphaISA namespace.
 186         enum DependenceTags {
 187             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
 188             Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
 189             Uniq_DepTag = AlphaISA::Uniq_DepTag,
 190             IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
 191         };
 192
 193         /// Constructor.
 194         AlphaStaticInst(const char *mnem, MachInst _machInst,
 195                         OpClass __opClass)
 196             : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
 197         {
 198         }
 199
 200         /// Print a register name for disassembly given the unique
 201         /// dependence tag number (FP or int).
 202         void printReg(std::ostream &os, int reg) const;
 203
 204         std::string
 205         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 206     };
 207 }};
 208
 209 output decoder {{
 210     void
 211     AlphaStaticInst::printReg(std::ostream &os, int reg) const
 212     {
 213         if (reg < FP_Base_DepTag) {
 214             ccprintf(os, "r%d", reg);
 215         }
 216         else {
 217             ccprintf(os, "f%d", reg - FP_Base_DepTag);
 218         }
 219     }
 220
 221     std::string
 222     AlphaStaticInst::generateDisassembly(Addr pc,
 223                                          const SymbolTable *symtab) const
 224     {
 225         std::stringstream ss;
 226
 227         ccprintf(ss, "%-10s ", mnemonic);
 228
 229         // just print the first two source regs... if there's
 230         // a third one, it's a read-modify-write dest (Rc),
 231         // e.g. for CMOVxx
 232         if (_numSrcRegs > 0) {
 233             printReg(ss, _srcRegIdx[0]);
 234         }
 235         if (_numSrcRegs > 1) {
 236             ss << ",";
 237             printReg(ss, _srcRegIdx[1]);
 238         }
 239
 240         // just print the first dest... if there's a second one,
 241         // it's generally implicit
 242         if (_numDestRegs > 0) {
 243             if (_numSrcRegs > 0)
 244                 ss << ",";
 245             printReg(ss, _destRegIdx[0]);
 246         }
 247
 248         return ss.str();
 249     }
 250 }};
 251
 252 // Declarations for execute() methods.
 253 def template BasicExecDeclare {{
 254     Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 255 }};
 256
 257 // Basic instruction class declaration template.
 258 def template BasicDeclare {{
 259     /**
 260      * Static instruction class for "%(mnemonic)s".
 261      */
 262     class %(class_name)s : public %(base_class)s
 263     {
 264       public:
 265         /// Constructor.
 266         %(class_name)s(MachInst machInst);
 267
 268         %(BasicExecDeclare)s
 269     };
 270 }};
 271
 272 // Basic instruction class constructor template.
 273 def template BasicConstructor {{
 274     inline %(class_name)s::%(class_name)s(MachInst machInst)
 275          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 276     {
 277         %(constructor)s;
 278     }
 279 }};
 280
 281 // Basic instruction class execute method template.
 282 def template BasicExecute {{
 283     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 284                                   Trace::InstRecord *traceData) const
 285     {
 286         Fault fault = No_Fault;
 287
 288         %(fp_enable_check)s;
 289         %(op_decl)s;
 290         %(op_rd)s;
 291         %(code)s;
 292
 293         if (fault == No_Fault) {
 294             %(op_wb)s;
 295         }
 296
 297         return fault;
 298     }
 299 }};
 300
 301 // Basic decode template.
 302 def template BasicDecode {{
 303     return new %(class_name)s(machInst);
 304 }};
 305
 306 // Basic decode template, passing mnemonic in as string arg to constructor.
 307 def template BasicDecodeWithMnemonic {{
 308     return new %(class_name)s("%(mnemonic)s", machInst);
 309 }};
 310
 311 // The most basic instruction format... used only for a few misc. insts
 312 def format BasicOperate(code, *flags) {{
 313     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
 314     header_output = BasicDeclare.subst(iop)
 315     decoder_output = BasicConstructor.subst(iop)
 316     decode_block = BasicDecode.subst(iop)
 317     exec_output = BasicExecute.subst(iop)
 318 }};
 319
 320
 321
 322 ////////////////////////////////////////////////////////////////////
 323 //
 324 // Nop
 325 //
 326
 327 output header {{
 328     /**
 329      * Static instruction class for no-ops.  This is a leaf class.
 330      */
 331     class Nop : public AlphaStaticInst
 332     {
 333         /// Disassembly of original instruction.
 334         const std::string originalDisassembly;
 335
 336       public:
 337         /// Constructor
 338         Nop(const std::string _originalDisassembly, MachInst _machInst)
 339             : AlphaStaticInst("nop", _machInst, No_OpClass),
 340               originalDisassembly(_originalDisassembly)
 341         {
 342             flags[IsNop] = true;
 343         }
 344
 345         ~Nop() { }
 346
 347         std::string
 348         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 349
 350         %(BasicExecDeclare)s
 351     };
 352 }};
 353
 354 output decoder {{
 355     std::string Nop::generateDisassembly(Addr pc,
 356                                          const SymbolTable *symtab) const
 357     {
 358 #ifdef SS_COMPATIBLE_DISASSEMBLY
 359         return originalDisassembly;
 360 #else
 361         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 362 #endif
 363     }
 364
 365     /// Helper function for decoding nops.  Substitute Nop object
 366     /// for original inst passed in as arg (and delete latter).
 367     inline
 368     AlphaStaticInst *
 369     makeNop(AlphaStaticInst *inst)
 370     {
 371         AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
 372         delete inst;
 373         return nop;
 374     }
 375 }};
 376
 377 output exec {{
 378     Fault
 379     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
 380     {
 381         return No_Fault;
 382     }
 383 }};
 384
 385 // integer & FP operate instructions use Rc as dest, so check for
 386 // Rc == 31 to detect nops
 387 def template OperateNopCheckDecode {{
 388  {
 389      AlphaStaticInst *i = new %(class_name)s(machInst);
 390      if (RC == 31) {
 391          i = makeNop(i);
 392      }
 393      return i;
 394  }
 395 }};
 396
 397 // Like BasicOperate format, but generates NOP if RC/FC == 31
 398 def format BasicOperateWithNopCheck(code, *opt_args) {{
 399     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
 400                         opt_args)
 401     header_output = BasicDeclare.subst(iop)
 402     decoder_output = BasicConstructor.subst(iop)
 403     decode_block = OperateNopCheckDecode.subst(iop)
 404     exec_output = BasicExecute.subst(iop)
 405 }};
 406
 407 // Integer instruction templates, formats, etc.
 408 ##include "m5/arch/alpha/isa/int.isa"
 409
 410 // Floating-point instruction templates, formats, etc.
 411 ##include "m5/arch/alpha/isa/fp.isa"
 412
 413 // Memory instruction templates, formats, etc.
 414 ##include "m5/arch/alpha/isa/mem.isa"
 415
 416 // Branch/jump instruction templates, formats, etc.
 417 ##include "m5/arch/alpha/isa/branch.isa"
 418
 419 // PAL instruction templates, formats, etc.
 420 ##include "m5/arch/alpha/isa/pal.isa"
 421
 422 // Unimplemented instruction templates, formats, etc.
 423 ##include "m5/arch/alpha/isa/unimp.isa"
 424
 425 // Unknown instruction templates, formats, etc.
 426 ##include "m5/arch/alpha/isa/unknown.isa"
 427
 428 // Execution utility functions
 429 ##include "m5/arch/alpha/isa/util.isa"
 430
 431 // The actual decoder
 432 ##include "m5/arch/alpha/isa/decoder.isa"