3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // All rights reserved.
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15 // this software without specific prior written permission.
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34 #include "config/ss_compatible_fp.hh"
35 #include "cpu/static_inst.hh"
36 #include "mem/mem_req.hh" // some constructors use MemReq flags
40 #include "base/cprintf.hh"
41 #include "base/fenv.hh"
42 #include "base/loader/symtab.hh"
43 #include "config/ss_compatible_fp.hh"
44 #include "cpu/exec_context.hh" // for Jump::branchTarget()
53 #include "arch/alpha/pseudo_inst.hh"
55 #include "base/fenv.hh"
56 #include "config/ss_compatible_fp.hh"
57 #include "cpu/base.hh"
58 #include "cpu/exetrace.hh"
59 #include "sim/sim_exit.hh"
62 ////////////////////////////////////////////////////////////////////
64 // Namespace statement. Everything below this line will be in the
65 // AlphaISAInst namespace.
71 ////////////////////////////////////////////////////////////////////
73 // Bitfield definitions.
76 // Universal (format-independent) fields
77 def bitfield OPCODE <31:26>;
78 def bitfield RA <25:21>;
79 def bitfield RB <20:16>;
82 def signed bitfield MEMDISP <15: 0>; // displacement
83 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
85 // Memory-format jumps
86 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
87 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
90 def signed bitfield BRDISP <20: 0>; // displacement
92 // Integer operate format(s>;
93 def bitfield INTIMM <20:13>; // integer immediate (literal)
94 def bitfield IMM <12:12>; // immediate flag
95 def bitfield INTFUNC <11: 5>; // function code
96 def bitfield RC < 4: 0>; // dest reg
98 // Floating-point operate format
99 def bitfield FA <25:21>;
100 def bitfield FB <20:16>;
101 def bitfield FP_FULLFUNC <15: 5>; // complete function code
102 def bitfield FP_TRAPMODE <15:13>; // trapping mode
103 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
104 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
105 def bitfield FP_SRCTYPE <10: 9>; // source reg type
106 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
107 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
108 def bitfield FC < 4: 0>; // dest reg
111 def bitfield PALFUNC <25: 0>; // function code
113 // EV5 PAL instructions:
115 def bitfield HW_LDST_PHYS <15>; // address is physical
116 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
117 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
118 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
119 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
120 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
121 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
122 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
125 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
126 def bitfield HW_REI_MBZ <13: 0>; // must be zero
129 def bitfield HW_IPR_IDX <15:0>; // IPR index
132 def bitfield M5FUNC <7:0>;
135 'sb' : ('signed int', 8),
136 'ub' : ('unsigned int', 8),
137 'sw' : ('signed int', 16),
138 'uw' : ('unsigned int', 16),
139 'sl' : ('signed int', 32),
140 'ul' : ('unsigned int', 32),
141 'sq' : ('signed int', 64),
142 'uq' : ('unsigned int', 64),
143 'sf' : ('float', 32),
148 # Int regs default to unsigned, but code should not count on this.
149 # For clarity, descriptions that depend on unsigned behavior should
150 # explicitly specify '.uq'.
151 'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
152 'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
153 'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
154 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
155 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
156 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
157 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
158 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
159 'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
160 'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1),
161 # The next two are hacks for non-full-system call-pal emulation
162 'R0': ('IntReg', 'uq', '0', None, 1),
163 'R16': ('IntReg', 'uq', '16', None, 1)
166 ////////////////////////////////////////////////////////////////////
168 // Basic instruction classes/templates/formats etc.
172 // uncomment the following to get SimpleScalar-compatible disassembly
173 // (useful for diffing output traces).
174 // #define SS_COMPATIBLE_DISASSEMBLY
177 * Base class for all Alpha static instructions.
179 class AlphaStaticInst : public StaticInst<AlphaISA>
183 /// Make AlphaISA register dependence tags directly visible in
184 /// this class and derived classes. Maybe these should really
185 /// live here and not in the AlphaISA namespace.
186 enum DependenceTags {
187 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
188 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
189 Uniq_DepTag = AlphaISA::Uniq_DepTag,
190 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
194 AlphaStaticInst(const char *mnem, MachInst _machInst,
196 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
200 /// Print a register name for disassembly given the unique
201 /// dependence tag number (FP or int).
202 void printReg(std::ostream &os, int reg) const;
205 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
211 AlphaStaticInst::printReg(std::ostream &os, int reg) const
213 if (reg < FP_Base_DepTag) {
214 ccprintf(os, "r%d", reg);
217 ccprintf(os, "f%d", reg - FP_Base_DepTag);
222 AlphaStaticInst::generateDisassembly(Addr pc,
223 const SymbolTable *symtab) const
225 std::stringstream ss;
227 ccprintf(ss, "%-10s ", mnemonic);
229 // just print the first two source regs... if there's
230 // a third one, it's a read-modify-write dest (Rc),
232 if (_numSrcRegs > 0) {
233 printReg(ss, _srcRegIdx[0]);
235 if (_numSrcRegs > 1) {
237 printReg(ss, _srcRegIdx[1]);
240 // just print the first dest... if there's a second one,
241 // it's generally implicit
242 if (_numDestRegs > 0) {
245 printReg(ss, _destRegIdx[0]);
252 // Declarations for execute() methods.
253 def template BasicExecDeclare {{
254 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
257 // Basic instruction class declaration template.
258 def template BasicDeclare {{
260 * Static instruction class for "%(mnemonic)s".
262 class %(class_name)s : public %(base_class)s
266 %(class_name)s(MachInst machInst);
272 // Basic instruction class constructor template.
273 def template BasicConstructor {{
274 inline %(class_name)s::%(class_name)s(MachInst machInst)
275 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
281 // Basic instruction class execute method template.
282 def template BasicExecute {{
283 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
284 Trace::InstRecord *traceData) const
286 Fault fault = No_Fault;
293 if (fault == No_Fault) {
301 // Basic decode template.
302 def template BasicDecode {{
303 return new %(class_name)s(machInst);
306 // Basic decode template, passing mnemonic in as string arg to constructor.
307 def template BasicDecodeWithMnemonic {{
308 return new %(class_name)s("%(mnemonic)s", machInst);
311 // The most basic instruction format... used only for a few misc. insts
312 def format BasicOperate(code, *flags) {{
313 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
314 header_output = BasicDeclare.subst(iop)
315 decoder_output = BasicConstructor.subst(iop)
316 decode_block = BasicDecode.subst(iop)
317 exec_output = BasicExecute.subst(iop)
322 ////////////////////////////////////////////////////////////////////
329 * Static instruction class for no-ops. This is a leaf class.
331 class Nop : public AlphaStaticInst
333 /// Disassembly of original instruction.
334 const std::string originalDisassembly;
338 Nop(const std::string _originalDisassembly, MachInst _machInst)
339 : AlphaStaticInst("nop", _machInst, No_OpClass),
340 originalDisassembly(_originalDisassembly)
348 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
355 std::string Nop::generateDisassembly(Addr pc,
356 const SymbolTable *symtab) const
358 #ifdef SS_COMPATIBLE_DISASSEMBLY
359 return originalDisassembly;
361 return csprintf("%-10s (%s)", "nop", originalDisassembly);
365 /// Helper function for decoding nops. Substitute Nop object
366 /// for original inst passed in as arg (and delete latter).
369 makeNop(AlphaStaticInst *inst)
371 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
379 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
385 // integer & FP operate instructions use Rc as dest, so check for
386 // Rc == 31 to detect nops
387 def template OperateNopCheckDecode {{
389 AlphaStaticInst *i = new %(class_name)s(machInst);
397 // Like BasicOperate format, but generates NOP if RC/FC == 31
398 def format BasicOperateWithNopCheck(code, *opt_args) {{
399 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
401 header_output = BasicDeclare.subst(iop)
402 decoder_output = BasicConstructor.subst(iop)
403 decode_block = OperateNopCheckDecode.subst(iop)
404 exec_output = BasicExecute.subst(iop)
407 // Integer instruction templates, formats, etc.
408 ##include "m5/arch/alpha/isa/int.isa"
410 // Floating-point instruction templates, formats, etc.
411 ##include "m5/arch/alpha/isa/fp.isa"
413 // Memory instruction templates, formats, etc.
414 ##include "m5/arch/alpha/isa/mem.isa"
416 // Branch/jump instruction templates, formats, etc.
417 ##include "m5/arch/alpha/isa/branch.isa"
419 // PAL instruction templates, formats, etc.
420 ##include "m5/arch/alpha/isa/pal.isa"
422 // Unimplemented instruction templates, formats, etc.
423 ##include "m5/arch/alpha/isa/unimp.isa"
425 // Unknown instruction templates, formats, etc.
426 ##include "m5/arch/alpha/isa/unknown.isa"
428 // Execution utility functions
429 ##include "m5/arch/alpha/isa/util.isa"
431 // The actual decoder
432 ##include "m5/arch/alpha/isa/decoder.isa"