arch/alpha/isa/main.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 output header {{
  30 #include <sstream>
  31 #include <iostream>
  32 #include <iomanip>
  33
  34 #include "config/ss_compatible_fp.hh"
  35 #include "cpu/static_inst.hh"
  36 #include "arch/alpha/faults.hh"
  37 #include "mem/mem_req.hh"  // some constructors use MemReq flags
  38 }};
  39
  40 output decoder {{
  41 #include "base/cprintf.hh"
  42 #include "base/fenv.hh"
  43 #include "base/loader/symtab.hh"
  44 #include "config/ss_compatible_fp.hh"
  45 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
  46
  47 #include <math.h>
  48 }};
  49
  50 output exec {{
  51 #include <math.h>
  52
  53 #if FULL_SYSTEM
  54 #include "sim/pseudo_inst.hh"
  55 #endif
  56 #include "base/fenv.hh"
  57 #include "config/ss_compatible_fp.hh"
  58 #include "cpu/base.hh"
  59 #include "cpu/exetrace.hh"
  60 #include "sim/sim_exit.hh"
  61 }};
  62
  63 ////////////////////////////////////////////////////////////////////
  64 //
  65 // Namespace statement.  Everything below this line will be in the
  66 // AlphaISAInst namespace.
  67 //
  68
  69
  70 namespace AlphaISA;
  71
  72 ////////////////////////////////////////////////////////////////////
  73 //
  74 // Bitfield definitions.
  75 //
  76
  77 // Universal (format-independent) fields
  78 def bitfield OPCODE     <31:26>;
  79 def bitfield RA         <25:21>;
  80 def bitfield RB         <20:16>;
  81
  82 // Memory format
  83 def signed bitfield MEMDISP <15: 0>; // displacement
  84 def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
  85
  86 // Memory-format jumps
  87 def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
  88 def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
  89
  90 // Branch format
  91 def signed bitfield BRDISP <20: 0>; // displacement
  92
  93 // Integer operate format(s>;
  94 def bitfield INTIMM     <20:13>; // integer immediate (literal)
  95 def bitfield IMM        <12:12>; // immediate flag
  96 def bitfield INTFUNC    <11: 5>; // function code
  97 def bitfield RC         < 4: 0>; // dest reg
  98
  99 // Floating-point operate format
 100 def bitfield FA           <25:21>;
 101 def bitfield FB           <20:16>;
 102 def bitfield FP_FULLFUNC  <15: 5>; // complete function code
 103     def bitfield FP_TRAPMODE  <15:13>; // trapping mode
 104     def bitfield FP_ROUNDMODE <12:11>; // rounding mode
 105     def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
 106         def bitfield FP_SRCTYPE   <10: 9>; // source reg type
 107         def bitfield FP_SHORTFUNC < 8: 5>; // short function code
 108         def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
 109 def bitfield FC           < 4: 0>; // dest reg
 110
 111 // PALcode format
 112 def bitfield PALFUNC    <25: 0>; // function code
 113
 114 // EV5 PAL instructions:
 115 // HW_LD/HW_ST
 116 def bitfield HW_LDST_PHYS  <15>; // address is physical
 117 def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
 118 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
 119 def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
 120 def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
 121 def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
 122 def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
 123 def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
 124
 125 // HW_REI
 126 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
 127 def bitfield HW_REI_MBZ <13: 0>; // must be zero
 128
 129 // HW_MTPR/MW_MFPR
 130 def bitfield HW_IPR_IDX <15:0>;  // IPR index
 131
 132 // M5 instructions
 133 def bitfield M5FUNC <7:0>;
 134
 135 def operand_types {{
 136     'sb' : ('signed int', 8),
 137     'ub' : ('unsigned int', 8),
 138     'sw' : ('signed int', 16),
 139     'uw' : ('unsigned int', 16),
 140     'sl' : ('signed int', 32),
 141     'ul' : ('unsigned int', 32),
 142     'sq' : ('signed int', 64),
 143     'uq' : ('unsigned int', 64),
 144     'sf' : ('float', 32),
 145     'df' : ('float', 64)
 146 }};
 147
 148 def operands {{
 149     # Int regs default to unsigned, but code should not count on this.
 150     # For clarity, descriptions that depend on unsigned behavior should
 151     # explicitly specify '.uq'.
 152     'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
 153     'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
 154     'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
 155     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
 156     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
 157     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
 158     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 159     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
 160     'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
 161     'FPCR':  (' ControlReg', 'uq', 'Fpcr', None, 1),
 162     # The next two are hacks for non-full-system call-pal emulation
 163     'R0':  ('IntReg', 'uq', '0', None, 1),
 164     'R16': ('IntReg', 'uq', '16', None, 1),
 165     'R17': ('IntReg', 'uq', '17', None, 1),
 166     'R18': ('IntReg', 'uq', '18', None, 1)
 167 }};
 168
 169 ////////////////////////////////////////////////////////////////////
 170 //
 171 // Basic instruction classes/templates/formats etc.
 172 //
 173
 174 output header {{
 175 // uncomment the following to get SimpleScalar-compatible disassembly
 176 // (useful for diffing output traces).
 177 // #define SS_COMPATIBLE_DISASSEMBLY
 178
 179     /**
 180      * Base class for all Alpha static instructions.
 181      */
 182     class AlphaStaticInst : public StaticInst<AlphaISA>
 183     {
 184       protected:
 185
 186         /// Make AlphaISA register dependence tags directly visible in
 187         /// this class and derived classes.  Maybe these should really
 188         /// live here and not in the AlphaISA namespace.
 189         enum DependenceTags {
 190             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
 191             Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
 192             Uniq_DepTag = AlphaISA::Uniq_DepTag,
 193             IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
 194         };
 195
 196         /// Constructor.
 197         AlphaStaticInst(const char *mnem, MachInst _machInst,
 198                         OpClass __opClass)
 199             : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
 200         {
 201         }
 202
 203         /// Print a register name for disassembly given the unique
 204         /// dependence tag number (FP or int).
 205         void printReg(std::ostream &os, int reg) const;
 206
 207         std::string
 208         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 209     };
 210 }};
 211
 212 output decoder {{
 213     void
 214     AlphaStaticInst::printReg(std::ostream &os, int reg) const
 215     {
 216         if (reg < FP_Base_DepTag) {
 217             ccprintf(os, "r%d", reg);
 218         }
 219         else {
 220             ccprintf(os, "f%d", reg - FP_Base_DepTag);
 221         }
 222     }
 223
 224     std::string
 225     AlphaStaticInst::generateDisassembly(Addr pc,
 226                                          const SymbolTable *symtab) const
 227     {
 228         std::stringstream ss;
 229
 230         ccprintf(ss, "%-10s ", mnemonic);
 231
 232         // just print the first two source regs... if there's
 233         // a third one, it's a read-modify-write dest (Rc),
 234         // e.g. for CMOVxx
 235         if (_numSrcRegs > 0) {
 236             printReg(ss, _srcRegIdx[0]);
 237         }
 238         if (_numSrcRegs > 1) {
 239             ss << ",";
 240             printReg(ss, _srcRegIdx[1]);
 241         }
 242
 243         // just print the first dest... if there's a second one,
 244         // it's generally implicit
 245         if (_numDestRegs > 0) {
 246             if (_numSrcRegs > 0)
 247                 ss << ",";
 248             printReg(ss, _destRegIdx[0]);
 249         }
 250
 251         return ss.str();
 252     }
 253 }};
 254
 255 // Declarations for execute() methods.
 256 def template BasicExecDeclare {{
 257     Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 258 }};
 259
 260 // Basic instruction class declaration template.
 261 def template BasicDeclare {{
 262     /**
 263      * Static instruction class for "%(mnemonic)s".
 264      */
 265     class %(class_name)s : public %(base_class)s
 266     {
 267       public:
 268         /// Constructor.
 269         %(class_name)s(MachInst machInst);
 270
 271         %(BasicExecDeclare)s
 272     };
 273 }};
 274
 275 // Basic instruction class constructor template.
 276 def template BasicConstructor {{
 277     inline %(class_name)s::%(class_name)s(MachInst machInst)
 278          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 279     {
 280         %(constructor)s;
 281     }
 282 }};
 283
 284 // Basic instruction class execute method template.
 285 def template BasicExecute {{
 286     Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
 287                                   Trace::InstRecord *traceData) const
 288     {
 289         Fault * fault = NoFault;
 290
 291         %(fp_enable_check)s;
 292         %(op_decl)s;
 293         %(op_rd)s;
 294         %(code)s;
 295
 296         if (fault == NoFault) {
 297             %(op_wb)s;
 298         }
 299
 300         return fault;
 301     }
 302 }};
 303
 304 // Basic decode template.
 305 def template BasicDecode {{
 306     return new %(class_name)s(machInst);
 307 }};
 308
 309 // Basic decode template, passing mnemonic in as string arg to constructor.
 310 def template BasicDecodeWithMnemonic {{
 311     return new %(class_name)s("%(mnemonic)s", machInst);
 312 }};
 313
 314 // The most basic instruction format... used only for a few misc. insts
 315 def format BasicOperate(code, *flags) {{
 316     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
 317     header_output = BasicDeclare.subst(iop)
 318     decoder_output = BasicConstructor.subst(iop)
 319     decode_block = BasicDecode.subst(iop)
 320     exec_output = BasicExecute.subst(iop)
 321 }};
 322
 323
 324
 325 ////////////////////////////////////////////////////////////////////
 326 //
 327 // Nop
 328 //
 329
 330 output header {{
 331     /**
 332      * Static instruction class for no-ops.  This is a leaf class.
 333      */
 334     class Nop : public AlphaStaticInst
 335     {
 336         /// Disassembly of original instruction.
 337         const std::string originalDisassembly;
 338
 339       public:
 340         /// Constructor
 341         Nop(const std::string _originalDisassembly, MachInst _machInst)
 342             : AlphaStaticInst("nop", _machInst, No_OpClass),
 343               originalDisassembly(_originalDisassembly)
 344         {
 345             flags[IsNop] = true;
 346         }
 347
 348         ~Nop() { }
 349
 350         std::string
 351         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 352
 353         %(BasicExecDeclare)s
 354     };
 355 }};
 356
 357 output decoder {{
 358     std::string Nop::generateDisassembly(Addr pc,
 359                                          const SymbolTable *symtab) const
 360     {
 361 #ifdef SS_COMPATIBLE_DISASSEMBLY
 362         return originalDisassembly;
 363 #else
 364         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 365 #endif
 366     }
 367
 368     /// Helper function for decoding nops.  Substitute Nop object
 369     /// for original inst passed in as arg (and delete latter).
 370     inline
 371     AlphaStaticInst *
 372     makeNop(AlphaStaticInst *inst)
 373     {
 374         AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
 375         delete inst;
 376         return nop;
 377     }
 378 }};
 379
 380 output exec {{
 381     Fault *
 382     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
 383     {
 384         return NoFault;
 385     }
 386 }};
 387
 388 // integer & FP operate instructions use Rc as dest, so check for
 389 // Rc == 31 to detect nops
 390 def template OperateNopCheckDecode {{
 391  {
 392      AlphaStaticInst *i = new %(class_name)s(machInst);
 393      if (RC == 31) {
 394          i = makeNop(i);
 395      }
 396      return i;
 397  }
 398 }};
 399
 400 // Like BasicOperate format, but generates NOP if RC/FC == 31
 401 def format BasicOperateWithNopCheck(code, *opt_args) {{
 402     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
 403                         opt_args)
 404     header_output = BasicDeclare.subst(iop)
 405     decoder_output = BasicConstructor.subst(iop)
 406     decode_block = OperateNopCheckDecode.subst(iop)
 407     exec_output = BasicExecute.subst(iop)
 408 }};
 409
 410 // Integer instruction templates, formats, etc.
 411 ##include "m5/arch/alpha/isa/int.isa"
 412
 413 // Floating-point instruction templates, formats, etc.
 414 ##include "m5/arch/alpha/isa/fp.isa"
 415
 416 // Memory instruction templates, formats, etc.
 417 ##include "m5/arch/alpha/isa/mem.isa"
 418
 419 // Branch/jump instruction templates, formats, etc.
 420 ##include "m5/arch/alpha/isa/branch.isa"
 421
 422 // PAL instruction templates, formats, etc.
 423 ##include "m5/arch/alpha/isa/pal.isa"
 424
 425 // Unimplemented instruction templates, formats, etc.
 426 ##include "m5/arch/alpha/isa/unimp.isa"
 427
 428 // Unknown instruction templates, formats, etc.
 429 ##include "m5/arch/alpha/isa/unknown.isa"
 430
 431 // Execution utility functions
 432 ##include "m5/arch/alpha/isa/util.isa"
 433
 434 // The actual decoder
 435 ##include "m5/arch/alpha/isa/decoder.isa"