arch/alpha/isa/mem.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 output header {{
  30     /**
  31      * Base class for general Alpha memory-format instructions.
  32      */
  33     class Memory : public AlphaStaticInst
  34     {
  35       protected:
  36
  37         /// Memory request flags.  See mem_req_base.hh.
  38         unsigned memAccessFlags;
  39         /// Pointer to EAComp object.
  40         const StaticInstPtr eaCompPtr;
  41         /// Pointer to MemAcc object.
  42         const StaticInstPtr memAccPtr;
  43
  44         /// Constructor
  45         Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  46                StaticInstPtr _eaCompPtr = nullStaticInstPtr,
  47                StaticInstPtr _memAccPtr = nullStaticInstPtr)
  48             : AlphaStaticInst(mnem, _machInst, __opClass),
  49               memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
  50         {
  51         }
  52
  53         std::string
  54         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  55
  56       public:
  57
  58         const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
  59         const StaticInstPtr &memAccInst() const { return memAccPtr; }
  60     };
  61
  62     /**
  63      * Base class for memory-format instructions using a 32-bit
  64      * displacement (i.e. most of them).
  65      */
  66     class MemoryDisp32 : public Memory
  67     {
  68       protected:
  69         /// Displacement for EA calculation (signed).
  70         int32_t disp;
  71
  72         /// Constructor.
  73         MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  74                      StaticInstPtr _eaCompPtr = nullStaticInstPtr,
  75                      StaticInstPtr _memAccPtr = nullStaticInstPtr)
  76             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
  77               disp(MEMDISP)
  78         {
  79         }
  80     };
  81
  82
  83     /**
  84      * Base class for a few miscellaneous memory-format insts
  85      * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
  86      * None of these instructions has a destination register either.
  87      */
  88     class MemoryNoDisp : public Memory
  89     {
  90       protected:
  91         /// Constructor
  92         MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  93                      StaticInstPtr _eaCompPtr = nullStaticInstPtr,
  94                      StaticInstPtr _memAccPtr = nullStaticInstPtr)
  95             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
  96         {
  97         }
  98
  99         std::string
 100         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 101     };
 102 }};
 103
 104
 105 output decoder {{
 106     std::string
 107     Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 108     {
 109         return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
 110                         flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
 111     }
 112
 113     std::string
 114     MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 115     {
 116         return csprintf("%-10s (r%d)", mnemonic, RB);
 117     }
 118 }};
 119
 120 def format LoadAddress(code) {{
 121     iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
 122     header_output = BasicDeclare.subst(iop)
 123     decoder_output = BasicConstructor.subst(iop)
 124     decode_block = BasicDecode.subst(iop)
 125     exec_output = BasicExecute.subst(iop)
 126 }};
 127
 128
 129 def template LoadStoreDeclare {{
 130     /**
 131      * Static instruction class for "%(mnemonic)s".
 132      */
 133     class %(class_name)s : public %(base_class)s
 134     {
 135       protected:
 136
 137         /**
 138          * "Fake" effective address computation class for "%(mnemonic)s".
 139          */
 140         class EAComp : public %(base_class)s
 141         {
 142           public:
 143             /// Constructor
 144             EAComp(ExtMachInst machInst);
 145
 146             %(BasicExecDeclare)s
 147         };
 148
 149         /**
 150          * "Fake" memory access instruction class for "%(mnemonic)s".
 151          */
 152         class MemAcc : public %(base_class)s
 153         {
 154           public:
 155             /// Constructor
 156             MemAcc(ExtMachInst machInst);
 157
 158             %(BasicExecDeclare)s
 159         };
 160
 161       public:
 162
 163         /// Constructor.
 164         %(class_name)s(ExtMachInst machInst);
 165
 166         %(BasicExecDeclare)s
 167
 168         %(InitiateAccDeclare)s
 169
 170         %(CompleteAccDeclare)s
 171     };
 172 }};
 173
 174
 175 def template InitiateAccDeclare {{
 176     Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 177 }};
 178
 179
 180 def template CompleteAccDeclare {{
 181     Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
 182 }};
 183
 184
 185 def template LoadStoreConstructor {{
 186     /** TODO: change op_class to AddrGenOp or something (requires
 187      * creating new member of OpClass enum in op_class.hh, updating
 188      * config files, etc.). */
 189     inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
 190         : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
 191     {
 192         %(ea_constructor)s;
 193     }
 194
 195     inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
 196         : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
 197     {
 198         %(memacc_constructor)s;
 199     }
 200
 201     inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
 202          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 203                           new EAComp(machInst), new MemAcc(machInst))
 204     {
 205         %(constructor)s;
 206     }
 207 }};
 208
 209
 210 def template EACompExecute {{
 211     Fault
 212     %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
 213                                    Trace::InstRecord *traceData) const
 214     {
 215         Addr EA;
 216         Fault fault = NoFault;
 217
 218         %(fp_enable_check)s;
 219         %(op_decl)s;
 220         %(op_rd)s;
 221         %(code)s;
 222
 223         if (fault == NoFault) {
 224             %(op_wb)s;
 225             xc->setEA(EA);
 226         }
 227
 228         return fault;
 229     }
 230 }};
 231
 232 def template LoadMemAccExecute {{
 233     Fault
 234     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
 235                                    Trace::InstRecord *traceData) const
 236     {
 237         Addr EA;
 238         Fault fault = NoFault;
 239
 240         %(fp_enable_check)s;
 241         %(op_decl)s;
 242         %(op_rd)s;
 243         EA = xc->getEA();
 244
 245         if (fault == NoFault) {
 246             fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
 247             %(code)s;
 248         }
 249
 250         if (fault == NoFault) {
 251             %(op_wb)s;
 252         }
 253
 254         return fault;
 255     }
 256 }};
 257
 258
 259 def template LoadExecute {{
 260     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 261                                   Trace::InstRecord *traceData) const
 262     {
 263         Addr EA;
 264         Fault fault = NoFault;
 265
 266         %(fp_enable_check)s;
 267         %(op_decl)s;
 268         %(op_rd)s;
 269         %(ea_code)s;
 270
 271         if (fault == NoFault) {
 272             fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
 273             %(memacc_code)s;
 274         }
 275
 276         if (fault == NoFault) {
 277             %(op_wb)s;
 278         }
 279
 280         return fault;
 281     }
 282 }};
 283
 284
 285 def template LoadInitiateAcc {{
 286     Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 287                                       Trace::InstRecord *traceData) const
 288     {
 289         Addr EA;
 290         Fault fault = NoFault;
 291
 292         %(fp_enable_check)s;
 293         %(op_src_decl)s;
 294         %(op_rd)s;
 295         %(ea_code)s;
 296
 297         if (fault == NoFault) {
 298             fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
 299         }
 300
 301         return fault;
 302     }
 303 }};
 304
 305
 306 def template LoadCompleteAcc {{
 307     Fault %(class_name)s::completeAcc(uint8_t *data,
 308                                       %(CPU_exec_context)s *xc,
 309                                       Trace::InstRecord *traceData) const
 310     {
 311         Fault fault = NoFault;
 312
 313         %(fp_enable_check)s;
 314         %(op_src_decl)s;
 315         %(op_dest_decl)s;
 316
 317         memcpy(&Mem, data, sizeof(Mem));
 318
 319         if (fault == NoFault) {
 320             %(memacc_code)s;
 321         }
 322
 323         if (fault == NoFault) {
 324             %(op_wb)s;
 325         }
 326
 327         return fault;
 328     }
 329 }};
 330
 331
 332 def template StoreMemAccExecute {{
 333     Fault
 334     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
 335                                    Trace::InstRecord *traceData) const
 336     {
 337         Addr EA;
 338         Fault fault = NoFault;
 339         uint64_t write_result = 0;
 340
 341         %(fp_enable_check)s;
 342         %(op_decl)s;
 343         %(op_rd)s;
 344         EA = xc->getEA();
 345
 346         if (fault == NoFault) {
 347             %(code)s;
 348         }
 349
 350         if (fault == NoFault) {
 351             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
 352                               memAccessFlags, &write_result);
 353             if (traceData) { traceData->setData(Mem); }
 354         }
 355
 356         if (fault == NoFault) {
 357             %(postacc_code)s;
 358         }
 359
 360         if (fault == NoFault) {
 361             %(op_wb)s;
 362         }
 363
 364         return fault;
 365     }
 366 }};
 367
 368
 369 def template StoreExecute {{
 370     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 371                                   Trace::InstRecord *traceData) const
 372     {
 373         Addr EA;
 374         Fault fault = NoFault;
 375         uint64_t write_result = 0;
 376
 377         %(fp_enable_check)s;
 378         %(op_decl)s;
 379         %(op_rd)s;
 380         %(ea_code)s;
 381
 382         if (fault == NoFault) {
 383             %(memacc_code)s;
 384         }
 385
 386         if (fault == NoFault) {
 387             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
 388                               memAccessFlags, &write_result);
 389             if (traceData) { traceData->setData(Mem); }
 390         }
 391
 392         if (fault == NoFault) {
 393             %(postacc_code)s;
 394         }
 395
 396         if (fault == NoFault) {
 397             %(op_wb)s;
 398         }
 399
 400         return fault;
 401     }
 402 }};
 403
 404 def template StoreInitiateAcc {{
 405     Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 406                                       Trace::InstRecord *traceData) const
 407     {
 408         Addr EA;
 409         Fault fault = NoFault;
 410         uint64_t write_result = 0;
 411
 412         %(fp_enable_check)s;
 413         %(op_src_decl)s;
 414         %(op_dest_decl)s;
 415         %(op_rd)s;
 416         %(ea_code)s;
 417
 418         if (fault == NoFault) {
 419             %(memacc_code)s;
 420         }
 421
 422         if (fault == NoFault) {
 423             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
 424                               memAccessFlags, &write_result);
 425             if (traceData) { traceData->setData(Mem); }
 426         }
 427
 428         return fault;
 429     }
 430 }};
 431
 432
 433 def template StoreCompleteAcc {{
 434     Fault %(class_name)s::completeAcc(uint8_t *data,
 435                                       %(CPU_exec_context)s *xc,
 436                                       Trace::InstRecord *traceData) const
 437     {
 438         Fault fault = NoFault;
 439         uint64_t write_result = 0;
 440
 441         %(fp_enable_check)s;
 442         %(op_dest_decl)s;
 443
 444         memcpy(&write_result, data, sizeof(write_result));
 445
 446         if (fault == NoFault) {
 447             %(postacc_code)s;
 448         }
 449
 450         if (fault == NoFault) {
 451             %(op_wb)s;
 452         }
 453
 454         return fault;
 455     }
 456 }};
 457
 458
 459 def template MiscMemAccExecute {{
 460     Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
 461                                           Trace::InstRecord *traceData) const
 462     {
 463         Addr EA;
 464         Fault fault = NoFault;
 465
 466         %(fp_enable_check)s;
 467         %(op_decl)s;
 468         %(op_rd)s;
 469         EA = xc->getEA();
 470
 471         if (fault == NoFault) {
 472             %(code)s;
 473         }
 474
 475         return NoFault;
 476     }
 477 }};
 478
 479 def template MiscExecute {{
 480     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 481                                   Trace::InstRecord *traceData) const
 482     {
 483         Addr EA;
 484         Fault fault = NoFault;
 485
 486         %(fp_enable_check)s;
 487         %(op_decl)s;
 488         %(op_rd)s;
 489         %(ea_code)s;
 490
 491         if (fault == NoFault) {
 492             %(memacc_code)s;
 493         }
 494
 495         return NoFault;
 496     }
 497 }};
 498
 499 def template MiscInitiateAcc {{
 500     Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
 501                                       Trace::InstRecord *traceData) const
 502     {
 503         panic("Misc instruction does not support split access method!");
 504         return NoFault;
 505     }
 506 }};
 507
 508
 509 def template MiscCompleteAcc {{
 510     Fault %(class_name)s::completeAcc(uint8_t *data,
 511                                       %(CPU_exec_context)s *xc,
 512                                       Trace::InstRecord *traceData) const
 513     {
 514         panic("Misc instruction does not support split access method!");
 515
 516         return NoFault;
 517     }
 518 }};
 519
 520 // load instructions use Ra as dest, so check for
 521 // Ra == 31 to detect nops
 522 def template LoadNopCheckDecode {{
 523  {
 524      AlphaStaticInst *i = new %(class_name)s(machInst);
 525      if (RA == 31) {
 526          i = makeNop(i);
 527      }
 528      return i;
 529  }
 530 }};
 531
 532
 533 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
 534 def template LoadPrefetchCheckDecode {{
 535  {
 536      if (RA != 31) {
 537          return new %(class_name)s(machInst);
 538      }
 539      else {
 540          return new %(class_name)sPrefetch(machInst);
 541      }
 542  }
 543 }};
 544
 545
 546 let {{
 547 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 548                   postacc_code = '', base_class = 'MemoryDisp32',
 549                   decode_template = BasicDecode, exec_template_base = ''):
 550     # Make sure flags are in lists (convert to lists if not).
 551     mem_flags = makeList(mem_flags)
 552     inst_flags = makeList(inst_flags)
 553
 554     # add hook to get effective addresses into execution trace output.
 555     ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
 556
 557     # generate code block objects
 558     ea_cblk = CodeBlock(ea_code)
 559     memacc_cblk = CodeBlock(memacc_code)
 560     postacc_cblk = CodeBlock(postacc_code)
 561
 562     # Some CPU models execute the memory operation as an atomic unit,
 563     # while others want to separate them into an effective address
 564     # computation and a memory access operation.  As a result, we need
 565     # to generate three StaticInst objects.  Note that the latter two
 566     # are nested inside the larger "atomic" one.
 567
 568     # generate InstObjParams for EAComp object
 569     ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
 570
 571     # generate InstObjParams for MemAcc object
 572     memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
 573     # in the split execution model, the MemAcc portion is responsible
 574     # for the post-access code.
 575     memacc_iop.postacc_code = postacc_cblk.code
 576
 577     # generate InstObjParams for InitiateAcc, CompleteAcc object
 578     # The code used depends on the template being used
 579     if (exec_template_base == 'Load'):
 580         initiateacc_cblk = CodeBlock(ea_code + memacc_code)
 581         completeacc_cblk = CodeBlock(memacc_code + postacc_code)
 582     elif (exec_template_base == 'Store'):
 583         initiateacc_cblk = CodeBlock(ea_code + memacc_code)
 584         completeacc_cblk = CodeBlock(postacc_code)
 585     else:
 586         initiateacc_cblk = ''
 587         completeacc_cblk = ''
 588
 589     initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
 590                                     inst_flags)
 591
 592     completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
 593                                     inst_flags)
 594
 595     if (exec_template_base == 'Load'):
 596         initiateacc_iop.ea_code = ea_cblk.code
 597         initiateacc_iop.memacc_code = memacc_cblk.code
 598         completeacc_iop.memacc_code = memacc_cblk.code
 599         completeacc_iop.postacc_code = postacc_cblk.code
 600     elif (exec_template_base == 'Store'):
 601         initiateacc_iop.ea_code = ea_cblk.code
 602         initiateacc_iop.memacc_code = memacc_cblk.code
 603         completeacc_iop.postacc_code = postacc_cblk.code
 604
 605     # generate InstObjParams for unified execution
 606     cblk = CodeBlock(ea_code + memacc_code + postacc_code)
 607     iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
 608
 609     iop.ea_constructor = ea_cblk.constructor
 610     iop.ea_code = ea_cblk.code
 611     iop.memacc_constructor = memacc_cblk.constructor
 612     iop.memacc_code = memacc_cblk.code
 613     iop.postacc_code = postacc_cblk.code
 614
 615     if mem_flags:
 616         s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
 617         iop.constructor += s
 618         memacc_iop.constructor += s
 619
 620     # select templates
 621     memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
 622     fullExecTemplate = eval(exec_template_base + 'Execute')
 623     initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
 624     completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
 625
 626     # (header_output, decoder_output, decode_block, exec_output)
 627     return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
 628             decode_template.subst(iop),
 629             EACompExecute.subst(ea_iop)
 630             + memAccExecTemplate.subst(memacc_iop)
 631             + fullExecTemplate.subst(iop)
 632             + initiateAccTemplate.subst(initiateacc_iop)
 633             + completeAccTemplate.subst(completeacc_iop))
 634 }};
 635
 636
 637 def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
 638                      mem_flags = [], inst_flags = []) {{
 639     (header_output, decoder_output, decode_block, exec_output) = \
 640         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 641                       decode_template = LoadNopCheckDecode,
 642                       exec_template_base = 'Load')
 643 }};
 644
 645
 646 // Note that the flags passed in apply only to the prefetch version
 647 def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
 648                           mem_flags = [], pf_flags = [], inst_flags = []) {{
 649     # declare the load instruction object and generate the decode block
 650     (header_output, decoder_output, decode_block, exec_output) = \
 651         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 652                       decode_template = LoadPrefetchCheckDecode,
 653                       exec_template_base = 'Load')
 654
 655     # Declare the prefetch instruction object.
 656
 657     # Make sure flag args are lists so we can mess with them.
 658     mem_flags = makeList(mem_flags)
 659     pf_flags = makeList(pf_flags)
 660     inst_flags = makeList(inst_flags)
 661
 662     pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
 663     pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
 664                                   'IsDataPrefetch', 'MemReadOp']
 665
 666     (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
 667         LoadStoreBase(name, Name + 'Prefetch', ea_code,
 668                       'xc->prefetch(EA, memAccessFlags);',
 669                       pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
 670
 671     header_output += pf_header_output
 672     decoder_output += pf_decoder_output
 673     exec_output += pf_exec_output
 674 }};
 675
 676
 677 def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
 678                  mem_flags = [], inst_flags = []) {{
 679     (header_output, decoder_output, decode_block, exec_output) = \
 680         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 681                       exec_template_base = 'Store')
 682 }};
 683
 684
 685 def format StoreCond(memacc_code, postacc_code,
 686                      ea_code = {{ EA = Rb + disp; }},
 687                      mem_flags = [], inst_flags = []) {{
 688     (header_output, decoder_output, decode_block, exec_output) = \
 689         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 690                       postacc_code, exec_template_base = 'Store')
 691 }};
 692
 693
 694 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
 695 def format MiscPrefetch(ea_code, memacc_code,
 696                         mem_flags = [], inst_flags = []) {{
 697     (header_output, decoder_output, decode_block, exec_output) = \
 698         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 699                       base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
 700 }};
 701
 702