3 // Alpha ISA description file.
21 #include "base/cprintf.hh"
22 #include "base/misc.hh"
23 #include "cpu/exec_context.hh"
24 #include "cpu/exetrace.hh"
25 #include "cpu/full_cpu/full_cpu.hh"
26 #include "cpu/full_cpu/op_class.hh"
27 #include "cpu/full_cpu/spec_state.hh"
28 #include "cpu/simple_cpu/simple_cpu.hh"
29 #include "cpu/static_inst.hh"
30 #include "sim/annotation.hh"
31 #include "sim/sim_exit.hh"
34 #include "arch/alpha/ev5.hh"
35 #include "arch/alpha/pseudo_inst.hh"
40 // Universal (format-independent) fields
41 def bitfield OPCODE <31:26>;
42 def bitfield RA <25:21>;
43 def bitfield RB <20:16>;
46 def signed bitfield MEMDISP <15: 0>; // displacement
47 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
49 // Memory-format jumps
50 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
51 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
54 def signed bitfield BRDISP <20: 0>; // displacement
56 // Integer operate format(s>;
57 def bitfield INTIMM <20:13>; // integer immediate (literal)
58 def bitfield IMM <12:12>; // immediate flag
59 def bitfield INTFUNC <11: 5>; // function code
60 def bitfield RC < 4: 0>; // dest reg
62 // Floating-point operate format
63 def bitfield FA <25:21>;
64 def bitfield FB <20:16>;
65 def bitfield FP_FULLFUNC <15: 5>; // complete function code
66 def bitfield FP_TRAPMODE <15:13>; // trapping mode
67 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
68 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
69 def bitfield FP_SRCTYPE <10: 9>; // source reg type
70 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
71 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
72 def bitfield FC < 4: 0>; // dest reg
75 def bitfield PALFUNC <25: 0>; // function code
77 // EV5 PAL instructions:
79 def bitfield HW_LDST_PHYS <15>; // address is physical
80 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
81 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
82 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
83 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
84 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
85 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
86 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
89 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
90 def bitfield HW_REI_MBZ <13: 0>; // must be zero
93 def bitfield HW_IPR_IDX <15:0>; // IPR index
96 def bitfield M5FUNC <7:0>;
101 'sb' : ('signed int', 8),
102 'ub' : ('unsigned int', 8),
103 'sw' : ('signed int', 16),
104 'uw' : ('unsigned int', 16),
105 'sl' : ('signed int', 32),
106 'ul' : ('unsigned int', 32),
107 'sq' : ('signed int', 64),
108 'uq' : ('unsigned int', 64),
109 'sf' : ('float', 32),
113 global operandTraitsMap
115 # Int regs default to unsigned, but code should not count on this.
116 # For clarity, descriptions that depend on unsigned behavior should
117 # explicitly specify '.uq'.
118 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
119 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
120 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
121 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
122 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
123 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
124 'Mem': MemOperandTraits('uq', None,
125 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
126 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
127 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
128 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
129 # The next two are hacks for non-full-system call-pal emulation
130 'R0': IntRegOperandTraits('uq', '0', None, 1),
131 'R16': IntRegOperandTraits('uq', '16', None, 1),
134 defineDerivedOperandVars()
138 // just temporary, while comparing with old code for debugging
139 // #define SS_COMPATIBLE_DISASSEMBLY
141 /// Check "FP enabled" machine status bit. Called when executing any FP
142 /// instruction in full-system mode.
143 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
144 /// if not. Non-full-system mode: always returns No_Fault.
146 inline Fault checkFpEnableFault(ExecContext *xc)
148 Fault fault = No_Fault; // dummy... this ipr access should not fault
149 if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
155 inline Fault checkFpEnableFault(ExecContext *xc)
162 * Base class for all Alpha static instructions.
164 class AlphaStaticInst : public StaticInst<AlphaISA>
168 /// Make AlphaISA register dependence tags directly visible in
169 /// this class and derived classes. Maybe these should really
170 /// live here and not in the AlphaISA namespace.
171 enum DependenceTags {
172 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
173 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
174 Uniq_DepTag = AlphaISA::Uniq_DepTag,
175 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
179 AlphaStaticInst(const char *mnem, MachInst _machInst,
181 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
185 /// Print a register name for disassembly given the unique
186 /// dependence tag number (FP or int).
187 void printReg(std::ostream &os, int reg)
189 if (reg < FP_Base_DepTag) {
190 ccprintf(os, "r%d", reg);
193 ccprintf(os, "f%d", reg - FP_Base_DepTag);
197 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
199 std::stringstream ss;
201 ccprintf(ss, "%-10s ", mnemonic);
203 // just print the first two source regs... if there's
204 // a third one, it's a read-modify-write dest (Rc),
206 if (_numSrcRegs > 0) {
207 printReg(ss, _srcRegIdx[0]);
209 if (_numSrcRegs > 1) {
211 printReg(ss, _srcRegIdx[1]);
214 // just print the first dest... if there's a second one,
215 // it's generally implicit
216 if (_numDestRegs > 0) {
219 printReg(ss, _destRegIdx[0]);
228 def template BasicDeclare {{
230 * Static instruction class for "%(mnemonic)s".
232 class %(class_name)s : public %(base_class)s
236 %(class_name)s(MachInst machInst)
237 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
242 Fault execute(SimpleCPU *cpu, ExecContext *xc,
243 Trace::InstRecord *traceData)
245 SimpleCPU *memAccessObj __attribute__((unused)) = cpu;
246 Fault fault = No_Fault;
253 if (fault == No_Fault) {
260 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
261 Trace::InstRecord *traceData)
263 DynInst *memAccessObj __attribute__((unused)) = dynInst;
264 Fault fault = No_Fault;
271 if (fault == No_Fault) {
280 def template BasicDecode {{
281 return new %(class_name)s(machInst);
284 def template BasicDecodeWithMnemonic {{
285 return new %(class_name)s("%(mnemonic)s", machInst);
288 // The most basic instruction format... used only for a few misc. insts
289 def format BasicOperate(code, *flags) {{
290 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
291 return iop.subst('BasicDeclare', 'BasicDecode')
296 ////////////////////////////////////////////////////////////////////
300 * Static instruction class for no-ops. This is a leaf class.
302 class Nop : public AlphaStaticInst
304 /// Disassembly of original instruction.
305 const std::string originalDisassembly;
309 Nop(const std::string _originalDisassembly, MachInst _machInst)
310 : AlphaStaticInst("nop", _machInst, No_OpClass),
311 originalDisassembly(_originalDisassembly)
318 Fault execute(SimpleCPU *cpu, ExecContext *xc,
319 Trace::InstRecord *traceData)
324 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
325 Trace::InstRecord *traceData)
330 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
332 #ifdef SS_COMPATIBLE_DISASSEMBLY
333 return originalDisassembly;
335 return csprintf("%-10s (%s)", "nop", originalDisassembly);
340 /// Helper function for decoding nops. Substitute Nop object
341 /// for original inst passed in as arg (and delete latter).
344 makeNop(AlphaStaticInst *inst)
346 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
353 return ('', 'return new Nop("%s", machInst);\n' % name)
357 // integer & FP operate instructions use Rc as dest, so check for
358 // Rc == 31 to detect nops
359 def template OperateNopCheckDecode {{
361 AlphaStaticInst *i = new %(class_name)s(machInst);
369 // Like BasicOperate format, but generates NOP if RC/FC == 31
370 def format BasicOperateWithNopCheck(code, *opt_args) {{
371 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
373 return iop.subst('BasicDeclare', 'OperateNopCheckDecode')
377 ////////////////////////////////////////////////////////////////////
379 // Integer operate instructions
384 * Base class for integer immediate instructions.
386 class IntegerImm : public AlphaStaticInst
389 /// Immediate operand value (unsigned 8-bit int).
393 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
394 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
398 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
400 std::stringstream ss;
402 ccprintf(ss, "%-10s ", mnemonic);
404 // just print the first source reg... if there's
405 // a second one, it's a read-modify-write dest (Rc),
407 if (_numSrcRegs > 0) {
408 printReg(ss, _srcRegIdx[0]);
414 if (_numDestRegs > 0) {
416 printReg(ss, _destRegIdx[0]);
424 def template RegOrImmDecode {{
427 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
428 : (AlphaStaticInst *)new %(class_name)s(machInst);
436 // Primary format for integer operate instructions:
437 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
438 // - Generates NOP if RC == 31.
439 def format IntegerOperate(code, *opt_flags) {{
440 # If the code block contains 'Rb_or_imm', we define two instructions,
441 # one using 'Rb' and one using 'imm', and have the decoder select
443 uses_imm = (code.find('Rb_or_imm') != -1)
446 # base code is reg version:
447 # rewrite by substituting 'Rb' for 'Rb_or_imm'
448 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
449 # generate immediate version by substituting 'imm'
450 # note that imm takes no extenstion, so we extend
451 # the regexp to replace any extension as well
452 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
454 # generate declaration for register version
455 cblk = CodeBlock(code)
456 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
457 decls = iop.subst('BasicDeclare')
460 # append declaration for imm version
461 imm_cblk = CodeBlock(imm_code)
462 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
464 decls += imm_iop.subst('BasicDeclare')
465 # decode checks IMM bit to pick correct version
466 decode = iop.subst('RegOrImmDecode')
468 # no imm version: just check for nop
469 decode = iop.subst('OperateNopCheckDecode')
471 return (decls, decode)
475 ////////////////////////////////////////////////////////////////////
477 // Floating-point instructions
479 // Note that many FP-type instructions which do not support all the
480 // various rounding & trapping modes use the simpler format
481 // BasicOperateWithNopCheck.
486 * Base class for general floating-point instructions. Includes
487 * support for various Alpha rounding and trapping modes. Only FP
488 * instructions that require this support are derived from this
489 * class; the rest derive directly from AlphaStaticInst.
491 class AlphaFP : public AlphaStaticInst
494 /// Alpha FP rounding modes.
496 Chopped = 0, ///< round toward zero
497 Minus_Infinity = 1, ///< round toward minus infinity
498 Normal = 2, ///< round to nearest (default)
499 Dynamic = 3, ///< use FPCR setting (in instruction)
500 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
503 /// Alpha FP trapping modes.
504 /// For instructions that produce integer results, the
505 /// "Underflow Enable" modes really mean "Overflow Enable", and
506 /// the assembly modifier is V rather than U.
508 /// default: nothing enabled
509 Imprecise = 0, ///< no modifier
510 /// underflow/overflow traps enabled, inexact disabled
511 Underflow_Imprecise = 1, ///< /U or /V
512 Underflow_Precise = 5, ///< /SU or /SV
513 /// underflow/overflow and inexact traps enabled
514 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
519 static const int alphaToC99RoundingMode[];
522 /// Map enum RoundingMode values to disassembly suffixes.
523 static const char *roundingModeSuffix[];
524 /// Map enum TrappingMode values to FP disassembly suffixes.
525 static const char *fpTrappingModeSuffix[];
526 /// Map enum TrappingMode values to integer disassembly suffixes.
527 static const char *intTrappingModeSuffix[];
529 /// This instruction's rounding mode.
530 RoundingMode roundingMode;
531 /// This instruction's trapping mode.
532 TrappingMode trappingMode;
535 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
536 : AlphaStaticInst(mnem, _machInst, __opClass),
537 roundingMode((enum RoundingMode)FP_ROUNDMODE),
538 trappingMode((enum TrappingMode)FP_TRAPMODE)
540 if (trappingMode != Imprecise) {
541 warn("precise FP traps unimplemented\n");
547 getC99RoundingMode(ExecContext *xc)
549 if (roundingMode == Dynamic) {
550 return alphaToC99RoundingMode[bits(xc->readFpcr(), 59, 58)];
553 return alphaToC99RoundingMode[roundingMode];
558 // This differs from the AlphaStaticInst version only in
559 // printing suffixes for non-default rounding & trapping modes.
560 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
562 std::string mnem_str(mnemonic);
564 #ifndef SS_COMPATIBLE_DISASSEMBLY
565 std::string suffix("");
566 suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
567 ? fpTrappingModeSuffix[trappingMode]
568 : intTrappingModeSuffix[trappingMode]);
569 suffix += roundingModeSuffix[roundingMode];
572 mnem_str = csprintf("%s/%s", mnemonic, suffix);
576 std::stringstream ss;
577 ccprintf(ss, "%-10s ", mnem_str.c_str());
579 // just print the first two source regs... if there's
580 // a third one, it's a read-modify-write dest (Rc),
582 if (_numSrcRegs > 0) {
583 printReg(ss, _srcRegIdx[0]);
585 if (_numSrcRegs > 1) {
587 printReg(ss, _srcRegIdx[1]);
590 // just print the first dest... if there's a second one,
591 // it's generally implicit
592 if (_numDestRegs > 0) {
595 printReg(ss, _destRegIdx[0]);
603 const int AlphaFP::alphaToC99RoundingMode[] = {
604 FE_TOWARDZERO, // Chopped
605 FE_DOWNWARD, // Minus_Infinity
606 FE_TONEAREST, // Normal
607 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
611 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
612 // mark invalid trapping modes, but don't fail on them, because
613 // you could decode anything on a misspeculated path
614 const char *AlphaFP::fpTrappingModeSuffix[] =
615 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
616 const char *AlphaFP::intTrappingModeSuffix[] =
617 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
621 def template FloatingPointDeclare {{
623 * "Fast" static instruction class for "%(mnemonic)s" (imprecise
624 * trapping mode, normal rounding mode).
626 class %(class_name)sFast : public %(base_class)s
630 %(class_name)sFast(MachInst machInst)
631 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
636 Fault execute(SimpleCPU *cpu, ExecContext *xc,
637 Trace::InstRecord *traceData)
639 Fault fault = No_Fault;
646 if (fault == No_Fault) {
653 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
654 Trace::InstRecord *traceData)
656 Fault fault = No_Fault;
663 if (fault == No_Fault) {
672 * General static instruction class for "%(mnemonic)s". Supports
673 * all the various rounding and trapping modes.
675 class %(class_name)sGeneral : public %(base_class)s
679 %(class_name)sGeneral(MachInst machInst)
680 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
685 Fault execute(SimpleCPU *cpu, ExecContext *xc,
686 Trace::InstRecord *traceData)
688 Fault fault = No_Fault;
695 fesetround(getC99RoundingMode(xc));
701 fesetround(FE_TONEAREST);
704 if (fault == No_Fault) {
711 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
712 Trace::InstRecord *traceData)
714 Fault fault = No_Fault;
721 fesetround(getC99RoundingMode(xc));
727 fesetround(FE_TONEAREST);
730 if (fault == No_Fault) {
739 def template FloatingPointDecode {{
741 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
742 && FP_ROUNDMODE == AlphaFP::Normal);
744 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
745 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
756 // General format for floating-point operate instructions:
757 // - Checks trapping and rounding mode flags. Trapping modes
758 // currently unimplemented (will fail).
759 // - Generates NOP if FC == 31.
760 def format FloatingPointOperate(code, *opt_args) {{
761 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code),
763 return iop.subst('FloatingPointDeclare', 'FloatingPointDecode')
767 ////////////////////////////////////////////////////////////////////
769 // Memory-format instructions: LoadAddress, Load, Store
774 * Base class for general Alpha memory-format instructions.
776 class Memory : public AlphaStaticInst
780 /// Displacement for EA calculation (signed).
782 /// Memory request flags. See mem_req_base.hh.
783 unsigned memAccessFlags;
786 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
787 : AlphaStaticInst(mnem, _machInst, __opClass),
788 disp(MEMDISP), memAccessFlags(0)
792 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
794 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
795 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
800 * Base class for a few miscellaneous memory-format insts
801 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
802 * None of these instructions has a destination register either.
804 class MemoryNoDisp : public AlphaStaticInst
807 /// Memory request flags. See mem_req_base.hh.
808 unsigned memAccessFlags;
811 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass)
812 : AlphaStaticInst(mnem, _machInst, __opClass),
817 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
819 return csprintf("%-10s (r%d)", mnemonic, RB);
824 * Base class for "fake" effective-address computation
825 * instructions returnded by eaCompInst().
827 class EACompBase : public AlphaStaticInst
831 EACompBase(MachInst machInst)
832 : AlphaStaticInst("(eacomp)", machInst, IntALU)
836 Fault execute(SimpleCPU *cpu, ExecContext *xc,
837 Trace::InstRecord *traceData)
838 { panic("attempt to execute eacomp"); }
840 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
841 Trace::InstRecord *traceData)
842 { panic("attempt to execute eacomp"); }
846 * Base class for "fake" memory-access instructions returnded by
849 class MemAccBase : public AlphaStaticInst
853 MemAccBase(MachInst machInst, OpClass __opClass)
854 : AlphaStaticInst("(memacc)", machInst, __opClass)
858 Fault execute(SimpleCPU *cpu, ExecContext *xc,
859 Trace::InstRecord *traceData)
860 { panic("attempt to execute memacc"); }
862 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
863 Trace::InstRecord *traceData)
864 { panic("attempt to execute memacc"); }
870 def format LoadAddress(code) {{
871 iop = InstObjParams(name, Name, 'Memory', CodeBlock(code))
872 return iop.subst('BasicDeclare', 'BasicDecode')
876 def template LoadStoreDeclare {{
878 * Static instruction class for "%(mnemonic)s".
880 class %(class_name)s : public %(base_class)s
885 * "Fake" effective address computation class for "%(mnemonic)s".
887 class EAComp : public EACompBase
891 EAComp(MachInst machInst)
892 : EACompBase(machInst)
899 * "Fake" memory access instruction class for "%(mnemonic)s".
901 class MemAcc : public MemAccBase
905 MemAcc(MachInst machInst)
906 : MemAccBase(machInst, %(op_class)s)
908 %(memacc_constructor)s;
912 /// Pointer to EAComp object.
913 StaticInstPtr<AlphaISA> eaCompPtr;
914 /// Pointer to MemAcc object.
915 StaticInstPtr<AlphaISA> memAccPtr;
919 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
920 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
923 %(class_name)s(MachInst machInst)
924 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
925 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
930 Fault execute(SimpleCPU *cpu, ExecContext *xc,
931 Trace::InstRecord *traceData)
933 SimpleCPU *memAccessObj = cpu;
935 Fault fault = No_Fault;
939 %(simple_nonmem_rd)s;
942 if (fault == No_Fault) {
947 if (fault == No_Fault) {
951 if (fault == No_Fault) {
955 if (fault == No_Fault) {
956 %(simple_nonmem_wb)s;
962 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
963 Trace::InstRecord *traceData)
965 DynInst *memAccessObj = dynInst;
967 Fault fault = No_Fault;
974 if (fault == No_Fault) {
979 if (fault == No_Fault) {
983 if (fault == No_Fault) {
987 if (fault == No_Fault) {
997 def template PrefetchDeclare {{
999 * Static instruction class for "%(mnemonic)s".
1001 class %(class_name)s : public %(base_class)s
1005 %(class_name)s(MachInst machInst)
1006 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
1011 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1012 Trace::InstRecord *traceData)
1015 Fault fault = No_Fault;
1017 %(fp_enable_check)s;
1019 %(simple_nonmem_rd)s;
1022 if (fault == No_Fault) {
1023 cpu->prefetch(EA, memAccessFlags);
1029 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1030 Trace::InstRecord *traceData)
1033 Fault fault = No_Fault;
1035 %(fp_enable_check)s;
1040 if (fault == No_Fault) {
1041 dynInst->prefetch(EA, memAccessFlags);
1050 // load instructions use Ra as dest, so check for
1051 // Ra == 31 to detect nops
1052 def template LoadNopCheckDecode {{
1054 AlphaStaticInst *i = new %(class_name)s(machInst);
1063 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1064 def template LoadPrefetchCheckDecode {{
1067 return new %(class_name)s(machInst);
1070 return new %(class_name)sPrefetch(machInst);
1077 global LoadStoreBase
1078 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1079 base_class = 'Memory', flags = [],
1080 declare_template = 'LoadStoreDeclare',
1081 decode_template = 'BasicDecode'):
1082 # Segregate flags into instruction flags (handled by InstObjParams)
1083 # and memory access flags (handled here).
1085 # Would be nice to autogenerate this list, but oh well.
1086 valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1090 if f in valid_mem_flags:
1093 inst_flags.append(f)
1095 ea_cblk = CodeBlock(ea_code)
1096 memacc_cblk = CodeBlock(memacc_code)
1097 postacc_cblk = CodeBlock(postacc_code)
1099 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1100 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1102 iop.ea_constructor = ea_cblk.constructor
1103 iop.ea_code = ea_cblk.code
1104 iop.memacc_constructor = memacc_cblk.constructor
1105 iop.memacc_code = memacc_cblk.code
1106 iop.postacc_code = postacc_cblk.code
1108 mem_flags = string.join(mem_flags, '|')
1110 iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
1112 return iop.subst(declare_template, decode_template)
1116 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1117 return LoadStoreBase(name, Name, ea_code, memacc_code,
1119 decode_template = 'LoadNopCheckDecode')
1123 // Note that the flags passed in apply only to the prefetch version
1124 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1125 # declare the load instruction object and generate the decode block
1127 LoadStoreBase(name, Name, ea_code, memacc_code,
1128 decode_template = 'LoadPrefetchCheckDecode')
1130 # Declare the prefetch instruction object.
1132 # convert flags from tuple to list to make them mutable
1133 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'RdPort']
1135 (pfdecls, pfdecode) = \
1136 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1138 declare_template = 'PrefetchDeclare')
1140 return (decls + pfdecls, decode)
1144 def format Store(ea_code, memacc_code, *flags) {{
1145 return LoadStoreBase(name, Name, ea_code, memacc_code,
1150 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1151 return LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1156 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1157 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1158 return LoadStoreBase(name, Name, ea_code, memacc_code,
1159 flags = flags, base_class = 'MemoryNoDisp')
1163 ////////////////////////////////////////////////////////////////////
1169 * Base class for instructions whose disassembly is not purely a
1170 * function of the machine instruction (i.e., it depends on the
1171 * PC). This class overrides the disassemble() method to check
1172 * the PC and symbol table values before re-using a cached
1173 * disassembly string. This is necessary for branches and jumps,
1174 * where the disassembly string includes the target address (which
1175 * may depend on the PC and/or symbol table).
1177 class PCDependentDisassembly : public AlphaStaticInst
1180 /// Cached program counter from last disassembly
1182 /// Cached symbol table pointer from last disassembly
1183 const SymbolTable *cachedSymtab;
1186 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1188 : AlphaStaticInst(mnem, _machInst, __opClass),
1189 cachedPC(0), cachedSymtab(0)
1193 const std::string &disassemble(Addr pc, const SymbolTable *symtab)
1195 if (!cachedDisassembly ||
1196 pc != cachedPC || symtab != cachedSymtab)
1198 if (cachedDisassembly)
1199 delete cachedDisassembly;
1202 new std::string(generateDisassembly(pc, symtab));
1204 cachedSymtab = symtab;
1207 return *cachedDisassembly;
1212 * Base class for branches (PC-relative control transfers),
1213 * conditional or unconditional.
1215 class Branch : public PCDependentDisassembly
1218 /// Displacement to target address (signed).
1222 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1223 : PCDependentDisassembly(mnem, _machInst, __opClass),
1228 Addr branchTarget(Addr branchPC) const
1230 return branchPC + 4 + disp;
1233 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1235 std::stringstream ss;
1237 ccprintf(ss, "%-10s ", mnemonic);
1239 // There's only one register arg (RA), but it could be
1240 // either a source (the condition for conditional
1241 // branches) or a destination (the link reg for
1242 // unconditional branches)
1243 if (_numSrcRegs > 0) {
1244 printReg(ss, _srcRegIdx[0]);
1247 else if (_numDestRegs > 0) {
1248 printReg(ss, _destRegIdx[0]);
1252 #ifdef SS_COMPATIBLE_DISASSEMBLY
1253 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1259 Addr target = pc + 4 + disp;
1262 if (symtab && symtab->findSymbol(target, str))
1265 ccprintf(ss, "0x%x", target);
1272 * Base class for jumps (register-indirect control transfers). In
1273 * the Alpha ISA, these are always unconditional.
1275 class Jump : public PCDependentDisassembly
1279 /// Displacement to target address (signed).
1284 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1285 : PCDependentDisassembly(mnem, _machInst, __opClass),
1290 Addr branchTarget(ExecContext *xc) const
1292 Addr NPC = xc->readPC() + 4;
1293 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
1294 return (Rb & ~3) | (NPC & 1);
1297 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1299 std::stringstream ss;
1301 ccprintf(ss, "%-10s ", mnemonic);
1303 #ifdef SS_COMPATIBLE_DISASSEMBLY
1304 if (_numDestRegs == 0) {
1310 if (_numDestRegs > 0) {
1311 printReg(ss, _destRegIdx[0]);
1315 ccprintf(ss, "(r%d)", RB);
1322 def template JumpOrBranchDecode {{
1324 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1325 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1328 def format CondBranch(code) {{
1329 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1330 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1331 ('IsDirectControl', 'IsCondControl'))
1332 return iop.subst('BasicDeclare', 'BasicDecode')
1336 global UncondCtrlBase
1337 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1338 # Declare basic control transfer w/o link (i.e. link reg is R31)
1339 nolink_code = 'NPC = %s;\n' % npc_expr
1340 nolink_iop = InstObjParams(name, Name, base_class,
1341 CodeBlock(nolink_code), flags)
1342 decls = nolink_iop.subst('BasicDeclare')
1344 # Generate declaration of '*AndLink' version, append to decls
1345 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1346 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1347 CodeBlock(link_code), flags)
1348 decls += link_iop.subst('BasicDeclare')
1350 # need to use link_iop for the decode template since it is expecting
1351 # the shorter version of class_name (w/o "AndLink")
1352 return (decls, nolink_iop.subst('JumpOrBranchDecode'))
1355 def format UncondBranch(*flags) {{
1356 flags += ('IsUncondControl', 'IsDirectControl')
1357 return UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1360 def format Jump(*flags) {{
1361 flags += ('IsUncondControl', 'IsIndirectControl')
1362 return UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1368 * Base class for emulated call_pal calls (used only in
1369 * non-full-system mode).
1371 class EmulatedCallPal : public AlphaStaticInst
1376 EmulatedCallPal(const char *mnem, MachInst _machInst,
1378 : AlphaStaticInst(mnem, _machInst, __opClass)
1382 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1384 #ifdef SS_COMPATIBLE_DISASSEMBLY
1385 return csprintf("%s %s", "call_pal", mnemonic);
1387 return csprintf("%-10s %s", "call_pal", mnemonic);
1393 def format EmulatedCallPal(code) {{
1394 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code))
1395 return iop.subst('BasicDeclare', 'BasicDecode')
1400 * Base class for full-system-mode call_pal instructions.
1401 * Probably could turn this into a leaf class and get rid of the
1404 class CallPalBase : public AlphaStaticInst
1407 int palFunc; ///< Function code part of instruction
1408 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1409 bool palValid; ///< is the function code valid?
1410 bool palPriv; ///< is this call privileged?
1413 CallPalBase(const char *mnem, MachInst _machInst,
1415 : AlphaStaticInst(mnem, _machInst, __opClass),
1418 // From the 21164 HRM (paraphrased):
1419 // Bit 7 of the function code (mask 0x80) indicates
1420 // whether the call is privileged (bit 7 == 0) or
1421 // unprivileged (bit 7 == 1). The privileged call table
1422 // starts at 0x2000, the unprivielged call table starts at
1423 // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
1425 const int palPrivMask = 0x80;
1426 const int palOffsetMask = 0x3f;
1428 // Pal call is invalid unless all other bits are 0
1429 palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
1430 palPriv = ((machInst & palPrivMask) == 0);
1431 int shortPalFunc = (machInst & palOffsetMask);
1432 // Add 1 to base to set pal-mode bit
1433 palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
1436 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1438 return csprintf("%-10s %#x", "call_pal", palFunc);
1444 def format CallPal(code) {{
1445 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code))
1446 return iop.subst('BasicDeclare', 'BasicDecode')
1454 * Base class for hw_ld and hw_st.
1456 class HwLoadStore : public AlphaStaticInst
1460 /// Displacement for EA calculation (signed).
1462 /// Memory request flags. See mem_req_base.hh.
1463 unsigned memAccessFlags;
1466 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass)
1467 : AlphaStaticInst(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
1470 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1471 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1472 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1473 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1476 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1478 #ifdef SS_COMPATIBLE_DISASSEMBLY
1479 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1481 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1482 const char *lock_str =
1483 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1485 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1486 mnemonic, RA, disp, RB,
1487 HW_LDST_PHYS ? ",PHYS" : "",
1488 HW_LDST_ALT ? ",ALT" : "",
1489 HW_LDST_QUAD ? ",QUAD" : "",
1490 HW_LDST_VPTE ? ",VPTE" : "",
1498 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1499 return LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1501 base_class = 'HwLoadStore')
1505 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1506 return LoadStoreBase(name, Name + class_ext,
1507 ea_code, memacc_code, postacc_code,
1509 base_class = 'HwLoadStore')
1515 * Base class for hw_mfpr and hw_mtpr.
1517 class HwMoveIPR : public AlphaStaticInst
1520 /// Index of internal processor register.
1524 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1525 : AlphaStaticInst(mnem, _machInst, __opClass),
1526 ipr_index(HW_IPR_IDX)
1530 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1532 if (_numSrcRegs > 0) {
1534 return csprintf("%-10s r%d,IPR(%#x)",
1535 mnemonic, RA, ipr_index);
1539 return csprintf("%-10s IPR(%#x),r%d",
1540 mnemonic, ipr_index, RA);
1546 def format HwMoveIPR(code) {{
1547 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1548 return iop.subst('BasicDeclare', 'BasicDecode')
1553 * Static instruction class for unimplemented instructions that
1554 * cause simulator termination. Note that these are recognized
1555 * (legal) instructions that the simulator does not support; the
1556 * 'Unknown' class is used for unrecognized/illegal instructions.
1557 * This is a leaf class.
1559 class FailUnimplemented : public AlphaStaticInst
1563 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1564 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1568 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1569 Trace::InstRecord *traceData)
1571 panic("attempt to execute unimplemented instruction '%s' "
1572 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1573 return Unimplemented_Opcode_Fault;
1576 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1577 Trace::InstRecord *traceData)
1579 // don't panic if this is a misspeculated instruction
1581 panic("attempt to execute unimplemented instruction '%s' "
1582 "(inst 0x%08x, opcode 0x%x)",
1583 mnemonic, machInst, OPCODE);
1584 return Unimplemented_Opcode_Fault;
1587 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1589 return csprintf("%-10s (unimplemented)", mnemonic);
1594 * Base class for unimplemented instructions that cause a warning
1595 * to be printed (but do not terminate simulation). This
1596 * implementation is a little screwy in that it will print a
1597 * warning for each instance of a particular unimplemented machine
1598 * instruction, not just for each unimplemented opcode. Should
1599 * probably make the 'warned' flag a static member of the derived
1602 class WarnUnimplemented : public AlphaStaticInst
1605 /// Have we warned on this instruction yet?
1610 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1611 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1615 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1616 Trace::InstRecord *traceData)
1619 warn("instruction '%s' unimplemented\n", mnemonic);
1626 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1627 Trace::InstRecord *traceData)
1629 if (!xc->spec_mode && !warned) {
1630 warn("instruction '%s' unimplemented\n", mnemonic);
1637 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1639 #ifdef SS_COMPATIBLE_DISASSEMBLY
1640 return csprintf("%-10s", mnemonic);
1642 return csprintf("%-10s (unimplemented)", mnemonic);
1648 def template WarnUnimplDeclare {{
1650 * Static instruction class for "%(mnemonic)s".
1652 class %(class_name)s : public %(base_class)s
1656 %(class_name)s(MachInst machInst)
1657 : %(base_class)s("%(mnemonic)s", machInst)
1664 def format FailUnimpl() {{
1665 iop = InstObjParams(name, 'FailUnimplemented')
1666 return ('', iop.subst('BasicDecodeWithMnemonic'))
1669 def format WarnUnimpl() {{
1670 iop = InstObjParams(name, Name, 'WarnUnimplemented')
1671 return iop.subst('WarnUnimplDeclare', 'BasicDecode')
1676 * Static instruction class for unknown (illegal) instructions.
1677 * These cause simulator termination if they are executed in a
1678 * non-speculative mode. This is a leaf class.
1680 class Unknown : public AlphaStaticInst
1684 Unknown(MachInst _machInst)
1685 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1689 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1690 Trace::InstRecord *traceData)
1692 panic("attempt to execute unknown instruction "
1693 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1694 return Unimplemented_Opcode_Fault;
1697 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1698 Trace::InstRecord *traceData)
1700 // don't panic if this is a misspeculated instruction
1702 panic("attempt to execute unknown instruction "
1703 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1704 return Unimplemented_Opcode_Fault;
1707 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1709 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1710 "unknown", machInst, OPCODE);
1715 def format Unknown() {{
1716 return ('', 'return new Unknown(machInst);\n')
1721 /// Return opa + opb, summing carry into third arg.
1723 addc(uint64_t opa, uint64_t opb, int &carry)
1725 uint64_t res = opa + opb;
1726 if (res < opa || res < opb)
1731 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1732 /// product in res_hi and res_lo.
1734 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1736 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1737 uint64_t opa_hi = opa<63:32>;
1738 uint64_t opa_lo = opa<31:0>;
1739 uint64_t opb_hi = opb<63:32>;
1740 uint64_t opb_lo = opb<31:0>;
1742 res_lo = opa_lo * opb_lo;
1744 // The middle partial products logically belong in bit
1745 // positions 95 to 32. Thus the lower 32 bits of each product
1746 // sum into the upper 32 bits of the low result, while the
1747 // upper 32 sum into the low 32 bits of the upper result.
1748 uint64_t partial1 = opa_hi * opb_lo;
1749 uint64_t partial2 = opa_lo * opb_hi;
1751 uint64_t partial1_lo = partial1<31:0> << 32;
1752 uint64_t partial1_hi = partial1<63:32>;
1753 uint64_t partial2_lo = partial2<31:0> << 32;
1754 uint64_t partial2_hi = partial2<63:32>;
1756 // Add partial1_lo and partial2_lo to res_lo, keeping track
1757 // of any carries out
1759 res_lo = addc(partial1_lo, res_lo, carry_out);
1760 res_lo = addc(partial2_lo, res_lo, carry_out);
1762 // Now calculate the high 64 bits...
1763 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1766 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1767 /// See Table 2-2 of Alpha AHB.
1771 int hibit = old_exp<7:>;
1772 int lobits = old_exp<6:0>;
1775 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1778 return (lobits == 0) ? 0 : (0x380 | lobits);
1782 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1783 /// representation to be stored in an FP reg.
1785 s_to_t(uint32_t s_val)
1787 uint64_t tmp = s_val;
1788 return (tmp<31:> << 63 // sign bit
1789 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1790 | tmp<22:0> << 29); // fraction
1793 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1794 /// S-floating representation to be stored in memory.
1796 t_to_s(uint64_t t_val)
1798 return (t_val<63:62> << 30 // sign bit & hi exp bit
1799 | t_val<58:29>); // rest of exp & fraction
1803 decode OPCODE default Unknown::unknown() {
1805 format LoadAddress {
1806 0x08: lda({{ Ra = Rb + disp; }});
1807 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1811 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1812 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1813 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1814 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1815 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1816 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1819 format LoadOrPrefetch {
1820 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1821 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1822 // IsFloating flag on lds gets the prefetch to disassemble
1823 // using f31 instead of r31... funcitonally it's unnecessary
1824 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1825 PF_EXCLUSIVE, IsFloating);
1829 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1830 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1831 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1832 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1833 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1834 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1835 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1839 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1841 uint64_t tmp = Mem_write_result;
1843 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1845 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1847 uint64_t tmp = Mem_write_result;
1848 // If the write operation returns 0 or 1, then
1849 // this was a conventional store conditional,
1850 // and the value indicates the success/failure
1851 // of the operation. If another value is
1852 // returned, then this was a Turbolaser
1853 // mailbox access, and we don't update the
1854 // result register at all.
1855 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1859 format IntegerOperate {
1861 0x10: decode INTFUNC { // integer arithmetic operations
1863 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1865 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1866 // signed overflow occurs when operands have same sign
1867 // and sign of result does not match.
1868 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1869 fault = Integer_Overflow_Fault;
1872 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1873 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1875 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1877 uint64_t tmp = Ra + Rb_or_imm;
1878 // signed overflow occurs when operands have same sign
1879 // and sign of result does not match.
1880 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1881 fault = Integer_Overflow_Fault;
1884 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1885 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1887 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1889 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1890 // signed overflow detection is same as for add,
1891 // except we need to look at the *complemented*
1892 // sign bit of the subtrahend (Rb), i.e., if the initial
1893 // signs are the *same* then no overflow can occur
1894 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1895 fault = Integer_Overflow_Fault;
1898 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1899 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1901 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1903 uint64_t tmp = Ra - Rb_or_imm;
1904 // signed overflow detection is same as for add,
1905 // except we need to look at the *complemented*
1906 // sign bit of the subtrahend (Rb), i.e., if the initial
1907 // signs are the *same* then no overflow can occur
1908 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1909 fault = Integer_Overflow_Fault;
1912 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1913 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1915 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1916 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1917 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1918 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1919 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1925 for (int i = 0; i < 8; ++i) {
1926 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1934 0x11: decode INTFUNC { // integer logical operations
1936 0x00: and({{ Rc = Ra & Rb_or_imm; }});
1937 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1938 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1939 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1940 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1941 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1943 // conditional moves
1944 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1945 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1946 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1947 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1948 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
1949 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1950 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1951 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
1953 // For AMASK, RA must be R31.
1955 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1958 // For IMPLVER, RA must be R31 and the B operand
1959 // must be the immediate value 1.
1963 // return EV5 for FULL_SYSTEM and EV6 otherwise
1976 // The mysterious 11.25...
1977 0x25: WarnUnimpl::eleven25();
1981 0x12: decode INTFUNC {
1982 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
1983 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
1984 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
1986 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
1987 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
1988 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
1989 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
1992 int bv = Rb_or_imm<2:0>;
1993 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
1996 int bv = Rb_or_imm<2:0>;
1997 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2000 int bv = Rb_or_imm<2:0>;
2001 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2004 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2005 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2006 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2007 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2010 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2012 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2014 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2016 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2017 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2018 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2019 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
2022 int bv = Rb_or_imm<2:0>;
2023 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2026 int bv = Rb_or_imm<2:0>;
2027 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2030 int bv = Rb_or_imm<2:0>;
2031 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
2035 uint64_t zapmask = 0;
2036 for (int i = 0; i < 8; ++i) {
2038 zapmask |= (mask(8) << (i * 8));
2043 uint64_t zapmask = 0;
2044 for (int i = 0; i < 8; ++i) {
2046 zapmask |= (mask(8) << (i * 8));
2052 0x13: decode INTFUNC { // integer multiplies
2053 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMULT);
2054 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMULT);
2057 mul128(Ra, Rb_or_imm, hi, lo);
2061 // 32-bit multiply with trap on overflow
2062 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
2063 int64_t Rbx = Rb_or_imm.sl;
2064 int64_t tmp = Rax * Rbx;
2065 // To avoid overflow, all the upper 32 bits must match
2066 // the sign bit of the lower 32. We code this as
2067 // checking the upper 33 bits for all 0s or all 1s.
2068 uint64_t sign_bits = tmp<63:31>;
2069 if (sign_bits != 0 && sign_bits != mask(33))
2070 fault = Integer_Overflow_Fault;
2074 // 64-bit multiply with trap on overflow
2076 mul128(Ra, Rb_or_imm, hi, lo);
2077 // all the upper 64 bits must match the sign bit of
2079 if (!((hi == 0 && lo<63:> == 0) ||
2080 (hi == mask(64) && lo<63:> == 1)))
2081 fault = Integer_Overflow_Fault;
2086 0x1c: decode INTFUNC {
2087 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2088 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2109 format BasicOperateWithNopCheck {
2111 31: ftoit({{ Rc = Fa.uq; }}, FloatCVT);
2114 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2121 // Conditional branches.
2123 0x39: beq({{ cond = (Ra == 0); }});
2124 0x3d: bne({{ cond = (Ra != 0); }});
2125 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2126 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2127 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2128 0x3a: blt({{ cond = (Ra.sq < 0); }});
2129 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2130 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2132 0x31: fbeq({{ cond = (Fa == 0); }});
2133 0x35: fbne({{ cond = (Fa != 0); }});
2134 0x36: fbge({{ cond = (Fa >= 0); }});
2135 0x37: fbgt({{ cond = (Fa > 0); }});
2136 0x33: fble({{ cond = (Fa <= 0); }});
2137 0x32: fblt({{ cond = (Fa < 0); }});
2140 // unconditional branches
2141 format UncondBranch {
2146 // indirect branches
2147 0x1a: decode JMPFUNC {
2152 3: jsr_coroutine(IsCall, IsReturn);
2156 // IEEE floating point
2157 0x14: decode FP_SHORTFUNC {
2158 // Integer to FP register moves must have RB == 31
2160 31: decode FP_FULLFUNC {
2161 format BasicOperateWithNopCheck {
2162 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCVT);
2163 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCVT);
2164 0x014: FailUnimpl::itoff(); // VAX-format conversion
2169 // Square root instructions must have FA == 31
2171 31: decode FP_TYPEFUNC {
2172 format FloatingPointOperate {
2173 #ifdef SS_COMPATIBLE_FP
2176 fault = Arithmetic_Fault;
2182 fault = Arithmetic_Fault;
2183 Fc.sf = sqrt(Fb.sf);
2188 fault = Arithmetic_Fault;
2195 // VAX-format sqrtf and sqrtg are not implemented
2196 0xa: FailUnimpl::sqrtfg();
2199 // IEEE floating point
2200 0x16: decode FP_SHORTFUNC_TOP2 {
2201 // The top two bits of the short function code break this space
2202 // into four groups: binary ops, compares, reserved, and conversions.
2203 // See Table 4-12 of AHB.
2204 // Most of these instructions may have various trapping and
2205 // rounding mode flags set; these are decoded in the
2206 // FloatingPointDecode template used by the
2207 // FloatingPointOperate format.
2209 // add/sub/mul/div: just decode on the short function code
2211 0: decode FP_TYPEFUNC {
2212 format FloatingPointOperate {
2213 #ifdef SS_COMPATIBLE_FP
2214 0x00: adds({{ Fc = Fa + Fb; }});
2215 0x01: subs({{ Fc = Fa - Fb; }});
2216 0x02: muls({{ Fc = Fa * Fb; }}, FloatMULT);
2217 0x03: divs({{ Fc = Fa / Fb; }}, FloatDIV);
2219 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2220 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2221 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMULT);
2222 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDIV);
2225 0x20: addt({{ Fc = Fa + Fb; }});
2226 0x21: subt({{ Fc = Fa - Fb; }});
2227 0x22: mult({{ Fc = Fa * Fb; }}, FloatMULT);
2228 0x23: divt({{ Fc = Fa / Fb; }}, FloatDIV);
2232 // Floating-point compare instructions must have the default
2233 // rounding mode, and may use the default trapping mode or
2234 // /SU. Both trapping modes are treated the same by M5; the
2235 // only difference on the real hardware (as far a I can tell)
2236 // is that without /SU you'd get an imprecise trap if you
2237 // tried to compare a NaN with something else (instead of an
2238 // "unordered" result).
2239 1: decode FP_FULLFUNC {
2240 format BasicOperateWithNopCheck {
2241 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2243 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2245 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2247 0x0a4, 0x5a4: cmptun({{ // unordered
2248 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2253 // The FP-to-integer and integer-to-FP conversion insts
2254 // require that FA be 31.
2256 31: decode FP_TYPEFUNC {
2257 format FloatingPointOperate {
2258 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2260 // The cvtts opcode is overloaded to be cvtst if the trap
2261 // mode is 2 or 6 (which are not valid otherwise)
2262 0x2c: decode FP_FULLFUNC {
2263 format BasicOperateWithNopCheck {
2264 // trap on denorm version "cvtst/s" is
2265 // simulated same as cvtst
2266 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2268 default: cvtts({{ Fc.sf = Fb; }});
2271 // The trapping mode for integer-to-FP conversions
2272 // must be /SUI or nothing; /U and /SU are not
2273 // allowed. The full set of rounding modes are
2274 // supported though.
2275 0x3c: decode FP_TRAPMODE {
2276 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2278 0x3e: decode FP_TRAPMODE {
2279 0,7: cvtqt({{ Fc = Fb.sq; }});
2287 0x17: decode FP_FULLFUNC {
2288 format BasicOperateWithNopCheck {
2290 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2293 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2296 // We treat the precise & imprecise trapping versions of
2297 // cvtql identically.
2298 0x130, 0x530: cvtqlv({{
2299 // To avoid overflow, all the upper 32 bits must match
2300 // the sign bit of the lower 32. We code this as
2301 // checking the upper 33 bits for all 0s or all 1s.
2302 uint64_t sign_bits = Fb.uq<63:31>;
2303 if (sign_bits != 0 && sign_bits != mask(33))
2304 fault = Integer_Overflow_Fault;
2305 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2308 0x020: cpys({{ // copy sign
2309 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2311 0x021: cpysn({{ // copy sign negated
2312 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2314 0x022: cpyse({{ // copy sign and exponent
2315 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2318 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2319 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2320 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2321 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2322 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2323 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2325 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2326 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2330 // miscellaneous mem-format ops
2331 0x18: decode MEMFUNC {
2338 format MiscPrefetch {
2339 0xf800: wh64({{ EA = Rb; }},
2340 {{ memAccessObj->writeHint(EA, 64); }},
2341 IsMemRef, IsStore, WrPort);
2344 format BasicOperate {
2345 0xc000: rpcc({{ Ra = curTick; }});
2347 // All of the barrier instructions below do nothing in
2348 // their execute() methods (hence the empty code blocks).
2349 // All of their functionality is hard-coded in the
2350 // pipeline based on the flags IsSerializing,
2351 // IsMemBarrier, and IsWriteBarrier. In the current
2352 // detailed CPU model, the execute() function only gets
2353 // called at fetch, so there's no way to generate pipeline
2354 // behavior at any other stage. Once we go to an
2355 // exec-in-exec CPU model we should be able to get rid of
2356 // these flags and implement this behavior via the
2357 // execute() methods.
2359 // trapb is just a barrier on integer traps, where excb is
2360 // a barrier on integer and FP traps. "EXCB is thus a
2361 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
2362 // them the same though.
2363 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
2364 0x0400: excb({{ }}, IsSerializing, No_OpClass);
2365 0x4000: mb({{ }}, IsMemBarrier, RdPort);
2366 0x4400: wmb({{ }}, IsWriteBarrier, WrPort);
2370 format BasicOperate {
2372 Ra = xc->regs.intrflag;
2373 if (!xc->misspeculating()) {
2374 xc->regs.intrflag = 0;
2378 Ra = xc->regs.intrflag;
2379 if (!xc->misspeculating()) {
2380 xc->regs.intrflag = 1;
2393 0x00: CallPal::call_pal({{
2396 && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
2397 // invalid pal function code, or attempt to do privileged
2398 // PAL call in non-kernel mode
2399 fault = Unimplemented_Opcode_Fault;
2404 if (!xc->misspeculating()) {
2405 // check to see if simulator wants to do something special
2406 // on this PAL call (including maybe suppress it)
2407 dopal = xc->simPalCheck(palFunc);
2409 Annotate::Callpal(xc, palFunc);
2412 AlphaISA::swap_palshadow(&xc->regs, true);
2413 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2417 // if we're misspeculating, it's still safe (if
2418 // unrealistic) to set NPC, as the control-flow change
2419 // won't get committed.
2421 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2426 0x00: decode PALFUNC {
2427 format EmulatedCallPal {
2429 if (!xc->misspeculating())
2430 SimExit(curTick, "halt instruction encountered");
2433 if (!xc->misspeculating())
2436 // Read uniq reg into ABI return value register (r0)
2437 0x9e: rduniq({{ R0 = Runiq; }});
2438 // Write uniq reg with value from ABI arg register (r16)
2439 0x9f: wruniq({{ Runiq = R16; }});
2445 format HwLoadStore {
2446 0x1b: decode HW_LDST_QUAD {
2447 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2448 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2451 0x1f: decode HW_LDST_COND {
2452 0: decode HW_LDST_QUAD {
2453 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2454 {{ Mem.ul = Ra<31:0>; }}, L);
2455 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2456 {{ Mem.uq = Ra.uq; }}, Q);
2459 1: FailUnimpl::hw_st_cond();
2463 format BasicOperate {
2464 0x1e: hw_rei({{ xc->hwrei(); }});
2466 // M5 special opcodes use the reserved 0x01 opcode space
2467 0x01: decode M5FUNC {
2469 if (!xc->misspeculating()) {
2471 xc->kernelStats.arm();
2475 if (!xc->misspeculating())
2476 AlphaPseudo::quiesce(xc);
2479 if (!xc->misspeculating()) {
2480 Annotate::BeginInterval(xc);
2481 xc->kernelStats.ivlb();
2485 if (!xc->misspeculating())
2486 Annotate::EndInterval(xc);
2489 if (!xc->misspeculating())
2490 AlphaPseudo::m5exit_old(xc);
2493 if (!xc->misspeculating())
2494 AlphaPseudo::m5exit(xc);
2496 0x30: initparam({{ Ra = cpu->system->init_param; }});
2498 if (!xc->misspeculating())
2499 AlphaPseudo::resetstats(xc);
2502 if (!xc->misspeculating())
2503 AlphaPseudo::dumpstats(xc);
2505 0x42: dumpresetstats({{
2506 if (!xc->misspeculating())
2507 AlphaPseudo::dumpresetstats(xc);
2509 0x43: m5checkpoint({{
2510 if (!xc->misspeculating())
2511 AlphaPseudo::m5checkpoint(xc);
2518 // this instruction is only valid in PAL mode
2519 if (!PC_PAL(xc->regs.pc)) {
2520 fault = Unimplemented_Opcode_Fault;
2523 Ra = xc->readIpr(ipr_index, fault);
2527 // this instruction is only valid in PAL mode
2528 if (!PC_PAL(xc->regs.pc)) {
2529 fault = Unimplemented_Opcode_Fault;
2532 xc->setIpr(ipr_index, Ra);
2533 if (traceData) { traceData->setData(Ra); }