3 ////////////////////////////////////////////////////////////////////
5 // Alpha ISA description file.
7 ////////////////////////////////////////////////////////////////////
10 ////////////////////////////////////////////////////////////////////
12 // Output include file directives.
20 #include "cpu/static_inst.hh"
21 #include "mem/mem_req.hh" // some constructors use MemReq flags
25 #include "base/cprintf.hh"
26 #include "base/loader/symtab.hh"
27 #include "cpu/exec_context.hh" // for Jump::branchTarget()
42 #include "arch/alpha/pseudo_inst.hh"
44 #include "cpu/base_cpu.hh"
45 #include "cpu/exetrace.hh"
46 #include "sim/sim_exit.hh"
49 ////////////////////////////////////////////////////////////////////
51 // Namespace statement. Everything below this line will be in the
52 // AlphaISAInst namespace.
58 ////////////////////////////////////////////////////////////////////
60 // Bitfield definitions.
63 // Universal (format-independent) fields
64 def bitfield OPCODE <31:26>;
65 def bitfield RA <25:21>;
66 def bitfield RB <20:16>;
69 def signed bitfield MEMDISP <15: 0>; // displacement
70 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
72 // Memory-format jumps
73 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
74 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
77 def signed bitfield BRDISP <20: 0>; // displacement
79 // Integer operate format(s>;
80 def bitfield INTIMM <20:13>; // integer immediate (literal)
81 def bitfield IMM <12:12>; // immediate flag
82 def bitfield INTFUNC <11: 5>; // function code
83 def bitfield RC < 4: 0>; // dest reg
85 // Floating-point operate format
86 def bitfield FA <25:21>;
87 def bitfield FB <20:16>;
88 def bitfield FP_FULLFUNC <15: 5>; // complete function code
89 def bitfield FP_TRAPMODE <15:13>; // trapping mode
90 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
91 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
92 def bitfield FP_SRCTYPE <10: 9>; // source reg type
93 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
94 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
95 def bitfield FC < 4: 0>; // dest reg
98 def bitfield PALFUNC <25: 0>; // function code
100 // EV5 PAL instructions:
102 def bitfield HW_LDST_PHYS <15>; // address is physical
103 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
104 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
105 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
106 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
107 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
108 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
109 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
112 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
113 def bitfield HW_REI_MBZ <13: 0>; // must be zero
116 def bitfield HW_IPR_IDX <15:0>; // IPR index
119 def bitfield M5FUNC <7:0>;
122 'sb' : ('signed int', 8),
123 'ub' : ('unsigned int', 8),
124 'sw' : ('signed int', 16),
125 'uw' : ('unsigned int', 16),
126 'sl' : ('signed int', 32),
127 'ul' : ('unsigned int', 32),
128 'sq' : ('signed int', 64),
129 'uq' : ('unsigned int', 64),
130 'sf' : ('float', 32),
135 # Int regs default to unsigned, but code should not count on this.
136 # For clarity, descriptions that depend on unsigned behavior should
137 # explicitly specify '.uq'.
138 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
139 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
140 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
141 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
142 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
143 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
144 'Mem': MemOperandTraits('uq', None,
145 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
146 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
147 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
148 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
149 # The next two are hacks for non-full-system call-pal emulation
150 'R0': IntRegOperandTraits('uq', '0', None, 1),
151 'R16': IntRegOperandTraits('uq', '16', None, 1)
154 ////////////////////////////////////////////////////////////////////
156 // Basic instruction classes/templates/formats etc.
160 // uncomment the following to get SimpleScalar-compatible disassembly
161 // (useful for diffing output traces).
162 // #define SS_COMPATIBLE_DISASSEMBLY
165 * Base class for all Alpha static instructions.
167 class AlphaStaticInst : public StaticInst<AlphaISA>
171 /// Make AlphaISA register dependence tags directly visible in
172 /// this class and derived classes. Maybe these should really
173 /// live here and not in the AlphaISA namespace.
174 enum DependenceTags {
175 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
176 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
177 Uniq_DepTag = AlphaISA::Uniq_DepTag,
178 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
182 AlphaStaticInst(const char *mnem, MachInst _machInst,
184 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
188 /// Print a register name for disassembly given the unique
189 /// dependence tag number (FP or int).
190 void printReg(std::ostream &os, int reg) const;
193 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
199 AlphaStaticInst::printReg(std::ostream &os, int reg) const
201 if (reg < FP_Base_DepTag) {
202 ccprintf(os, "r%d", reg);
205 ccprintf(os, "f%d", reg - FP_Base_DepTag);
210 AlphaStaticInst::generateDisassembly(Addr pc,
211 const SymbolTable *symtab) const
213 std::stringstream ss;
215 ccprintf(ss, "%-10s ", mnemonic);
217 // just print the first two source regs... if there's
218 // a third one, it's a read-modify-write dest (Rc),
220 if (_numSrcRegs > 0) {
221 printReg(ss, _srcRegIdx[0]);
223 if (_numSrcRegs > 1) {
225 printReg(ss, _srcRegIdx[1]);
228 // just print the first dest... if there's a second one,
229 // it's generally implicit
230 if (_numDestRegs > 0) {
233 printReg(ss, _destRegIdx[0]);
240 // Declarations for execute() methods.
241 def template BasicExecDeclare {{
242 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
245 // Basic instruction class declaration template.
246 def template BasicDeclare {{
248 * Static instruction class for "%(mnemonic)s".
250 class %(class_name)s : public %(base_class)s
254 %(class_name)s(MachInst machInst);
260 // Basic instruction class constructor template.
261 def template BasicConstructor {{
262 inline %(class_name)s::%(class_name)s(MachInst machInst)
263 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
269 // Basic instruction class execute method template.
270 def template BasicExecute {{
271 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
272 Trace::InstRecord *traceData) const
274 Fault fault = No_Fault;
281 if (fault == No_Fault) {
289 // Basic decode template.
290 def template BasicDecode {{
291 return new %(class_name)s(machInst);
294 // Basic decode template, passing mnemonic in as string arg to constructor.
295 def template BasicDecodeWithMnemonic {{
296 return new %(class_name)s("%(mnemonic)s", machInst);
299 // The most basic instruction format... used only for a few misc. insts
300 def format BasicOperate(code, *flags) {{
301 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
302 header_output = BasicDeclare.subst(iop)
303 decoder_output = BasicConstructor.subst(iop)
304 decode_block = BasicDecode.subst(iop)
305 exec_output = BasicExecute.subst(iop)
310 ////////////////////////////////////////////////////////////////////
317 * Static instruction class for no-ops. This is a leaf class.
319 class Nop : public AlphaStaticInst
321 /// Disassembly of original instruction.
322 const std::string originalDisassembly;
326 Nop(const std::string _originalDisassembly, MachInst _machInst)
327 : AlphaStaticInst("nop", _machInst, No_OpClass),
328 originalDisassembly(_originalDisassembly)
336 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
343 std::string Nop::generateDisassembly(Addr pc,
344 const SymbolTable *symtab) const
346 #ifdef SS_COMPATIBLE_DISASSEMBLY
347 return originalDisassembly;
349 return csprintf("%-10s (%s)", "nop", originalDisassembly);
353 /// Helper function for decoding nops. Substitute Nop object
354 /// for original inst passed in as arg (and delete latter).
357 makeNop(AlphaStaticInst *inst)
359 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
367 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
373 // integer & FP operate instructions use Rc as dest, so check for
374 // Rc == 31 to detect nops
375 def template OperateNopCheckDecode {{
377 AlphaStaticInst *i = new %(class_name)s(machInst);
385 // Like BasicOperate format, but generates NOP if RC/FC == 31
386 def format BasicOperateWithNopCheck(code, *opt_args) {{
387 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
389 header_output = BasicDeclare.subst(iop)
390 decoder_output = BasicConstructor.subst(iop)
391 decode_block = OperateNopCheckDecode.subst(iop)
392 exec_output = BasicExecute.subst(iop)
396 ////////////////////////////////////////////////////////////////////
398 // Integer operate instructions
403 * Base class for integer immediate instructions.
405 class IntegerImm : public AlphaStaticInst
408 /// Immediate operand value (unsigned 8-bit int).
412 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
413 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
418 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
424 IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
426 std::stringstream ss;
428 ccprintf(ss, "%-10s ", mnemonic);
430 // just print the first source reg... if there's
431 // a second one, it's a read-modify-write dest (Rc),
433 if (_numSrcRegs > 0) {
434 printReg(ss, _srcRegIdx[0]);
440 if (_numDestRegs > 0) {
442 printReg(ss, _destRegIdx[0]);
450 def template RegOrImmDecode {{
453 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
454 : (AlphaStaticInst *)new %(class_name)s(machInst);
462 // Primary format for integer operate instructions:
463 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
464 // - Generates NOP if RC == 31.
465 def format IntegerOperate(code, *opt_flags) {{
466 # If the code block contains 'Rb_or_imm', we define two instructions,
467 # one using 'Rb' and one using 'imm', and have the decoder select
469 uses_imm = (code.find('Rb_or_imm') != -1)
472 # base code is reg version:
473 # rewrite by substituting 'Rb' for 'Rb_or_imm'
474 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
475 # generate immediate version by substituting 'imm'
476 # note that imm takes no extenstion, so we extend
477 # the regexp to replace any extension as well
478 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
480 # generate declaration for register version
481 cblk = CodeBlock(code)
482 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
483 header_output = BasicDeclare.subst(iop)
484 decoder_output = BasicConstructor.subst(iop)
485 exec_output = BasicExecute.subst(iop)
488 # append declaration for imm version
489 imm_cblk = CodeBlock(imm_code)
490 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
492 header_output += BasicDeclare.subst(imm_iop)
493 decoder_output += BasicConstructor.subst(imm_iop)
494 exec_output += BasicExecute.subst(imm_iop)
495 # decode checks IMM bit to pick correct version
496 decode_block = RegOrImmDecode.subst(iop)
498 # no imm version: just check for nop
499 decode_block = OperateNopCheckDecode.subst(iop)
503 ////////////////////////////////////////////////////////////////////
505 // Floating-point instructions
507 // Note that many FP-type instructions which do not support all the
508 // various rounding & trapping modes use the simpler format
509 // BasicOperateWithNopCheck.
513 /// Check "FP enabled" machine status bit. Called when executing any FP
514 /// instruction in full-system mode.
515 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
516 /// if not. Non-full-system mode: always returns No_Fault.
518 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
520 Fault fault = No_Fault; // dummy... this ipr access should not fault
521 if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
527 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
536 * Base class for general floating-point instructions. Includes
537 * support for various Alpha rounding and trapping modes. Only FP
538 * instructions that require this support are derived from this
539 * class; the rest derive directly from AlphaStaticInst.
541 class AlphaFP : public AlphaStaticInst
544 /// Alpha FP rounding modes.
546 Chopped = 0, ///< round toward zero
547 Minus_Infinity = 1, ///< round toward minus infinity
548 Normal = 2, ///< round to nearest (default)
549 Dynamic = 3, ///< use FPCR setting (in instruction)
550 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
553 /// Alpha FP trapping modes.
554 /// For instructions that produce integer results, the
555 /// "Underflow Enable" modes really mean "Overflow Enable", and
556 /// the assembly modifier is V rather than U.
558 /// default: nothing enabled
559 Imprecise = 0, ///< no modifier
560 /// underflow/overflow traps enabled, inexact disabled
561 Underflow_Imprecise = 1, ///< /U or /V
562 Underflow_Precise = 5, ///< /SU or /SV
563 /// underflow/overflow and inexact traps enabled
564 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
569 static const int alphaToC99RoundingMode[];
572 /// Map enum RoundingMode values to disassembly suffixes.
573 static const char *roundingModeSuffix[];
574 /// Map enum TrappingMode values to FP disassembly suffixes.
575 static const char *fpTrappingModeSuffix[];
576 /// Map enum TrappingMode values to integer disassembly suffixes.
577 static const char *intTrappingModeSuffix[];
579 /// This instruction's rounding mode.
580 RoundingMode roundingMode;
581 /// This instruction's trapping mode.
582 TrappingMode trappingMode;
585 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
586 : AlphaStaticInst(mnem, _machInst, __opClass),
587 roundingMode((enum RoundingMode)FP_ROUNDMODE),
588 trappingMode((enum TrappingMode)FP_TRAPMODE)
590 if (trappingMode != Imprecise) {
591 warn("precise FP traps unimplemented\n");
596 int getC99RoundingMode(uint64_t fpcr_val) const;
599 // This differs from the AlphaStaticInst version only in
600 // printing suffixes for non-default rounding & trapping modes.
602 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
608 def template FloatingPointDecode {{
610 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
611 && FP_ROUNDMODE == AlphaFP::Normal);
613 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
614 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
627 AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
629 if (roundingMode == Dynamic) {
630 return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
633 return alphaToC99RoundingMode[roundingMode];
639 AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
641 std::string mnem_str(mnemonic);
643 #ifndef SS_COMPATIBLE_DISASSEMBLY
644 std::string suffix("");
645 suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
646 ? fpTrappingModeSuffix[trappingMode]
647 : intTrappingModeSuffix[trappingMode]);
648 suffix += roundingModeSuffix[roundingMode];
651 mnem_str = csprintf("%s/%s", mnemonic, suffix);
655 std::stringstream ss;
656 ccprintf(ss, "%-10s ", mnem_str.c_str());
658 // just print the first two source regs... if there's
659 // a third one, it's a read-modify-write dest (Rc),
661 if (_numSrcRegs > 0) {
662 printReg(ss, _srcRegIdx[0]);
664 if (_numSrcRegs > 1) {
666 printReg(ss, _srcRegIdx[1]);
669 // just print the first dest... if there's a second one,
670 // it's generally implicit
671 if (_numDestRegs > 0) {
674 printReg(ss, _destRegIdx[0]);
681 const int AlphaFP::alphaToC99RoundingMode[] = {
682 FE_TOWARDZERO, // Chopped
683 FE_DOWNWARD, // Minus_Infinity
684 FE_TONEAREST, // Normal
685 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
689 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
690 // mark invalid trapping modes, but don't fail on them, because
691 // you could decode anything on a misspeculated path
692 const char *AlphaFP::fpTrappingModeSuffix[] =
693 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
694 const char *AlphaFP::intTrappingModeSuffix[] =
695 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
698 // General format for floating-point operate instructions:
699 // - Checks trapping and rounding mode flags. Trapping modes
700 // currently unimplemented (will fail).
701 // - Generates NOP if FC == 31.
702 def format FloatingPointOperate(code, *opt_args) {{
703 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
704 decode_block = FloatingPointDecode.subst(iop)
706 fast_iop = InstObjParams(name, Name + 'Fast', 'AlphaFP',
707 CodeBlock(code), opt_args)
708 header_output = BasicDeclare.subst(fast_iop)
709 decoder_output = BasicConstructor.subst(fast_iop)
710 exec_output = BasicExecute.subst(fast_iop)
712 gen_code_prefix = r'''
714 fesetround(getC99RoundingMode(xc->readFpcr()));
717 gen_code_suffix = r'''
719 fesetround(FE_TONEAREST);
723 gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
724 CodeBlock(gen_code_prefix + code + gen_code_suffix), opt_args)
725 header_output += BasicDeclare.subst(gen_iop)
726 decoder_output += BasicConstructor.subst(gen_iop)
727 exec_output += BasicExecute.subst(gen_iop)
731 ////////////////////////////////////////////////////////////////////
733 // Memory-format instructions: LoadAddress, Load, Store
738 * Base class for general Alpha memory-format instructions.
740 class Memory : public AlphaStaticInst
744 /// Memory request flags. See mem_req_base.hh.
745 unsigned memAccessFlags;
746 /// Pointer to EAComp object.
747 StaticInstPtr<AlphaISA> eaCompPtr;
748 /// Pointer to MemAcc object.
749 StaticInstPtr<AlphaISA> memAccPtr;
752 Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
753 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
754 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
755 : AlphaStaticInst(mnem, _machInst, __opClass),
756 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
761 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
765 StaticInstPtr<AlphaISA> &eaCompInst() { return eaCompPtr; }
766 StaticInstPtr<AlphaISA> &memAccInst() { return memAccPtr; }
770 * Base class for memory-format instructions using a 32-bit
771 * displacement (i.e. most of them).
773 class MemoryDisp32 : public Memory
776 /// Displacement for EA calculation (signed).
780 MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
781 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
782 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
783 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
791 * Base class for a few miscellaneous memory-format insts
792 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
793 * None of these instructions has a destination register either.
795 class MemoryNoDisp : public Memory
799 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
800 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
801 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
802 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
807 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
814 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
816 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
817 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
821 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
823 return csprintf("%-10s (r%d)", mnemonic, RB);
827 def format LoadAddress(code) {{
828 iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
829 header_output = BasicDeclare.subst(iop)
830 decoder_output = BasicConstructor.subst(iop)
831 decode_block = BasicDecode.subst(iop)
832 exec_output = BasicExecute.subst(iop)
836 def template LoadStoreDeclare {{
838 * Static instruction class for "%(mnemonic)s".
840 class %(class_name)s : public %(base_class)s
845 * "Fake" effective address computation class for "%(mnemonic)s".
847 class EAComp : public %(base_class)s
851 EAComp(MachInst machInst);
857 * "Fake" memory access instruction class for "%(mnemonic)s".
859 class MemAcc : public %(base_class)s
863 MemAcc(MachInst machInst);
871 %(class_name)s(MachInst machInst);
877 def template LoadStoreConstructor {{
878 /** TODO: change op_class to AddrGenOp or something (requires
879 * creating new member of OpClass enum in op_class.hh, updating
880 * config files, etc.). */
881 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
882 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
887 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
888 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
890 %(memacc_constructor)s;
893 inline %(class_name)s::%(class_name)s(MachInst machInst)
894 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
895 new EAComp(machInst), new MemAcc(machInst))
902 def template EACompExecute {{
904 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
905 Trace::InstRecord *traceData) const
908 Fault fault = No_Fault;
915 if (fault == No_Fault) {
924 def template MemAccExecute {{
926 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
927 Trace::InstRecord *traceData) const
930 Fault fault = No_Fault;
937 if (fault == No_Fault) {
942 if (fault == No_Fault) {
946 if (fault == No_Fault) {
950 if (fault == No_Fault) {
959 def template LoadStoreExecute {{
960 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
961 Trace::InstRecord *traceData) const
964 Fault fault = No_Fault;
971 if (fault == No_Fault) {
976 if (fault == No_Fault) {
980 if (fault == No_Fault) {
984 if (fault == No_Fault) {
993 def template PrefetchExecute {{
994 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
995 Trace::InstRecord *traceData) const
998 Fault fault = No_Fault;
1000 %(fp_enable_check)s;
1005 if (fault == No_Fault) {
1006 xc->prefetch(EA, memAccessFlags);
1013 // load instructions use Ra as dest, so check for
1014 // Ra == 31 to detect nops
1015 def template LoadNopCheckDecode {{
1017 AlphaStaticInst *i = new %(class_name)s(machInst);
1026 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1027 def template LoadPrefetchCheckDecode {{
1030 return new %(class_name)s(machInst);
1033 return new %(class_name)sPrefetch(machInst);
1040 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1041 base_class = 'MemoryDisp32', flags = [],
1042 decode_template = BasicDecode,
1043 exec_template = LoadStoreExecute):
1044 # Segregate flags into instruction flags (handled by InstObjParams)
1045 # and memory access flags (handled here).
1047 # Would be nice to autogenerate this list, but oh well.
1048 valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1049 mem_flags = [f for f in flags if f in valid_mem_flags]
1050 inst_flags = [f for f in flags if f not in valid_mem_flags]
1052 # add hook to get effective addresses into execution trace output.
1053 ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
1055 # generate code block objects
1056 ea_cblk = CodeBlock(ea_code)
1057 memacc_cblk = CodeBlock(memacc_code)
1058 postacc_cblk = CodeBlock(postacc_code)
1060 # Some CPU models execute the memory operation as an atomic unit,
1061 # while others want to separate them into an effective address
1062 # computation and a memory access operation. As a result, we need
1063 # to generate three StaticInst objects. Note that the latter two
1064 # are nested inside the larger "atomic" one.
1066 # generate InstObjParams for EAComp object
1067 ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
1069 # generate InstObjParams for MemAcc object
1070 memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
1071 # in the split execution model, the MemAcc portion is responsible
1072 # for the post-access code.
1073 memacc_iop.postacc_code = postacc_cblk.code
1075 # generate InstObjParams for unified execution
1076 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1077 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1079 iop.ea_constructor = ea_cblk.constructor
1080 iop.ea_code = ea_cblk.code
1081 iop.memacc_constructor = memacc_cblk.constructor
1082 iop.memacc_code = memacc_cblk.code
1083 iop.postacc_code = postacc_cblk.code
1086 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
1087 iop.constructor += s
1088 memacc_iop.constructor += s
1090 # (header_output, decoder_output, decode_block, exec_output)
1091 return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
1092 decode_template.subst(iop),
1093 EACompExecute.subst(ea_iop)
1094 + MemAccExecute.subst(memacc_iop)
1095 + exec_template.subst(iop))
1099 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1100 (header_output, decoder_output, decode_block, exec_output) = \
1101 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1102 decode_template = LoadNopCheckDecode)
1106 // Note that the flags passed in apply only to the prefetch version
1107 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1108 # declare the load instruction object and generate the decode block
1109 (header_output, decoder_output, decode_block, exec_output) = \
1110 LoadStoreBase(name, Name, ea_code, memacc_code,
1111 decode_template = LoadPrefetchCheckDecode)
1113 # Declare the prefetch instruction object.
1115 # convert flags from tuple to list to make them mutable
1116 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
1118 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
1119 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1120 flags = pf_flags, exec_template = PrefetchExecute)
1122 header_output += pf_header_output
1123 decoder_output += pf_decoder_output
1124 exec_output += pf_exec_output
1128 def format Store(ea_code, memacc_code, *flags) {{
1129 (header_output, decoder_output, decode_block, exec_output) = \
1130 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags)
1134 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1135 (header_output, decoder_output, decode_block, exec_output) = \
1136 LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1141 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1142 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1143 (header_output, decoder_output, decode_block, exec_output) = \
1144 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1145 base_class = 'MemoryNoDisp')
1149 ////////////////////////////////////////////////////////////////////
1151 // Control transfer instructions
1157 * Base class for instructions whose disassembly is not purely a
1158 * function of the machine instruction (i.e., it depends on the
1159 * PC). This class overrides the disassemble() method to check
1160 * the PC and symbol table values before re-using a cached
1161 * disassembly string. This is necessary for branches and jumps,
1162 * where the disassembly string includes the target address (which
1163 * may depend on the PC and/or symbol table).
1165 class PCDependentDisassembly : public AlphaStaticInst
1168 /// Cached program counter from last disassembly
1169 mutable Addr cachedPC;
1170 /// Cached symbol table pointer from last disassembly
1171 mutable const SymbolTable *cachedSymtab;
1174 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1176 : AlphaStaticInst(mnem, _machInst, __opClass),
1177 cachedPC(0), cachedSymtab(0)
1182 disassemble(Addr pc, const SymbolTable *symtab) const;
1186 * Base class for branches (PC-relative control transfers),
1187 * conditional or unconditional.
1189 class Branch : public PCDependentDisassembly
1192 /// Displacement to target address (signed).
1196 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1197 : PCDependentDisassembly(mnem, _machInst, __opClass),
1202 Addr branchTarget(Addr branchPC) const;
1205 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1209 * Base class for jumps (register-indirect control transfers). In
1210 * the Alpha ISA, these are always unconditional.
1212 class Jump : public PCDependentDisassembly
1216 /// Displacement to target address (signed).
1221 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1222 : PCDependentDisassembly(mnem, _machInst, __opClass),
1227 Addr branchTarget(ExecContext *xc) const;
1230 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1236 Branch::branchTarget(Addr branchPC) const
1238 return branchPC + 4 + disp;
1242 Jump::branchTarget(ExecContext *xc) const
1244 Addr NPC = xc->readPC() + 4;
1245 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
1246 return (Rb & ~3) | (NPC & 1);
1250 PCDependentDisassembly::disassemble(Addr pc,
1251 const SymbolTable *symtab) const
1253 if (!cachedDisassembly ||
1254 pc != cachedPC || symtab != cachedSymtab)
1256 if (cachedDisassembly)
1257 delete cachedDisassembly;
1260 new std::string(generateDisassembly(pc, symtab));
1262 cachedSymtab = symtab;
1265 return *cachedDisassembly;
1269 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1271 std::stringstream ss;
1273 ccprintf(ss, "%-10s ", mnemonic);
1275 // There's only one register arg (RA), but it could be
1276 // either a source (the condition for conditional
1277 // branches) or a destination (the link reg for
1278 // unconditional branches)
1279 if (_numSrcRegs > 0) {
1280 printReg(ss, _srcRegIdx[0]);
1283 else if (_numDestRegs > 0) {
1284 printReg(ss, _destRegIdx[0]);
1288 #ifdef SS_COMPATIBLE_DISASSEMBLY
1289 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1295 Addr target = pc + 4 + disp;
1298 if (symtab && symtab->findSymbol(target, str))
1301 ccprintf(ss, "0x%x", target);
1307 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1309 std::stringstream ss;
1311 ccprintf(ss, "%-10s ", mnemonic);
1313 #ifdef SS_COMPATIBLE_DISASSEMBLY
1314 if (_numDestRegs == 0) {
1320 if (_numDestRegs > 0) {
1321 printReg(ss, _destRegIdx[0]);
1325 ccprintf(ss, "(r%d)", RB);
1331 def template JumpOrBranchDecode {{
1333 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1334 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1337 def format CondBranch(code) {{
1338 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1339 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1340 ('IsDirectControl', 'IsCondControl'))
1341 header_output = BasicDeclare.subst(iop)
1342 decoder_output = BasicConstructor.subst(iop)
1343 decode_block = BasicDecode.subst(iop)
1344 exec_output = BasicExecute.subst(iop)
1348 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1349 # Declare basic control transfer w/o link (i.e. link reg is R31)
1350 nolink_code = 'NPC = %s;\n' % npc_expr
1351 nolink_iop = InstObjParams(name, Name, base_class,
1352 CodeBlock(nolink_code), flags)
1353 header_output = BasicDeclare.subst(nolink_iop)
1354 decoder_output = BasicConstructor.subst(nolink_iop)
1355 exec_output = BasicExecute.subst(nolink_iop)
1357 # Generate declaration of '*AndLink' version, append to decls
1358 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1359 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1360 CodeBlock(link_code), flags)
1361 header_output += BasicDeclare.subst(link_iop)
1362 decoder_output += BasicConstructor.subst(link_iop)
1363 exec_output += BasicExecute.subst(link_iop)
1365 # need to use link_iop for the decode template since it is expecting
1366 # the shorter version of class_name (w/o "AndLink")
1368 return (header_output, decoder_output,
1369 JumpOrBranchDecode.subst(nolink_iop), exec_output)
1372 def format UncondBranch(*flags) {{
1373 flags += ('IsUncondControl', 'IsDirectControl')
1374 (header_output, decoder_output, decode_block, exec_output) = \
1375 UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1378 def format Jump(*flags) {{
1379 flags += ('IsUncondControl', 'IsIndirectControl')
1380 (header_output, decoder_output, decode_block, exec_output) = \
1381 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1385 ////////////////////////////////////////////////////////////////////
1392 * Base class for emulated call_pal calls (used only in
1393 * non-full-system mode).
1395 class EmulatedCallPal : public AlphaStaticInst
1400 EmulatedCallPal(const char *mnem, MachInst _machInst,
1402 : AlphaStaticInst(mnem, _machInst, __opClass)
1407 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1413 EmulatedCallPal::generateDisassembly(Addr pc,
1414 const SymbolTable *symtab) const
1416 #ifdef SS_COMPATIBLE_DISASSEMBLY
1417 return csprintf("%s %s", "call_pal", mnemonic);
1419 return csprintf("%-10s %s", "call_pal", mnemonic);
1424 def format EmulatedCallPal(code, *flags) {{
1425 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
1426 header_output = BasicDeclare.subst(iop)
1427 decoder_output = BasicConstructor.subst(iop)
1428 decode_block = BasicDecode.subst(iop)
1429 exec_output = BasicExecute.subst(iop)
1434 * Base class for full-system-mode call_pal instructions.
1435 * Probably could turn this into a leaf class and get rid of the
1438 class CallPalBase : public AlphaStaticInst
1441 int palFunc; ///< Function code part of instruction
1442 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1443 bool palValid; ///< is the function code valid?
1444 bool palPriv; ///< is this call privileged?
1447 CallPalBase(const char *mnem, MachInst _machInst,
1451 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1457 CallPalBase::CallPalBase(const char *mnem, MachInst _machInst,
1459 : AlphaStaticInst(mnem, _machInst, __opClass),
1462 // From the 21164 HRM (paraphrased):
1463 // Bit 7 of the function code (mask 0x80) indicates
1464 // whether the call is privileged (bit 7 == 0) or
1465 // unprivileged (bit 7 == 1). The privileged call table
1466 // starts at 0x2000, the unprivielged call table starts at
1467 // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
1469 const int palPrivMask = 0x80;
1470 const int palOffsetMask = 0x3f;
1472 // Pal call is invalid unless all other bits are 0
1473 palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
1474 palPriv = ((machInst & palPrivMask) == 0);
1475 int shortPalFunc = (machInst & palOffsetMask);
1476 // Add 1 to base to set pal-mode bit
1477 palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
1481 CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1483 return csprintf("%-10s %#x", "call_pal", palFunc);
1487 def format CallPal(code, *flags) {{
1488 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
1489 header_output = BasicDeclare.subst(iop)
1490 decoder_output = BasicConstructor.subst(iop)
1491 decode_block = BasicDecode.subst(iop)
1492 exec_output = BasicExecute.subst(iop)
1495 ////////////////////////////////////////////////////////////////////
1502 * Base class for hw_ld and hw_st.
1504 class HwLoadStore : public Memory
1508 /// Displacement for EA calculation (signed).
1512 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
1513 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
1514 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
1517 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1524 HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
1526 StaticInstPtr<AlphaISA> _eaCompPtr,
1527 StaticInstPtr<AlphaISA> _memAccPtr)
1528 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
1532 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1533 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1534 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1535 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1539 HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1541 #ifdef SS_COMPATIBLE_DISASSEMBLY
1542 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1544 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1545 const char *lock_str =
1546 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1548 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1549 mnemonic, RA, disp, RB,
1550 HW_LDST_PHYS ? ",PHYS" : "",
1551 HW_LDST_ALT ? ",ALT" : "",
1552 HW_LDST_QUAD ? ",QUAD" : "",
1553 HW_LDST_VPTE ? ",VPTE" : "",
1559 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1560 (header_output, decoder_output, decode_block, exec_output) = \
1561 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1562 flags = flags, base_class = 'HwLoadStore')
1566 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1567 (header_output, decoder_output, decode_block, exec_output) = \
1568 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1569 postacc_code, flags = flags, base_class = 'HwLoadStore')
1575 * Base class for hw_mfpr and hw_mtpr.
1577 class HwMoveIPR : public AlphaStaticInst
1580 /// Index of internal processor register.
1584 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1585 : AlphaStaticInst(mnem, _machInst, __opClass),
1586 ipr_index(HW_IPR_IDX)
1591 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1597 HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1599 if (_numSrcRegs > 0) {
1601 return csprintf("%-10s r%d,IPR(%#x)",
1602 mnemonic, RA, ipr_index);
1606 return csprintf("%-10s IPR(%#x),r%d",
1607 mnemonic, ipr_index, RA);
1612 def format HwMoveIPR(code) {{
1613 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
1615 header_output = BasicDeclare.subst(iop)
1616 decoder_output = BasicConstructor.subst(iop)
1617 decode_block = BasicDecode.subst(iop)
1618 exec_output = BasicExecute.subst(iop)
1622 ////////////////////////////////////////////////////////////////////
1624 // Unimplemented instructions
1629 * Static instruction class for unimplemented instructions that
1630 * cause simulator termination. Note that these are recognized
1631 * (legal) instructions that the simulator does not support; the
1632 * 'Unknown' class is used for unrecognized/illegal instructions.
1633 * This is a leaf class.
1635 class FailUnimplemented : public AlphaStaticInst
1639 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1640 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1642 // don't call execute() (which panics) if we're on a
1644 flags[IsNonSpeculative] = true;
1647 %(BasicExecDeclare)s
1650 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1654 * Base class for unimplemented instructions that cause a warning
1655 * to be printed (but do not terminate simulation). This
1656 * implementation is a little screwy in that it will print a
1657 * warning for each instance of a particular unimplemented machine
1658 * instruction, not just for each unimplemented opcode. Should
1659 * probably make the 'warned' flag a static member of the derived
1662 class WarnUnimplemented : public AlphaStaticInst
1665 /// Have we warned on this instruction yet?
1666 mutable bool warned;
1670 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1671 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1673 // don't call execute() (which panics) if we're on a
1675 flags[IsNonSpeculative] = true;
1678 %(BasicExecDeclare)s
1681 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1687 FailUnimplemented::generateDisassembly(Addr pc,
1688 const SymbolTable *symtab) const
1690 return csprintf("%-10s (unimplemented)", mnemonic);
1694 WarnUnimplemented::generateDisassembly(Addr pc,
1695 const SymbolTable *symtab) const
1697 #ifdef SS_COMPATIBLE_DISASSEMBLY
1698 return csprintf("%-10s", mnemonic);
1700 return csprintf("%-10s (unimplemented)", mnemonic);
1707 FailUnimplemented::execute(%(CPU_exec_context)s *xc,
1708 Trace::InstRecord *traceData) const
1710 panic("attempt to execute unimplemented instruction '%s' "
1711 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1712 return Unimplemented_Opcode_Fault;
1716 WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
1717 Trace::InstRecord *traceData) const
1720 warn("instruction '%s' unimplemented\n", mnemonic);
1729 def format FailUnimpl() {{
1730 iop = InstObjParams(name, 'FailUnimplemented')
1731 decode_block = BasicDecodeWithMnemonic.subst(iop)
1734 def format WarnUnimpl() {{
1735 iop = InstObjParams(name, 'WarnUnimplemented')
1736 decode_block = BasicDecodeWithMnemonic.subst(iop)
1741 * Static instruction class for unknown (illegal) instructions.
1742 * These cause simulator termination if they are executed in a
1743 * non-speculative mode. This is a leaf class.
1745 class Unknown : public AlphaStaticInst
1749 Unknown(MachInst _machInst)
1750 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1752 // don't call execute() (which panics) if we're on a
1754 flags[IsNonSpeculative] = true;
1757 %(BasicExecDeclare)s
1760 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1764 ////////////////////////////////////////////////////////////////////
1766 // Unknown instructions
1771 Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1773 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1774 "unknown", machInst, OPCODE);
1780 Unknown::execute(%(CPU_exec_context)s *xc,
1781 Trace::InstRecord *traceData) const
1783 panic("attempt to execute unknown instruction "
1784 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1785 return Unimplemented_Opcode_Fault;
1789 def format Unknown() {{
1790 decode_block = 'return new Unknown(machInst);\n'
1793 ////////////////////////////////////////////////////////////////////
1795 // Utility functions for execute methods
1800 /// Return opa + opb, summing carry into third arg.
1802 addc(uint64_t opa, uint64_t opb, int &carry)
1804 uint64_t res = opa + opb;
1805 if (res < opa || res < opb)
1810 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1811 /// product in res_hi and res_lo.
1813 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1815 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1816 uint64_t opa_hi = opa<63:32>;
1817 uint64_t opa_lo = opa<31:0>;
1818 uint64_t opb_hi = opb<63:32>;
1819 uint64_t opb_lo = opb<31:0>;
1821 res_lo = opa_lo * opb_lo;
1823 // The middle partial products logically belong in bit
1824 // positions 95 to 32. Thus the lower 32 bits of each product
1825 // sum into the upper 32 bits of the low result, while the
1826 // upper 32 sum into the low 32 bits of the upper result.
1827 uint64_t partial1 = opa_hi * opb_lo;
1828 uint64_t partial2 = opa_lo * opb_hi;
1830 uint64_t partial1_lo = partial1<31:0> << 32;
1831 uint64_t partial1_hi = partial1<63:32>;
1832 uint64_t partial2_lo = partial2<31:0> << 32;
1833 uint64_t partial2_hi = partial2<63:32>;
1835 // Add partial1_lo and partial2_lo to res_lo, keeping track
1836 // of any carries out
1838 res_lo = addc(partial1_lo, res_lo, carry_out);
1839 res_lo = addc(partial2_lo, res_lo, carry_out);
1841 // Now calculate the high 64 bits...
1842 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1845 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1846 /// See Table 2-2 of Alpha AHB.
1850 int hibit = old_exp<7:>;
1851 int lobits = old_exp<6:0>;
1854 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1857 return (lobits == 0) ? 0 : (0x380 | lobits);
1861 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1862 /// representation to be stored in an FP reg.
1864 s_to_t(uint32_t s_val)
1866 uint64_t tmp = s_val;
1867 return (tmp<31:> << 63 // sign bit
1868 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1869 | tmp<22:0> << 29); // fraction
1872 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1873 /// S-floating representation to be stored in memory.
1875 t_to_s(uint64_t t_val)
1877 return (t_val<63:62> << 30 // sign bit & hi exp bit
1878 | t_val<58:29>); // rest of exp & fraction
1882 ////////////////////////////////////////////////////////////////////
1884 // The actual decoder specification
1887 decode OPCODE default Unknown::unknown() {
1889 format LoadAddress {
1890 0x08: lda({{ Ra = Rb + disp; }});
1891 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1895 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1896 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1897 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1898 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1899 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1900 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1901 0x20: copy_load({{EA = Ra;}},
1902 {{fault = xc->copySrcTranslate(EA);}},
1903 IsMemRef, IsLoad, IsCopy);
1906 format LoadOrPrefetch {
1907 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1908 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1909 // IsFloating flag on lds gets the prefetch to disassemble
1910 // using f31 instead of r31... funcitonally it's unnecessary
1911 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1912 PF_EXCLUSIVE, IsFloating);
1916 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1917 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1918 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1919 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1920 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1921 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1922 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1923 0x24: copy_store({{EA = Rb;}},
1924 {{fault = xc->copy(EA);}},
1925 IsMemRef, IsStore, IsCopy);
1929 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1931 uint64_t tmp = Mem_write_result;
1933 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1935 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1937 uint64_t tmp = Mem_write_result;
1938 // If the write operation returns 0 or 1, then
1939 // this was a conventional store conditional,
1940 // and the value indicates the success/failure
1941 // of the operation. If another value is
1942 // returned, then this was a Turbolaser
1943 // mailbox access, and we don't update the
1944 // result register at all.
1945 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1949 format IntegerOperate {
1951 0x10: decode INTFUNC { // integer arithmetic operations
1953 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1955 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1956 // signed overflow occurs when operands have same sign
1957 // and sign of result does not match.
1958 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1959 fault = Integer_Overflow_Fault;
1962 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1963 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1965 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1967 uint64_t tmp = Ra + Rb_or_imm;
1968 // signed overflow occurs when operands have same sign
1969 // and sign of result does not match.
1970 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1971 fault = Integer_Overflow_Fault;
1974 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1975 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1977 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1979 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1980 // signed overflow detection is same as for add,
1981 // except we need to look at the *complemented*
1982 // sign bit of the subtrahend (Rb), i.e., if the initial
1983 // signs are the *same* then no overflow can occur
1984 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1985 fault = Integer_Overflow_Fault;
1988 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1989 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1991 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1993 uint64_t tmp = Ra - Rb_or_imm;
1994 // signed overflow detection is same as for add,
1995 // except we need to look at the *complemented*
1996 // sign bit of the subtrahend (Rb), i.e., if the initial
1997 // signs are the *same* then no overflow can occur
1998 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1999 fault = Integer_Overflow_Fault;
2002 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
2003 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
2005 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
2006 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
2007 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
2008 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
2009 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
2015 for (int i = 0; i < 8; ++i) {
2016 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
2024 0x11: decode INTFUNC { // integer logical operations
2026 0x00: and({{ Rc = Ra & Rb_or_imm; }});
2027 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
2028 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
2029 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
2030 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
2031 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
2033 // conditional moves
2034 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
2035 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
2036 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
2037 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
2038 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
2039 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
2040 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
2041 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
2043 // For AMASK, RA must be R31.
2045 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
2048 // For IMPLVER, RA must be R31 and the B operand
2049 // must be the immediate value 1.
2053 // return EV5 for FULL_SYSTEM and EV6 otherwise
2066 // The mysterious 11.25...
2067 0x25: WarnUnimpl::eleven25();
2071 0x12: decode INTFUNC {
2072 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2073 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2074 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2076 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2077 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2078 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2079 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2082 int bv = Rb_or_imm<2:0>;
2083 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2086 int bv = Rb_or_imm<2:0>;
2087 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2090 int bv = Rb_or_imm<2:0>;
2091 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2094 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2095 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2096 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2097 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2100 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2102 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2104 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2106 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2107 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2108 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2109 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
2112 int bv = Rb_or_imm<2:0>;
2113 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2116 int bv = Rb_or_imm<2:0>;
2117 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2120 int bv = Rb_or_imm<2:0>;
2121 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
2125 uint64_t zapmask = 0;
2126 for (int i = 0; i < 8; ++i) {
2128 zapmask |= (mask(8) << (i * 8));
2133 uint64_t zapmask = 0;
2134 for (int i = 0; i < 8; ++i) {
2136 zapmask |= (mask(8) << (i * 8));
2142 0x13: decode INTFUNC { // integer multiplies
2143 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2144 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
2147 mul128(Ra, Rb_or_imm, hi, lo);
2151 // 32-bit multiply with trap on overflow
2152 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
2153 int64_t Rbx = Rb_or_imm.sl;
2154 int64_t tmp = Rax * Rbx;
2155 // To avoid overflow, all the upper 32 bits must match
2156 // the sign bit of the lower 32. We code this as
2157 // checking the upper 33 bits for all 0s or all 1s.
2158 uint64_t sign_bits = tmp<63:31>;
2159 if (sign_bits != 0 && sign_bits != mask(33))
2160 fault = Integer_Overflow_Fault;
2164 // 64-bit multiply with trap on overflow
2166 mul128(Ra, Rb_or_imm, hi, lo);
2167 // all the upper 64 bits must match the sign bit of
2169 if (!((hi == 0 && lo<63:> == 0) ||
2170 (hi == mask(64) && lo<63:> == 1)))
2171 fault = Integer_Overflow_Fault;
2176 0x1c: decode INTFUNC {
2177 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2178 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2182 if (temp<63:32>) temp >>= 32; else count += 32;
2183 if (temp<31:16>) temp >>= 16; else count += 16;
2184 if (temp<15:8>) temp >>= 8; else count += 8;
2185 if (temp<7:4>) temp >>= 4; else count += 4;
2186 if (temp<3:2>) temp >>= 2; else count += 2;
2187 if (temp<1:1>) temp >>= 1; else count += 1;
2188 if ((temp<0:0>) != 0x1) count += 1;
2195 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
2196 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
2197 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
2198 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
2199 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
2200 if (!(temp<0:0> & ULL(0x1))) count += 1;
2221 format BasicOperateWithNopCheck {
2223 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
2226 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2233 // Conditional branches.
2235 0x39: beq({{ cond = (Ra == 0); }});
2236 0x3d: bne({{ cond = (Ra != 0); }});
2237 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2238 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2239 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2240 0x3a: blt({{ cond = (Ra.sq < 0); }});
2241 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2242 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2244 0x31: fbeq({{ cond = (Fa == 0); }});
2245 0x35: fbne({{ cond = (Fa != 0); }});
2246 0x36: fbge({{ cond = (Fa >= 0); }});
2247 0x37: fbgt({{ cond = (Fa > 0); }});
2248 0x33: fble({{ cond = (Fa <= 0); }});
2249 0x32: fblt({{ cond = (Fa < 0); }});
2252 // unconditional branches
2253 format UncondBranch {
2258 // indirect branches
2259 0x1a: decode JMPFUNC {
2264 3: jsr_coroutine(IsCall, IsReturn);
2268 // IEEE floating point
2269 0x14: decode FP_SHORTFUNC {
2270 // Integer to FP register moves must have RB == 31
2272 31: decode FP_FULLFUNC {
2273 format BasicOperateWithNopCheck {
2274 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
2275 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
2276 0x014: FailUnimpl::itoff(); // VAX-format conversion
2281 // Square root instructions must have FA == 31
2283 31: decode FP_TYPEFUNC {
2284 format FloatingPointOperate {
2285 #ifdef SS_COMPATIBLE_FP
2288 fault = Arithmetic_Fault;
2294 fault = Arithmetic_Fault;
2295 Fc.sf = sqrt(Fb.sf);
2300 fault = Arithmetic_Fault;
2307 // VAX-format sqrtf and sqrtg are not implemented
2308 0xa: FailUnimpl::sqrtfg();
2311 // IEEE floating point
2312 0x16: decode FP_SHORTFUNC_TOP2 {
2313 // The top two bits of the short function code break this space
2314 // into four groups: binary ops, compares, reserved, and conversions.
2315 // See Table 4-12 of AHB.
2316 // Most of these instructions may have various trapping and
2317 // rounding mode flags set; these are decoded in the
2318 // FloatingPointDecode template used by the
2319 // FloatingPointOperate format.
2321 // add/sub/mul/div: just decode on the short function code
2323 0: decode FP_TYPEFUNC {
2324 format FloatingPointOperate {
2325 #ifdef SS_COMPATIBLE_FP
2326 0x00: adds({{ Fc = Fa + Fb; }});
2327 0x01: subs({{ Fc = Fa - Fb; }});
2328 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
2329 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
2331 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2332 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2333 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
2334 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
2337 0x20: addt({{ Fc = Fa + Fb; }});
2338 0x21: subt({{ Fc = Fa - Fb; }});
2339 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
2340 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
2344 // Floating-point compare instructions must have the default
2345 // rounding mode, and may use the default trapping mode or
2346 // /SU. Both trapping modes are treated the same by M5; the
2347 // only difference on the real hardware (as far a I can tell)
2348 // is that without /SU you'd get an imprecise trap if you
2349 // tried to compare a NaN with something else (instead of an
2350 // "unordered" result).
2351 1: decode FP_FULLFUNC {
2352 format BasicOperateWithNopCheck {
2353 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2355 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2357 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2359 0x0a4, 0x5a4: cmptun({{ // unordered
2360 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2365 // The FP-to-integer and integer-to-FP conversion insts
2366 // require that FA be 31.
2368 31: decode FP_TYPEFUNC {
2369 format FloatingPointOperate {
2370 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2372 // The cvtts opcode is overloaded to be cvtst if the trap
2373 // mode is 2 or 6 (which are not valid otherwise)
2374 0x2c: decode FP_FULLFUNC {
2375 format BasicOperateWithNopCheck {
2376 // trap on denorm version "cvtst/s" is
2377 // simulated same as cvtst
2378 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2380 default: cvtts({{ Fc.sf = Fb; }});
2383 // The trapping mode for integer-to-FP conversions
2384 // must be /SUI or nothing; /U and /SU are not
2385 // allowed. The full set of rounding modes are
2386 // supported though.
2387 0x3c: decode FP_TRAPMODE {
2388 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2390 0x3e: decode FP_TRAPMODE {
2391 0,7: cvtqt({{ Fc = Fb.sq; }});
2399 0x17: decode FP_FULLFUNC {
2400 format BasicOperateWithNopCheck {
2402 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2405 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2408 // We treat the precise & imprecise trapping versions of
2409 // cvtql identically.
2410 0x130, 0x530: cvtqlv({{
2411 // To avoid overflow, all the upper 32 bits must match
2412 // the sign bit of the lower 32. We code this as
2413 // checking the upper 33 bits for all 0s or all 1s.
2414 uint64_t sign_bits = Fb.uq<63:31>;
2415 if (sign_bits != 0 && sign_bits != mask(33))
2416 fault = Integer_Overflow_Fault;
2417 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2420 0x020: cpys({{ // copy sign
2421 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2423 0x021: cpysn({{ // copy sign negated
2424 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2426 0x022: cpyse({{ // copy sign and exponent
2427 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2430 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2431 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2432 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2433 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2434 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2435 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2437 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2438 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2442 // miscellaneous mem-format ops
2443 0x18: decode MEMFUNC {
2450 format MiscPrefetch {
2451 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
2452 {{ xc->writeHint(EA, 64, memAccessFlags); }},
2453 IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
2457 format BasicOperate {
2460 /* Rb is a fake dependency so here is a fun way to get
2461 * the parser to understand that.
2463 Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
2470 // All of the barrier instructions below do nothing in
2471 // their execute() methods (hence the empty code blocks).
2472 // All of their functionality is hard-coded in the
2473 // pipeline based on the flags IsSerializing,
2474 // IsMemBarrier, and IsWriteBarrier. In the current
2475 // detailed CPU model, the execute() function only gets
2476 // called at fetch, so there's no way to generate pipeline
2477 // behavior at any other stage. Once we go to an
2478 // exec-in-exec CPU model we should be able to get rid of
2479 // these flags and implement this behavior via the
2480 // execute() methods.
2482 // trapb is just a barrier on integer traps, where excb is
2483 // a barrier on integer and FP traps. "EXCB is thus a
2484 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
2485 // them the same though.
2486 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
2487 0x0400: excb({{ }}, IsSerializing, No_OpClass);
2488 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
2489 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
2493 format BasicOperate {
2495 Ra = xc->readIntrFlag();
2497 }}, IsNonSpeculative);
2499 Ra = xc->readIntrFlag();
2501 }}, IsNonSpeculative);
2512 0x00: CallPal::call_pal({{
2515 && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
2516 // invalid pal function code, or attempt to do privileged
2517 // PAL call in non-kernel mode
2518 fault = Unimplemented_Opcode_Fault;
2521 // check to see if simulator wants to do something special
2522 // on this PAL call (including maybe suppress it)
2523 bool dopal = xc->simPalCheck(palFunc);
2526 AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
2527 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2528 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2531 }}, IsNonSpeculative);
2533 0x00: decode PALFUNC {
2534 format EmulatedCallPal {
2536 SimExit(curTick, "halt instruction encountered");
2537 }}, IsNonSpeculative);
2540 }}, IsNonSpeculative);
2541 // Read uniq reg into ABI return value register (r0)
2542 0x9e: rduniq({{ R0 = Runiq; }}, IsNonSpeculative);
2543 // Write uniq reg with value from ABI arg register (r16)
2544 0x9f: wruniq({{ Runiq = R16; }}, IsNonSpeculative);
2550 format HwLoadStore {
2551 0x1b: decode HW_LDST_QUAD {
2552 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2553 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2556 0x1f: decode HW_LDST_COND {
2557 0: decode HW_LDST_QUAD {
2558 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2559 {{ Mem.ul = Ra<31:0>; }}, L);
2560 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2561 {{ Mem.uq = Ra.uq; }}, Q);
2564 1: FailUnimpl::hw_st_cond();
2568 format BasicOperate {
2569 0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing);
2571 // M5 special opcodes use the reserved 0x01 opcode space
2572 0x01: decode M5FUNC {
2574 AlphaPseudo::arm(xc->xcBase());
2575 }}, IsNonSpeculative);
2577 AlphaPseudo::quiesce(xc->xcBase());
2578 }}, IsNonSpeculative);
2580 AlphaPseudo::ivlb(xc->xcBase());
2581 }}, No_OpClass, IsNonSpeculative);
2583 AlphaPseudo::ivle(xc->xcBase());
2584 }}, No_OpClass, IsNonSpeculative);
2586 AlphaPseudo::m5exit_old(xc->xcBase());
2587 }}, No_OpClass, IsNonSpeculative);
2589 AlphaPseudo::m5exit(xc->xcBase());
2590 }}, No_OpClass, IsNonSpeculative);
2591 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
2593 AlphaPseudo::resetstats(xc->xcBase());
2594 }}, IsNonSpeculative);
2596 AlphaPseudo::dumpstats(xc->xcBase());
2597 }}, IsNonSpeculative);
2598 0x42: dumpresetstats({{
2599 AlphaPseudo::dumpresetstats(xc->xcBase());
2600 }}, IsNonSpeculative);
2601 0x43: m5checkpoint({{
2602 AlphaPseudo::m5checkpoint(xc->xcBase());
2603 }}, IsNonSpeculative);
2605 AlphaPseudo::readfile(xc->xcBase());
2606 }}, IsNonSpeculative);
2608 AlphaPseudo::debugbreak(xc->xcBase());
2609 }}, IsNonSpeculative);
2610 0x52: m5switchcpu({{
2611 AlphaPseudo::switchcpu(xc->xcBase());
2612 }}, IsNonSpeculative);
2619 // this instruction is only valid in PAL mode
2620 if (!xc->inPalMode()) {
2621 fault = Unimplemented_Opcode_Fault;
2624 Ra = xc->readIpr(ipr_index, fault);
2628 // this instruction is only valid in PAL mode
2629 if (!xc->inPalMode()) {
2630 fault = Unimplemented_Opcode_Fault;
2633 xc->setIpr(ipr_index, Ra);
2634 if (traceData) { traceData->setData(Ra); }