3 // Alpha ISA description file.
21 #include "base/cprintf.hh"
22 #include "base/misc.hh"
23 #include "cpu/exec_context.hh"
24 #include "cpu/exetrace.hh"
25 #include "cpu/full_cpu/full_cpu.hh"
26 #include "cpu/full_cpu/op_class.hh"
27 #include "cpu/full_cpu/spec_state.hh"
28 #include "cpu/simple_cpu/simple_cpu.hh"
29 #include "cpu/static_inst.hh"
30 #include "sim/annotation.hh"
31 #include "sim/serialize.hh"
32 #include "sim/sim_events.hh"
33 #include "sim/sim_stats.hh"
36 #include "targetarch/ev5.hh"
41 // Universal (format-independent) fields
42 def bitfield OPCODE <31:26>;
43 def bitfield RA <25:21>;
44 def bitfield RB <20:16>;
47 def signed bitfield MEMDISP <15: 0>; // displacement
48 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
50 // Memory-format jumps
51 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
52 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
55 def signed bitfield BRDISP <20: 0>; // displacement
57 // Integer operate format(s>;
58 def bitfield INTIMM <20:13>; // integer immediate (literal)
59 def bitfield IMM <12:12>; // immediate flag
60 def bitfield INTFUNC <11: 5>; // function code
61 def bitfield RC < 4: 0>; // dest reg
63 // Floating-point operate format
64 def bitfield FA <25:21>;
65 def bitfield FB <20:16>;
66 def bitfield FP_FULLFUNC <15: 5>; // complete function code
67 def bitfield FP_TRAPMODE <15:13>; // trapping mode
68 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
69 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
70 def bitfield FP_SRCTYPE <10: 9>; // source reg type
71 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
72 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
73 def bitfield FC < 4: 0>; // dest reg
76 def bitfield PALFUNC <25: 0>; // function code
78 // EV5 PAL instructions:
80 def bitfield HW_LDST_PHYS <15>; // address is physical
81 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
82 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
83 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
84 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
85 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
86 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
87 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
90 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
91 def bitfield HW_REI_MBZ <13: 0>; // must be zero
94 def bitfield HW_IPR_IDX <15:0>; // IPR index
97 def bitfield M5FUNC <7:0>;
100 global operandTypeMap
102 'sb' : ('signed int', 8),
103 'ub' : ('unsigned int', 8),
104 'sw' : ('signed int', 16),
105 'uw' : ('unsigned int', 16),
106 'sl' : ('signed int', 32),
107 'ul' : ('unsigned int', 32),
108 'sq' : ('signed int', 64),
109 'uq' : ('unsigned int', 64),
110 'sf' : ('float', 32),
114 global operandTraitsMap
116 # Int regs default to unsigned, but code should not count on this.
117 # For clarity, descriptions that depend on unsigned behavior should
118 # explicitly specify '.uq'.
119 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
120 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
121 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
122 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
123 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
124 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
125 'Mem': MemOperandTraits('uq', None,
126 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
127 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
128 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
129 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
130 # The next two are hacks for non-full-system call-pal emulation
131 'R0': IntRegOperandTraits('uq', '0', None, 1),
132 'R16': IntRegOperandTraits('uq', '16', None, 1),
135 defineDerivedOperandVars()
139 // just temporary, while comparing with old code for debugging
140 // #define SS_COMPATIBLE_DISASSEMBLY
142 /// Check "FP enabled" machine status bit. Called when executing any FP
143 /// instruction in full-system mode.
144 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
145 /// if not. Non-full-system mode: always returns No_Fault.
147 inline Fault checkFpEnableFault(ExecContext *xc)
149 Fault fault = No_Fault; // dummy... this ipr access should not fault
150 if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
156 inline Fault checkFpEnableFault(ExecContext *xc)
163 * Base class for all Alpha static instructions.
165 class AlphaStaticInst : public StaticInst<AlphaISA>
169 /// Make AlphaISA register dependence tags directly visible in
170 /// this class and derived classes. Maybe these should really
171 /// live here and not in the AlphaISA namespace.
172 enum DependenceTags {
173 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
174 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
175 Uniq_DepTag = AlphaISA::Uniq_DepTag,
176 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
180 AlphaStaticInst(const char *mnem, MachInst _machInst,
182 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
186 /// Print a register name for disassembly given the unique
187 /// dependence tag number (FP or int).
188 void printReg(std::ostream &os, int reg)
190 if (reg < FP_Base_DepTag) {
191 ccprintf(os, "r%d", reg);
194 ccprintf(os, "f%d", reg - FP_Base_DepTag);
198 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
200 std::stringstream ss;
202 ccprintf(ss, "%-10s ", mnemonic);
204 // just print the first two source regs... if there's
205 // a third one, it's a read-modify-write dest (Rc),
207 if (_numSrcRegs > 0) {
208 printReg(ss, _srcRegIdx[0]);
210 if (_numSrcRegs > 1) {
212 printReg(ss, _srcRegIdx[1]);
215 // just print the first dest... if there's a second one,
216 // it's generally implicit
217 if (_numDestRegs > 0) {
220 printReg(ss, _destRegIdx[0]);
229 def template BasicDeclare {{
231 * Static instruction class for "%(mnemonic)s".
233 class %(class_name)s : public %(base_class)s
237 %(class_name)s(MachInst machInst)
238 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
243 Fault execute(SimpleCPU *cpu, ExecContext *xc,
244 Trace::InstRecord *traceData)
246 SimpleCPU *memAccessObj __attribute__((unused)) = cpu;
247 Fault fault = No_Fault;
254 if (fault == No_Fault) {
261 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
262 Trace::InstRecord *traceData)
264 DynInst *memAccessObj __attribute__((unused)) = dynInst;
265 Fault fault = No_Fault;
272 if (fault == No_Fault) {
281 def template BasicDecode {{
282 return new %(class_name)s(machInst);
285 def template BasicDecodeWithMnemonic {{
286 return new %(class_name)s("%(mnemonic)s", machInst);
289 // The most basic instruction format... used only for a few misc. insts
290 def format BasicOperate(code, *flags) {{
291 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
292 return iop.subst('BasicDeclare', 'BasicDecode')
297 ////////////////////////////////////////////////////////////////////
301 * Static instruction class for no-ops. This is a leaf class.
303 class Nop : public AlphaStaticInst
305 /// Disassembly of original instruction.
306 const std::string originalDisassembly;
310 Nop(const std::string _originalDisassembly, MachInst _machInst)
311 : AlphaStaticInst("nop", _machInst, No_OpClass),
312 originalDisassembly(_originalDisassembly)
319 Fault execute(SimpleCPU *cpu, ExecContext *xc,
320 Trace::InstRecord *traceData)
325 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
326 Trace::InstRecord *traceData)
331 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
333 #ifdef SS_COMPATIBLE_DISASSEMBLY
334 return originalDisassembly;
336 return csprintf("%-10s (%s)", "nop", originalDisassembly);
341 /// Helper function for decoding nops. Substitute Nop object
342 /// for original inst passed in as arg (and delete latter).
345 makeNop(AlphaStaticInst *inst)
347 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
354 return ('', 'return new Nop("%s", machInst);\n' % name)
358 // integer & FP operate instructions use Rc as dest, so check for
359 // Rc == 31 to detect nops
360 def template OperateNopCheckDecode {{
362 AlphaStaticInst *i = new %(class_name)s(machInst);
370 // Like BasicOperate format, but generates NOP if RC/FC == 31
371 def format BasicOperateWithNopCheck(code, *opt_args) {{
372 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
374 return iop.subst('BasicDeclare', 'OperateNopCheckDecode')
378 ////////////////////////////////////////////////////////////////////
380 // Integer operate instructions
385 * Base class for integer immediate instructions.
387 class IntegerImm : public AlphaStaticInst
390 /// Immediate operand value (unsigned 8-bit int).
394 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
395 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
399 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
401 std::stringstream ss;
403 ccprintf(ss, "%-10s ", mnemonic);
405 // just print the first source reg... if there's
406 // a second one, it's a read-modify-write dest (Rc),
408 if (_numSrcRegs > 0) {
409 printReg(ss, _srcRegIdx[0]);
415 if (_numDestRegs > 0) {
417 printReg(ss, _destRegIdx[0]);
425 def template RegOrImmDecode {{
428 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
429 : (AlphaStaticInst *)new %(class_name)s(machInst);
437 // Primary format for integer operate instructions:
438 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
439 // - Generates NOP if RC == 31.
440 def format IntegerOperate(code, *opt_flags) {{
441 # If the code block contains 'Rb_or_imm', we define two instructions,
442 # one using 'Rb' and one using 'imm', and have the decoder select
444 uses_imm = (code.find('Rb_or_imm') != -1)
447 # base code is reg version:
448 # rewrite by substituting 'Rb' for 'Rb_or_imm'
449 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
450 # generate immediate version by substituting 'imm'
451 # note that imm takes no extenstion, so we extend
452 # the regexp to replace any extension as well
453 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
455 # generate declaration for register version
456 cblk = CodeBlock(code)
457 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
458 decls = iop.subst('BasicDeclare')
461 # append declaration for imm version
462 imm_cblk = CodeBlock(imm_code)
463 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
465 decls += imm_iop.subst('BasicDeclare')
466 # decode checks IMM bit to pick correct version
467 decode = iop.subst('RegOrImmDecode')
469 # no imm version: just check for nop
470 decode = iop.subst('OperateNopCheckDecode')
472 return (decls, decode)
476 ////////////////////////////////////////////////////////////////////
478 // Floating-point instructions
480 // Note that many FP-type instructions which do not support all the
481 // various rounding & trapping modes use the simpler format
482 // BasicOperateWithNopCheck.
487 * Base class for general floating-point instructions. Includes
488 * support for various Alpha rounding and trapping modes. Only FP
489 * instructions that require this support are derived from this
490 * class; the rest derive directly from AlphaStaticInst.
492 class AlphaFP : public AlphaStaticInst
495 /// Alpha FP rounding modes.
497 Chopped = 0, ///< round toward zero
498 Minus_Infinity = 1, ///< round toward minus infinity
499 Normal = 2, ///< round to nearest (default)
500 Dynamic = 3, ///< use FPCR setting (in instruction)
501 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
504 /// Alpha FP trapping modes.
505 /// For instructions that produce integer results, the
506 /// "Underflow Enable" modes really mean "Overflow Enable", and
507 /// the assembly modifier is V rather than U.
509 /// default: nothing enabled
510 Imprecise = 0, ///< no modifier
511 /// underflow/overflow traps enabled, inexact disabled
512 Underflow_Imprecise = 1, ///< /U or /V
513 Underflow_Precise = 5, ///< /SU or /SV
514 /// underflow/overflow and inexact traps enabled
515 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
520 static const int alphaToC99RoundingMode[];
523 /// Map enum RoundingMode values to disassembly suffixes.
524 static const char *roundingModeSuffix[];
525 /// Map enum TrappingMode values to FP disassembly suffixes.
526 static const char *fpTrappingModeSuffix[];
527 /// Map enum TrappingMode values to integer disassembly suffixes.
528 static const char *intTrappingModeSuffix[];
530 /// This instruction's rounding mode.
531 RoundingMode roundingMode;
532 /// This instruction's trapping mode.
533 TrappingMode trappingMode;
536 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
537 : AlphaStaticInst(mnem, _machInst, __opClass),
538 roundingMode((enum RoundingMode)FP_ROUNDMODE),
539 trappingMode((enum TrappingMode)FP_TRAPMODE)
541 if (trappingMode != Imprecise) {
542 warn("Warning: precise FP traps unimplemented\n");
548 getC99RoundingMode(ExecContext *xc)
550 if (roundingMode == Dynamic) {
551 return alphaToC99RoundingMode[bits(xc->readFpcr(), 59, 58)];
554 return alphaToC99RoundingMode[roundingMode];
559 // This differs from the AlphaStaticInst version only in
560 // printing suffixes for non-default rounding & trapping modes.
561 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
563 std::string mnem_str(mnemonic);
565 mnem_str += ((_destRegIdx[0] >= FP_Base_DepTag)
566 ? fpTrappingModeSuffix[trappingMode]
567 : intTrappingModeSuffix[trappingMode]);
568 mnem_str += roundingModeSuffix[roundingMode];
570 std::stringstream ss;
572 ccprintf(ss, "%-10s ", mnem_str.c_str());
574 // just print the first two source regs... if there's
575 // a third one, it's a read-modify-write dest (Rc),
577 if (_numSrcRegs > 0) {
578 printReg(ss, _srcRegIdx[0]);
580 if (_numSrcRegs > 1) {
582 printReg(ss, _srcRegIdx[1]);
585 // just print the first dest... if there's a second one,
586 // it's generally implicit
587 if (_numDestRegs > 0) {
590 printReg(ss, _destRegIdx[0]);
598 const int AlphaFP::alphaToC99RoundingMode[] = {
599 FE_TOWARDZERO, // Chopped
600 FE_DOWNWARD, // Minus_Infinity
601 FE_TONEAREST, // Normal
602 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
606 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
607 // mark invalid trapping modes, but don't fail on them, because
608 // you could decode anything on a misspeculated path
609 const char *AlphaFP::fpTrappingModeSuffix[] =
610 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
611 const char *AlphaFP::intTrappingModeSuffix[] =
612 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
616 def template FloatingPointDeclare {{
618 * "Fast" static instruction class for "%(mnemonic)s" (imprecise
619 * trapping mode, normal rounding mode).
621 class %(class_name)sFast : public %(base_class)s
625 %(class_name)sFast(MachInst machInst)
626 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
631 Fault execute(SimpleCPU *cpu, ExecContext *xc,
632 Trace::InstRecord *traceData)
634 Fault fault = No_Fault;
641 if (fault == No_Fault) {
648 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
649 Trace::InstRecord *traceData)
651 Fault fault = No_Fault;
658 if (fault == No_Fault) {
667 * General static instruction class for "%(mnemonic)s". Supports
668 * all the various rounding and trapping modes.
670 class %(class_name)sGeneral : public %(base_class)s
674 %(class_name)sGeneral(MachInst machInst)
675 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
680 Fault execute(SimpleCPU *cpu, ExecContext *xc,
681 Trace::InstRecord *traceData)
683 Fault fault = No_Fault;
690 fesetround(getC99RoundingMode(xc));
696 fesetround(FE_TONEAREST);
699 if (fault == No_Fault) {
706 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
707 Trace::InstRecord *traceData)
709 Fault fault = No_Fault;
716 fesetround(getC99RoundingMode(xc));
722 fesetround(FE_TONEAREST);
725 if (fault == No_Fault) {
734 def template FloatingPointDecode {{
736 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
737 && FP_ROUNDMODE == AlphaFP::Normal);
739 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
740 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
751 // General format for floating-point operate instructions:
752 // - Checks trapping and rounding mode flags. Trapping modes
753 // currently unimplemented (will fail).
754 // - Generates NOP if FC == 31.
755 def format FloatingPointOperate(code, *opt_args) {{
756 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code),
758 return iop.subst('FloatingPointDeclare', 'FloatingPointDecode')
762 ////////////////////////////////////////////////////////////////////
764 // Memory-format instructions: LoadAddress, Load, Store
769 * Base class for general Alpha memory-format instructions.
771 class Memory : public AlphaStaticInst
775 /// Displacement for EA calculation (signed).
777 /// Memory request flags. See mem_req_base.hh.
778 unsigned memAccessFlags;
781 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
782 : AlphaStaticInst(mnem, _machInst, __opClass),
783 disp(MEMDISP), memAccessFlags(0)
787 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
789 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
790 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
795 * Base class for a few miscellaneous memory-format insts
796 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
797 * None of these instructions has a destination register either.
799 class MemoryNoDisp : public AlphaStaticInst
802 /// Memory request flags. See mem_req_base.hh.
803 unsigned memAccessFlags;
806 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass)
807 : AlphaStaticInst(mnem, _machInst, __opClass),
812 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
814 return csprintf("%-10s (r%d)", mnemonic, RB);
819 * Base class for "fake" effective-address computation
820 * instructions returnded by eaCompInst().
822 class EACompBase : public AlphaStaticInst
826 EACompBase(MachInst machInst)
827 : AlphaStaticInst("(eacomp)", machInst, IntALU)
831 Fault execute(SimpleCPU *cpu, ExecContext *xc,
832 Trace::InstRecord *traceData)
833 { panic("attempt to execute eacomp"); }
835 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
836 Trace::InstRecord *traceData)
837 { panic("attempt to execute eacomp"); }
841 * Base class for "fake" memory-access instructions returnded by
844 class MemAccBase : public AlphaStaticInst
848 MemAccBase(MachInst machInst, OpClass __opClass)
849 : AlphaStaticInst("(memacc)", machInst, __opClass)
853 Fault execute(SimpleCPU *cpu, ExecContext *xc,
854 Trace::InstRecord *traceData)
855 { panic("attempt to execute memacc"); }
857 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
858 Trace::InstRecord *traceData)
859 { panic("attempt to execute memacc"); }
865 def format LoadAddress(code) {{
866 iop = InstObjParams(name, Name, 'Memory', CodeBlock(code))
867 return iop.subst('BasicDeclare', 'BasicDecode')
871 def template LoadStoreDeclare {{
873 * Static instruction class for "%(mnemonic)s".
875 class %(class_name)s : public %(base_class)s
880 * "Fake" effective address computation class for "%(mnemonic)s".
882 class EAComp : public EACompBase
886 EAComp(MachInst machInst)
887 : EACompBase(machInst)
894 * "Fake" memory access instruction class for "%(mnemonic)s".
896 class MemAcc : public MemAccBase
900 MemAcc(MachInst machInst)
901 : MemAccBase(machInst, %(op_class)s)
903 %(memacc_constructor)s;
907 /// Pointer to EAComp object.
908 StaticInstPtr<AlphaISA> eaCompPtr;
909 /// Pointer to MemAcc object.
910 StaticInstPtr<AlphaISA> memAccPtr;
914 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
915 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
918 %(class_name)s(MachInst machInst)
919 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
920 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
925 Fault execute(SimpleCPU *cpu, ExecContext *xc,
926 Trace::InstRecord *traceData)
928 SimpleCPU *memAccessObj = cpu;
930 Fault fault = No_Fault;
934 %(simple_nonmem_rd)s;
937 if (fault == No_Fault) {
942 if (fault == No_Fault) {
946 if (fault == No_Fault) {
950 if (fault == No_Fault) {
951 %(simple_nonmem_wb)s;
957 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
958 Trace::InstRecord *traceData)
960 DynInst *memAccessObj = dynInst;
962 Fault fault = No_Fault;
969 if (fault == No_Fault) {
974 if (fault == No_Fault) {
978 if (fault == No_Fault) {
982 if (fault == No_Fault) {
992 def template PrefetchDeclare {{
994 * Static instruction class for "%(mnemonic)s".
996 class %(class_name)s : public %(base_class)s
1000 %(class_name)s(MachInst machInst)
1001 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
1006 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1007 Trace::InstRecord *traceData)
1010 Fault fault = No_Fault;
1012 %(fp_enable_check)s;
1014 %(simple_nonmem_rd)s;
1017 if (fault == No_Fault) {
1018 cpu->prefetch(EA, memAccessFlags);
1024 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1025 Trace::InstRecord *traceData)
1028 Fault fault = No_Fault;
1030 %(fp_enable_check)s;
1035 if (fault == No_Fault) {
1036 dynInst->prefetch(EA, memAccessFlags);
1045 // load instructions use Ra as dest, so check for
1046 // Ra == 31 to detect nops
1047 def template LoadNopCheckDecode {{
1049 AlphaStaticInst *i = new %(class_name)s(machInst);
1058 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1059 def template LoadPrefetchCheckDecode {{
1062 return new %(class_name)s(machInst);
1065 return new %(class_name)sPrefetch(machInst);
1072 global LoadStoreBase
1073 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1074 base_class = 'Memory', flags = [],
1075 declare_template = 'LoadStoreDeclare',
1076 decode_template = 'BasicDecode'):
1077 # Segregate flags into instruction flags (handled by InstObjParams)
1078 # and memory access flags (handled here).
1080 # Would be nice to autogenerate this list, but oh well.
1081 valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1085 if f in valid_mem_flags:
1088 inst_flags.append(f)
1090 ea_cblk = CodeBlock(ea_code)
1091 memacc_cblk = CodeBlock(memacc_code)
1092 postacc_cblk = CodeBlock(postacc_code)
1094 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1095 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1097 iop.ea_constructor = ea_cblk.constructor
1098 iop.ea_code = ea_cblk.code
1099 iop.memacc_constructor = memacc_cblk.constructor
1100 iop.memacc_code = memacc_cblk.code
1101 iop.postacc_code = postacc_cblk.code
1103 mem_flags = string.join(mem_flags, '|')
1105 iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
1107 return iop.subst(declare_template, decode_template)
1111 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1112 return LoadStoreBase(name, Name, ea_code, memacc_code,
1114 decode_template = 'LoadNopCheckDecode')
1118 // Note that the flags passed in apply only to the prefetch version
1119 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1120 # declare the load instruction object and generate the decode block
1122 LoadStoreBase(name, Name, ea_code, memacc_code,
1123 decode_template = 'LoadPrefetchCheckDecode')
1125 # Declare the prefetch instruction object.
1127 # convert flags from tuple to list to make them mutable
1128 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'RdPort']
1130 (pfdecls, pfdecode) = \
1131 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1133 declare_template = 'PrefetchDeclare')
1135 return (decls + pfdecls, decode)
1139 def format Store(ea_code, memacc_code, *flags) {{
1140 return LoadStoreBase(name, Name, ea_code, memacc_code,
1145 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1146 return LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1151 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1152 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1153 return LoadStoreBase(name, Name, ea_code, memacc_code,
1154 flags = flags, base_class = 'MemoryNoDisp')
1158 ////////////////////////////////////////////////////////////////////
1164 * Base class for instructions whose disassembly is not purely a
1165 * function of the machine instruction (i.e., it depends on the
1166 * PC). This class overrides the disassemble() method to check
1167 * the PC and symbol table values before re-using a cached
1168 * disassembly string. This is necessary for branches and jumps,
1169 * where the disassembly string includes the target address (which
1170 * may depend on the PC and/or symbol table).
1172 class PCDependentDisassembly : public AlphaStaticInst
1175 /// Cached program counter from last disassembly
1177 /// Cached symbol table pointer from last disassembly
1178 const SymbolTable *cachedSymtab;
1181 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1183 : AlphaStaticInst(mnem, _machInst, __opClass),
1184 cachedPC(0), cachedSymtab(0)
1188 const std::string &disassemble(Addr pc, const SymbolTable *symtab)
1190 if (!cachedDisassembly ||
1191 pc != cachedPC || symtab != cachedSymtab)
1193 if (cachedDisassembly)
1194 delete cachedDisassembly;
1197 new std::string(generateDisassembly(pc, symtab));
1199 cachedSymtab = symtab;
1202 return *cachedDisassembly;
1207 * Base class for branches (PC-relative control transfers),
1208 * conditional or unconditional.
1210 class Branch : public PCDependentDisassembly
1213 /// Displacement to target address (signed).
1217 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1218 : PCDependentDisassembly(mnem, _machInst, __opClass),
1223 Addr branchTarget(Addr branchPC)
1225 return branchPC + 4 + disp;
1228 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1230 std::stringstream ss;
1232 ccprintf(ss, "%-10s ", mnemonic);
1234 // There's only one register arg (RA), but it could be
1235 // either a source (the condition for conditional
1236 // branches) or a destination (the link reg for
1237 // unconditional branches)
1238 if (_numSrcRegs > 0) {
1239 printReg(ss, _srcRegIdx[0]);
1242 else if (_numDestRegs > 0) {
1243 printReg(ss, _destRegIdx[0]);
1247 #ifdef SS_COMPATIBLE_DISASSEMBLY
1248 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1254 Addr target = pc + 4 + disp;
1257 if (symtab && symtab->findSymbol(target, str))
1260 ccprintf(ss, "0x%x", target);
1267 * Base class for jumps (register-indirect control transfers). In
1268 * the Alpha ISA, these are always unconditional.
1270 class Jump : public PCDependentDisassembly
1274 /// Displacement to target address (signed).
1279 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1280 : PCDependentDisassembly(mnem, _machInst, __opClass),
1285 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1287 std::stringstream ss;
1289 ccprintf(ss, "%-10s ", mnemonic);
1291 #ifdef SS_COMPATIBLE_DISASSEMBLY
1292 if (_numDestRegs == 0) {
1298 if (_numDestRegs > 0) {
1299 printReg(ss, _destRegIdx[0]);
1303 ccprintf(ss, "(r%d)", RB);
1310 def template JumpOrBranchDecode {{
1312 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1313 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1316 def format CondBranch(code) {{
1317 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1318 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1319 ('IsDirectControl', 'IsCondControl'))
1320 return iop.subst('BasicDeclare', 'BasicDecode')
1324 global UncondCtrlBase
1325 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1326 # Declare basic control transfer w/o link (i.e. link reg is R31)
1327 nolink_code = 'NPC = %s;\n' % npc_expr
1328 nolink_iop = InstObjParams(name, Name, base_class,
1329 CodeBlock(nolink_code), flags)
1330 decls = nolink_iop.subst('BasicDeclare')
1332 # Generate declaration of '*AndLink' version, append to decls
1333 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1334 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1335 CodeBlock(link_code), flags)
1336 decls += link_iop.subst('BasicDeclare')
1338 # need to use link_iop for the decode template since it is expecting
1339 # the shorter version of class_name (w/o "AndLink")
1340 return (decls, nolink_iop.subst('JumpOrBranchDecode'))
1343 def format UncondBranch(*flags) {{
1344 flags += ('IsUncondControl', 'IsDirectControl')
1345 return UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1348 def format Jump(*flags) {{
1349 flags += ('IsUncondControl', 'IsIndirectControl')
1350 return UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1356 * Base class for emulated call_pal calls (used only in
1357 * non-full-system mode).
1359 class EmulatedCallPal : public AlphaStaticInst
1364 EmulatedCallPal(const char *mnem, MachInst _machInst,
1366 : AlphaStaticInst(mnem, _machInst, __opClass)
1370 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1372 #ifdef SS_COMPATIBLE_DISASSEMBLY
1373 return csprintf("%s %s", "call_pal", mnemonic);
1375 return csprintf("%-10s %s", "call_pal", mnemonic);
1381 def format EmulatedCallPal(code) {{
1382 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code))
1383 return iop.subst('BasicDeclare', 'BasicDecode')
1388 * Base class for full-system-mode call_pal instructions.
1389 * Probably could turn this into a leaf class and get rid of the
1392 class CallPalBase : public AlphaStaticInst
1395 int palFunc; ///< Function code part of instruction
1396 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1399 CallPalBase(const char *mnem, MachInst _machInst,
1401 : AlphaStaticInst(mnem, _machInst, __opClass),
1404 int palPriv = ((machInst & 0x80) != 0);
1405 int shortPalFunc = (machInst & 0x3f);
1406 palOffset = 0x2001 + (palPriv << 12) + (shortPalFunc << 6);
1409 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1411 return csprintf("%-10s %#x", "call_pal", palFunc);
1417 def format CallPal(code) {{
1418 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code))
1419 return iop.subst('BasicDeclare', 'BasicDecode')
1427 * Base class for hw_ld and hw_st.
1429 class HwLoadStore : public AlphaStaticInst
1433 /// Displacement for EA calculation (signed).
1435 /// Memory request flags. See mem_req_base.hh.
1436 unsigned memAccessFlags;
1439 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass)
1440 : AlphaStaticInst(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
1443 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1444 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1445 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1446 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1449 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1451 #ifdef SS_COMPATIBLE_DISASSEMBLY
1452 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1454 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1455 const char *lock_str =
1456 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1458 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1459 mnemonic, RA, disp, RB,
1460 HW_LDST_PHYS ? ",PHYS" : "",
1461 HW_LDST_ALT ? ",ALT" : "",
1462 HW_LDST_QUAD ? ",QUAD" : "",
1463 HW_LDST_VPTE ? ",VPTE" : "",
1471 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1472 return LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1474 base_class = 'HwLoadStore')
1478 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1479 return LoadStoreBase(name, Name + class_ext,
1480 ea_code, memacc_code, postacc_code,
1482 base_class = 'HwLoadStore')
1488 * Base class for hw_mfpr and hw_mtpr.
1490 class HwMoveIPR : public AlphaStaticInst
1493 /// Index of internal processor register.
1497 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1498 : AlphaStaticInst(mnem, _machInst, __opClass),
1499 ipr_index(HW_IPR_IDX)
1503 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1505 if (_numSrcRegs > 0) {
1507 return csprintf("%-10s r%d,IPR(%#x)",
1508 mnemonic, RA, ipr_index);
1512 return csprintf("%-10s IPR(%#x),r%d",
1513 mnemonic, ipr_index, RA);
1519 def format HwMoveIPR(code) {{
1520 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1521 return iop.subst('BasicDeclare', 'BasicDecode')
1526 * Static instruction class for unimplemented instructions that
1527 * cause simulator termination. Note that these are recognized
1528 * (legal) instructions that the simulator does not support; the
1529 * 'Unknown' class is used for unrecognized/illegal instructions.
1530 * This is a leaf class.
1532 class FailUnimplemented : public AlphaStaticInst
1536 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1537 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1541 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1542 Trace::InstRecord *traceData)
1544 panic("attempt to execute unimplemented instruction '%s' "
1545 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1546 return Unimplemented_Opcode_Fault;
1549 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1550 Trace::InstRecord *traceData)
1552 // don't panic if this is a misspeculated instruction
1554 panic("attempt to execute unimplemented instruction '%s' "
1555 "(inst 0x%08x, opcode 0x%x)",
1556 mnemonic, machInst, OPCODE);
1557 return Unimplemented_Opcode_Fault;
1560 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1562 return csprintf("%-10s (unimplemented)", mnemonic);
1567 * Base class for unimplemented instructions that cause a warning
1568 * to be printed (but do not terminate simulation). This
1569 * implementation is a little screwy in that it will print a
1570 * warning for each instance of a particular unimplemented machine
1571 * instruction, not just for each unimplemented opcode. Should
1572 * probably make the 'warned' flag a static member of the derived
1575 class WarnUnimplemented : public AlphaStaticInst
1578 /// Have we warned on this instruction yet?
1583 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1584 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1588 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1589 Trace::InstRecord *traceData)
1592 warn("Warning: instruction '%s' unimplemented\n", mnemonic);
1599 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1600 Trace::InstRecord *traceData)
1602 if (!xc->spec_mode && !warned) {
1603 warn("Warning: instruction '%s' unimplemented\n", mnemonic);
1610 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1612 #ifdef SS_COMPATIBLE_DISASSEMBLY
1613 return csprintf("%-10s", mnemonic);
1615 return csprintf("%-10s (unimplemented)", mnemonic);
1621 def template WarnUnimplDeclare {{
1623 * Static instruction class for "%(mnemonic)s".
1625 class %(class_name)s : public %(base_class)s
1629 %(class_name)s(MachInst machInst)
1630 : %(base_class)s("%(mnemonic)s", machInst)
1637 def format FailUnimpl() {{
1638 iop = InstObjParams(name, 'FailUnimplemented')
1639 return ('', iop.subst('BasicDecodeWithMnemonic'))
1642 def format WarnUnimpl() {{
1643 iop = InstObjParams(name, Name, 'WarnUnimplemented')
1644 return iop.subst('WarnUnimplDeclare', 'BasicDecode')
1649 * Static instruction class for unknown (illegal) instructions.
1650 * These cause simulator termination if they are executed in a
1651 * non-speculative mode. This is a leaf class.
1653 class Unknown : public AlphaStaticInst
1657 Unknown(MachInst _machInst)
1658 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1662 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1663 Trace::InstRecord *traceData)
1665 panic("attempt to execute unknown instruction "
1666 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1667 return Unimplemented_Opcode_Fault;
1670 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1671 Trace::InstRecord *traceData)
1673 // don't panic if this is a misspeculated instruction
1675 panic("attempt to execute unknown instruction "
1676 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1677 return Unimplemented_Opcode_Fault;
1680 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1682 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1683 "unknown", machInst, OPCODE);
1688 def format Unknown() {{
1689 return ('', 'return new Unknown(machInst);\n')
1694 /// Return opa + opb, summing carry into third arg.
1696 addc(uint64_t opa, uint64_t opb, int &carry)
1698 uint64_t res = opa + opb;
1699 if (res < opa || res < opb)
1704 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1705 /// product in res_hi and res_lo.
1707 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1709 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1710 uint64_t opa_hi = opa<63:32>;
1711 uint64_t opa_lo = opa<31:0>;
1712 uint64_t opb_hi = opb<63:32>;
1713 uint64_t opb_lo = opb<31:0>;
1715 res_lo = opa_lo * opb_lo;
1717 // The middle partial products logically belong in bit
1718 // positions 95 to 32. Thus the lower 32 bits of each product
1719 // sum into the upper 32 bits of the low result, while the
1720 // upper 32 sum into the low 32 bits of the upper result.
1721 uint64_t partial1 = opa_hi * opb_lo;
1722 uint64_t partial2 = opa_lo * opb_hi;
1724 uint64_t partial1_lo = partial1<31:0> << 32;
1725 uint64_t partial1_hi = partial1<63:32>;
1726 uint64_t partial2_lo = partial2<31:0> << 32;
1727 uint64_t partial2_hi = partial2<63:32>;
1729 // Add partial1_lo and partial2_lo to res_lo, keeping track
1730 // of any carries out
1732 res_lo = addc(partial1_lo, res_lo, carry_out);
1733 res_lo = addc(partial2_lo, res_lo, carry_out);
1735 // Now calculate the high 64 bits...
1736 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1739 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1740 /// See Table 2-2 of Alpha AHB.
1744 int hibit = old_exp<7:>;
1745 int lobits = old_exp<6:0>;
1748 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1751 return (lobits == 0) ? 0 : (0x380 | lobits);
1755 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1756 /// representation to be stored in an FP reg.
1758 s_to_t(uint32_t s_val)
1760 uint64_t tmp = s_val;
1761 return (tmp<31:> << 63 // sign bit
1762 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1763 | tmp<22:0> << 29); // fraction
1766 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1767 /// S-floating representation to be stored in memory.
1769 t_to_s(uint64_t t_val)
1771 return (t_val<63:62> << 30 // sign bit & hi exp bit
1772 | t_val<58:29>); // rest of exp & fraction
1776 decode OPCODE default Unknown::unknown() {
1778 format LoadAddress {
1779 0x08: lda({{ Ra = Rb + disp; }});
1780 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1784 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1785 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1786 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1787 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1788 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1789 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1792 format LoadOrPrefetch {
1793 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1794 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1795 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1800 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1801 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1802 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1803 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1804 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1805 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1806 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1810 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1812 uint64_t tmp = Mem_write_result;
1814 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1816 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1818 uint64_t tmp = Mem_write_result;
1819 // If the write operation returns 0 or 1, then
1820 // this was a conventional store conditional,
1821 // and the value indicates the success/failure
1822 // of the operation. If another value is
1823 // returned, then this was a Turbolaser
1824 // mailbox access, and we don't update the
1825 // result register at all.
1826 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1830 format IntegerOperate {
1832 0x10: decode INTFUNC { // integer arithmetic operations
1834 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1836 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1837 // signed overflow occurs when operands have same sign
1838 // and sign of result does not match.
1839 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1840 fault = Integer_Overflow_Fault;
1843 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1844 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1846 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1848 uint64_t tmp = Ra + Rb_or_imm;
1849 // signed overflow occurs when operands have same sign
1850 // and sign of result does not match.
1851 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1852 fault = Integer_Overflow_Fault;
1855 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1856 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1858 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1860 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1861 // signed overflow detection is same as for add,
1862 // except we need to look at the *complemented*
1863 // sign bit of the subtrahend (Rb), i.e., if the initial
1864 // signs are the *same* then no overflow can occur
1865 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1866 fault = Integer_Overflow_Fault;
1869 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1870 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1872 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1874 uint64_t tmp = Ra - Rb_or_imm;
1875 // signed overflow detection is same as for add,
1876 // except we need to look at the *complemented*
1877 // sign bit of the subtrahend (Rb), i.e., if the initial
1878 // signs are the *same* then no overflow can occur
1879 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1880 fault = Integer_Overflow_Fault;
1883 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1884 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1886 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1887 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1888 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1889 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1890 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1896 for (int i = 0; i < 8; ++i) {
1897 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1905 0x11: decode INTFUNC { // integer logical operations
1907 0x00: and({{ Rc = Ra & Rb_or_imm; }});
1908 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1909 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1910 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1911 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1912 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1914 // conditional moves
1915 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1916 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1917 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1918 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1919 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
1920 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1921 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1922 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
1924 // For AMASK, RA must be R31.
1926 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1929 // For IMPLVER, RA must be R31 and the B operand
1930 // must be the immediate value 1.
1934 // return EV5 for FULL_SYSTEM and EV6 otherwise
1947 // The mysterious 11.25...
1948 0x25: WarnUnimpl::eleven25();
1952 0x12: decode INTFUNC {
1953 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
1954 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
1955 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
1957 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
1958 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
1959 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
1960 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
1963 int bv = Rb_or_imm<2:0>;
1964 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
1967 int bv = Rb_or_imm<2:0>;
1968 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
1971 int bv = Rb_or_imm<2:0>;
1972 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
1975 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
1976 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
1977 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
1978 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
1981 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
1983 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
1985 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
1987 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
1988 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
1989 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
1990 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
1993 int bv = Rb_or_imm<2:0>;
1994 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
1997 int bv = Rb_or_imm<2:0>;
1998 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2001 int bv = Rb_or_imm<2:0>;
2002 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
2006 uint64_t zapmask = 0;
2007 for (int i = 0; i < 8; ++i) {
2009 zapmask |= (mask(8) << (i * 8));
2014 uint64_t zapmask = 0;
2015 for (int i = 0; i < 8; ++i) {
2017 zapmask |= (mask(8) << (i * 8));
2023 0x13: decode INTFUNC { // integer multiplies
2024 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMULT);
2025 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMULT);
2028 mul128(Ra, Rb_or_imm, hi, lo);
2032 // 32-bit multiply with trap on overflow
2033 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
2034 int64_t Rbx = Rb_or_imm.sl;
2035 int64_t tmp = Rax * Rbx;
2036 // To avoid overflow, all the upper 32 bits must match
2037 // the sign bit of the lower 32. We code this as
2038 // checking the upper 33 bits for all 0s or all 1s.
2039 uint64_t sign_bits = tmp<63:31>;
2040 if (sign_bits != 0 && sign_bits != mask(33))
2041 fault = Integer_Overflow_Fault;
2045 // 64-bit multiply with trap on overflow
2047 mul128(Ra, Rb_or_imm, hi, lo);
2048 // all the upper 64 bits must match the sign bit of
2050 if (!((hi == 0 && lo<63:> == 0) ||
2051 (hi == mask(64) && lo<63:> == 1)))
2052 fault = Integer_Overflow_Fault;
2057 0x1c: decode INTFUNC {
2058 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2059 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2080 format BasicOperateWithNopCheck {
2082 31: ftoit({{ Rc = Fa.uq; }}, FloatCVT);
2085 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2092 // Conditional branches.
2094 0x39: beq({{ cond = (Ra == 0); }});
2095 0x3d: bne({{ cond = (Ra != 0); }});
2096 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2097 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2098 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2099 0x3a: blt({{ cond = (Ra.sq < 0); }});
2100 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2101 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2103 0x31: fbeq({{ cond = (Fa == 0); }});
2104 0x35: fbne({{ cond = (Fa != 0); }});
2105 0x36: fbge({{ cond = (Fa >= 0); }});
2106 0x37: fbgt({{ cond = (Fa > 0); }});
2107 0x33: fble({{ cond = (Fa <= 0); }});
2108 0x32: fblt({{ cond = (Fa < 0); }});
2111 // unconditional branches
2112 format UncondBranch {
2117 // indirect branches
2118 0x1a: decode JMPFUNC {
2123 3: jsr_coroutine(IsCall, IsReturn);
2127 // IEEE floating point
2128 0x14: decode FP_SHORTFUNC {
2129 // Integer to FP register moves must have RB == 31
2131 31: decode FP_FULLFUNC {
2132 format BasicOperateWithNopCheck {
2133 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCVT);
2134 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCVT);
2135 0x014: FailUnimpl::itoff(); // VAX-format conversion
2140 // Square root instructions must have FA == 31
2142 31: decode FP_TYPEFUNC {
2143 format FloatingPointOperate {
2144 #ifdef SS_COMPATIBLE_FP
2147 fault = Arithmetic_Fault;
2153 fault = Arithmetic_Fault;
2154 Fc.sf = sqrt(Fb.sf);
2159 fault = Arithmetic_Fault;
2166 // VAX-format sqrtf and sqrtg are not implemented
2167 0xa: FailUnimpl::sqrtfg();
2170 // IEEE floating point
2171 0x16: decode FP_SHORTFUNC_TOP2 {
2172 // The top two bits of the short function code break this space
2173 // into four groups: binary ops, compares, reserved, and conversions.
2174 // See Table 4-12 of AHB.
2175 // Most of these instructions may have various trapping and
2176 // rounding mode flags set; these are decoded in the
2177 // FloatingPointDecode template used by the
2178 // FloatingPointOperate format.
2180 // add/sub/mul/div: just decode on the short function code
2182 0: decode FP_TYPEFUNC {
2183 format FloatingPointOperate {
2184 #ifdef SS_COMPATIBLE_FP
2185 0x00: adds({{ Fc = Fa + Fb; }});
2186 0x01: subs({{ Fc = Fa - Fb; }});
2187 0x02: muls({{ Fc = Fa * Fb; }}, FloatMULT);
2188 0x03: divs({{ Fc = Fa / Fb; }}, FloatDIV);
2190 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2191 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2192 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMULT);
2193 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDIV);
2196 0x20: addt({{ Fc = Fa + Fb; }});
2197 0x21: subt({{ Fc = Fa - Fb; }});
2198 0x22: mult({{ Fc = Fa * Fb; }}, FloatMULT);
2199 0x23: divt({{ Fc = Fa / Fb; }}, FloatDIV);
2203 // Floating-point compare instructions must have the default
2204 // rounding mode, and may use the default trapping mode or
2205 // /SU. Both trapping modes are treated the same by M5; the
2206 // only difference on the real hardware (as far a I can tell)
2207 // is that without /SU you'd get an imprecise trap if you
2208 // tried to compare a NaN with something else (instead of an
2209 // "unordered" result).
2210 1: decode FP_FULLFUNC {
2211 format BasicOperateWithNopCheck {
2212 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2214 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2216 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2218 0x0a4, 0x5a4: cmptun({{ // unordered
2219 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2224 // The FP-to-integer and integer-to-FP conversion insts
2225 // require that FA be 31.
2227 31: decode FP_TYPEFUNC {
2228 format FloatingPointOperate {
2229 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2231 // The cvtts opcode is overloaded to be cvtst if the trap
2232 // mode is 2 or 6 (which are not valid otherwise)
2233 0x2c: decode FP_FULLFUNC {
2234 format BasicOperateWithNopCheck {
2235 // trap on denorm version "cvtst/s" is
2236 // simulated same as cvtst
2237 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2239 default: cvtts({{ Fc.sf = Fb; }});
2242 // The trapping mode for integer-to-FP conversions
2243 // must be /SUI or nothing; /U and /SU are not
2244 // allowed. The full set of rounding modes are
2245 // supported though.
2246 0x3c: decode FP_TRAPMODE {
2247 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2249 0x3e: decode FP_TRAPMODE {
2250 0,7: cvtqt({{ Fc = Fb.sq; }});
2258 0x17: decode FP_FULLFUNC {
2259 format BasicOperateWithNopCheck {
2261 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2264 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2267 // We treat the precise & imprecise trapping versions of
2268 // cvtql identically.
2269 0x130, 0x530: cvtqlv({{
2270 // To avoid overflow, all the upper 32 bits must match
2271 // the sign bit of the lower 32. We code this as
2272 // checking the upper 33 bits for all 0s or all 1s.
2273 uint64_t sign_bits = Fb.uq<63:31>;
2274 if (sign_bits != 0 && sign_bits != mask(33))
2275 fault = Integer_Overflow_Fault;
2276 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2279 0x020: cpys({{ // copy sign
2280 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2282 0x021: cpysn({{ // copy sign negated
2283 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2285 0x022: cpyse({{ // copy sign and exponent
2286 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2289 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2290 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2291 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2292 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2293 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2294 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2296 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2297 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2301 // miscellaneous mem-format ops
2302 0x18: decode MEMFUNC {
2313 format MiscPrefetch {
2314 0xf800: wh64({{ EA = Rb; }},
2315 {{ memAccessObj->writeHint(EA, 64); }},
2316 IsMemRef, IsStore, WrPort);
2319 format BasicOperate {
2320 0xc000: rpcc({{ Ra = curTick; }});
2324 format BasicOperate {
2326 Ra = xc->regs.intrflag;
2327 if (!xc->misspeculating()) {
2328 xc->regs.intrflag = 0;
2332 Ra = xc->regs.intrflag;
2333 if (!xc->misspeculating()) {
2334 xc->regs.intrflag = 1;
2347 0x00: CallPal::call_pal({{
2348 // check to see if simulator wants to do something special
2349 // on this PAL call (including maybe suppress it)
2350 bool dopal = xc->simPalCheck(palFunc);
2352 if (!xc->misspeculating()) {
2353 Annotate::Callpal(xc, palFunc);
2357 if (!xc->misspeculating()) {
2358 AlphaISA::swap_palshadow(&xc->regs, true);
2360 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2361 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2365 0x00: decode PALFUNC {
2366 format EmulatedCallPal {
2368 if (!xc->misspeculating())
2369 SimExit(curTick, "halt instruction encountered");
2372 if (!xc->misspeculating())
2375 // Read uniq reg into ABI return value register (r0)
2376 0x9e: rduniq({{ R0 = Runiq; }});
2377 // Write uniq reg with value from ABI arg register (r16)
2378 0x9f: wruniq({{ Runiq = R16; }});
2384 format HwLoadStore {
2385 0x1b: decode HW_LDST_QUAD {
2386 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2387 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2390 0x1f: decode HW_LDST_COND {
2391 0: decode HW_LDST_QUAD {
2392 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2393 {{ Mem.ul = Ra<31:0>; }}, L);
2394 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2395 {{ Mem.uq = Ra.uq; }}, Q);
2398 1: FailUnimpl::hw_st_cond();
2402 format BasicOperate {
2403 0x1e: hw_rei({{ xc->hwrei(); }});
2405 // M5 special opcodes use the reserved 0x01 opcode space
2406 0x01: decode M5FUNC {
2408 if (!xc->misspeculating()) {
2410 xc->kernelStats.arm();
2414 if (!xc->misspeculating()) {
2415 Annotate::QUIESCE(xc);
2416 xc->setStatus(ExecContext::Suspended);
2417 xc->kernelStats.quiesce();
2421 if (!xc->misspeculating()) {
2422 Annotate::BeginInterval(xc);
2423 xc->kernelStats.ivlb();
2427 if (!xc->misspeculating())
2428 Annotate::EndInterval(xc);
2431 if (!xc->misspeculating())
2432 SimExit(curTick, "m5_exit_old instruction encountered");
2435 if (!xc->misspeculating()) {
2436 Tick delay = xc->regs.intRegFile[16];
2437 Tick when = curTick + NS2Ticks(delay);
2438 SimExit(when, "m5_exit instruction encountered");
2441 0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
2443 if (!xc->misspeculating()) {
2444 using namespace Statistics;
2445 Tick delay = xc->regs.intRegFile[16];
2446 Tick period = xc->regs.intRegFile[17];
2448 Tick when = curTick + NS2Ticks(delay);
2449 Tick repeat = NS2Ticks(period);
2451 SetupEvent(Reset, when, repeat);
2455 if (!xc->misspeculating()) {
2456 using namespace Statistics;
2457 Tick delay = xc->regs.intRegFile[16];
2458 Tick period = xc->regs.intRegFile[17];
2460 Tick when = curTick + NS2Ticks(delay);
2461 Tick repeat = NS2Ticks(period);
2463 SetupEvent(Dump, when, repeat);
2466 0x42: dumpresetstats({{
2467 if (!xc->misspeculating()) {
2468 using namespace Statistics;
2469 Tick delay = xc->regs.intRegFile[16];
2470 Tick period = xc->regs.intRegFile[17];
2472 Tick when = curTick + NS2Ticks(delay);
2473 Tick repeat = NS2Ticks(period);
2475 SetupEvent(Dump|Reset, when, repeat);
2478 0x43: m5checkpoint({{
2479 if (!xc->misspeculating()) {
2480 Tick delay = xc->regs.intRegFile[16];
2481 Tick period = xc->regs.intRegFile[17];
2483 Tick when = curTick + NS2Ticks(delay);
2484 Tick repeat = NS2Ticks(period);
2486 SetupCheckpoint(when, repeat);
2494 // this instruction is only valid in PAL mode
2495 if (!PC_PAL(xc->regs.pc)) {
2496 fault = Unimplemented_Opcode_Fault;
2499 Ra = xc->readIpr(ipr_index, fault);
2503 // this instruction is only valid in PAL mode
2504 if (!PC_PAL(xc->regs.pc)) {
2505 fault = Unimplemented_Opcode_Fault;
2508 xc->setIpr(ipr_index, Ra);
2509 if (traceData) { traceData->setData(Ra); }