arch/alpha/isa_desc

   1 // -*- mode:c++ -*-
   2
   3 ////////////////////////////////////////////////////////////////////
   4 //
   5 // Alpha ISA description file.
   6 //
   7 ////////////////////////////////////////////////////////////////////
   8
   9
  10 ////////////////////////////////////////////////////////////////////
  11 //
  12 // Output include file directives.
  13 //
  14
  15 output header {{
  16 #include <sstream>
  17 #include <iostream>
  18 #include <iomanip>
  19
  20 #include "cpu/static_inst.hh"
  21 #include "mem/mem_req.hh"  // some constructors use MemReq flags
  22 }};
  23
  24 output decoder {{
  25 #include "base/cprintf.hh"
  26 #include "base/loader/symtab.hh"
  27 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
  28
  29 #include <math.h>
  30 #if defined(linux)
  31 #include <fenv.h>
  32 #endif
  33 }};
  34
  35 output exec {{
  36 #include <math.h>
  37 #if defined(linux)
  38 #include <fenv.h>
  39 #endif
  40
  41 #ifdef FULL_SYSTEM
  42 #include "arch/alpha/pseudo_inst.hh"
  43 #endif
  44 #include "cpu/base_cpu.hh"
  45 #include "cpu/exetrace.hh"
  46 #include "sim/sim_exit.hh"
  47 }};
  48
  49 ////////////////////////////////////////////////////////////////////
  50 //
  51 // Namespace statement.  Everything below this line will be in the
  52 // AlphaISAInst namespace.
  53 //
  54
  55
  56 namespace AlphaISA;
  57
  58 ////////////////////////////////////////////////////////////////////
  59 //
  60 // Bitfield definitions.
  61 //
  62
  63 // Universal (format-independent) fields
  64 def bitfield OPCODE     <31:26>;
  65 def bitfield RA         <25:21>;
  66 def bitfield RB         <20:16>;
  67
  68 // Memory format
  69 def signed bitfield MEMDISP <15: 0>; // displacement
  70 def        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
  71
  72 // Memory-format jumps
  73 def bitfield JMPFUNC    <15:14>; // function code (disp<15:14>)
  74 def bitfield JMPHINT    <13: 0>; // tgt Icache idx hint (disp<13:0>)
  75
  76 // Branch format
  77 def signed bitfield BRDISP <20: 0>; // displacement
  78
  79 // Integer operate format(s>;
  80 def bitfield INTIMM     <20:13>; // integer immediate (literal)
  81 def bitfield IMM        <12:12>; // immediate flag
  82 def bitfield INTFUNC    <11: 5>; // function code
  83 def bitfield RC         < 4: 0>; // dest reg
  84
  85 // Floating-point operate format
  86 def bitfield FA           <25:21>;
  87 def bitfield FB           <20:16>;
  88 def bitfield FP_FULLFUNC  <15: 5>; // complete function code
  89     def bitfield FP_TRAPMODE  <15:13>; // trapping mode
  90     def bitfield FP_ROUNDMODE <12:11>; // rounding mode
  91     def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding
  92         def bitfield FP_SRCTYPE   <10: 9>; // source reg type
  93         def bitfield FP_SHORTFUNC < 8: 5>; // short function code
  94         def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
  95 def bitfield FC           < 4: 0>; // dest reg
  96
  97 // PALcode format
  98 def bitfield PALFUNC    <25: 0>; // function code
  99
 100 // EV5 PAL instructions:
 101 // HW_LD/HW_ST
 102 def bitfield HW_LDST_PHYS  <15>; // address is physical
 103 def bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPR
 104 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
 105 def bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64b
 106 def bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetch
 107 def bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load locked
 108 def bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditional
 109 def signed bitfield HW_LDST_DISP  <9:0>; // signed displacement
 110
 111 // HW_REI
 112 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
 113 def bitfield HW_REI_MBZ <13: 0>; // must be zero
 114
 115 // HW_MTPR/MW_MFPR
 116 def bitfield HW_IPR_IDX <15:0>;  // IPR index
 117
 118 // M5 instructions
 119 def bitfield M5FUNC <7:0>;
 120
 121 def operand_types {{
 122     'sb' : ('signed int', 8),
 123     'ub' : ('unsigned int', 8),
 124     'sw' : ('signed int', 16),
 125     'uw' : ('unsigned int', 16),
 126     'sl' : ('signed int', 32),
 127     'ul' : ('unsigned int', 32),
 128     'sq' : ('signed int', 64),
 129     'uq' : ('unsigned int', 64),
 130     'sf' : ('float', 32),
 131     'df' : ('float', 64)
 132 }};
 133
 134 def operands {{
 135     # Int regs default to unsigned, but code should not count on this.
 136     # For clarity, descriptions that depend on unsigned behavior should
 137     # explicitly specify '.uq'.
 138     'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
 139     'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
 140     'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
 141     'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
 142     'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
 143     'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
 144     'Mem': MemOperandTraits('uq', None,
 145                             ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 146     'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
 147     'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
 148     'FPCR':  ControlRegOperandTraits('uq', 'Fpcr', None, 1),
 149     # The next two are hacks for non-full-system call-pal emulation
 150     'R0':  IntRegOperandTraits('uq', '0', None, 1),
 151     'R16': IntRegOperandTraits('uq', '16', None, 1)
 152 }};
 153
 154 ////////////////////////////////////////////////////////////////////
 155 //
 156 // Basic instruction classes/templates/formats etc.
 157 //
 158
 159 output header {{
 160 // uncomment the following to get SimpleScalar-compatible disassembly
 161 // (useful for diffing output traces).
 162 // #define SS_COMPATIBLE_DISASSEMBLY
 163
 164     /**
 165      * Base class for all Alpha static instructions.
 166      */
 167     class AlphaStaticInst : public StaticInst<AlphaISA>
 168     {
 169       protected:
 170
 171         /// Make AlphaISA register dependence tags directly visible in
 172         /// this class and derived classes.  Maybe these should really
 173         /// live here and not in the AlphaISA namespace.
 174         enum DependenceTags {
 175             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
 176             Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
 177             Uniq_DepTag = AlphaISA::Uniq_DepTag,
 178             IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
 179         };
 180
 181         /// Constructor.
 182         AlphaStaticInst(const char *mnem, MachInst _machInst,
 183                         OpClass __opClass)
 184             : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
 185         {
 186         }
 187
 188         /// Print a register name for disassembly given the unique
 189         /// dependence tag number (FP or int).
 190         void printReg(std::ostream &os, int reg) const;
 191
 192         std::string
 193         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 194     };
 195 }};
 196
 197 output decoder {{
 198     void
 199     AlphaStaticInst::printReg(std::ostream &os, int reg) const
 200     {
 201         if (reg < FP_Base_DepTag) {
 202             ccprintf(os, "r%d", reg);
 203         }
 204         else {
 205             ccprintf(os, "f%d", reg - FP_Base_DepTag);
 206         }
 207     }
 208
 209     std::string
 210     AlphaStaticInst::generateDisassembly(Addr pc,
 211                                          const SymbolTable *symtab) const
 212     {
 213         std::stringstream ss;
 214
 215         ccprintf(ss, "%-10s ", mnemonic);
 216
 217         // just print the first two source regs... if there's
 218         // a third one, it's a read-modify-write dest (Rc),
 219         // e.g. for CMOVxx
 220         if (_numSrcRegs > 0) {
 221             printReg(ss, _srcRegIdx[0]);
 222         }
 223         if (_numSrcRegs > 1) {
 224             ss << ",";
 225             printReg(ss, _srcRegIdx[1]);
 226         }
 227
 228         // just print the first dest... if there's a second one,
 229         // it's generally implicit
 230         if (_numDestRegs > 0) {
 231             if (_numSrcRegs > 0)
 232                 ss << ",";
 233             printReg(ss, _destRegIdx[0]);
 234         }
 235
 236         return ss.str();
 237     }
 238 }};
 239
 240 // Declarations for execute() methods.
 241 def template BasicExecDeclare {{
 242     Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 243 }};
 244
 245 // Basic instruction class declaration template.
 246 def template BasicDeclare {{
 247     /**
 248      * Static instruction class for "%(mnemonic)s".
 249      */
 250     class %(class_name)s : public %(base_class)s
 251     {
 252       public:
 253         /// Constructor.
 254         %(class_name)s(MachInst machInst);
 255
 256         %(BasicExecDeclare)s
 257     };
 258 }};
 259
 260 // Basic instruction class constructor template.
 261 def template BasicConstructor {{
 262     inline %(class_name)s::%(class_name)s(MachInst machInst)
 263          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
 264     {
 265         %(constructor)s;
 266     }
 267 }};
 268
 269 // Basic instruction class execute method template.
 270 def template BasicExecute {{
 271     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 272                                   Trace::InstRecord *traceData) const
 273     {
 274         Fault fault = No_Fault;
 275
 276         %(fp_enable_check)s;
 277         %(op_decl)s;
 278         %(op_rd)s;
 279         %(code)s;
 280
 281         if (fault == No_Fault) {
 282             %(op_wb)s;
 283         }
 284
 285         return fault;
 286     }
 287 }};
 288
 289 // Basic decode template.
 290 def template BasicDecode {{
 291     return new %(class_name)s(machInst);
 292 }};
 293
 294 // Basic decode template, passing mnemonic in as string arg to constructor.
 295 def template BasicDecodeWithMnemonic {{
 296     return new %(class_name)s("%(mnemonic)s", machInst);
 297 }};
 298
 299 // The most basic instruction format... used only for a few misc. insts
 300 def format BasicOperate(code, *flags) {{
 301     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
 302     header_output = BasicDeclare.subst(iop)
 303     decoder_output = BasicConstructor.subst(iop)
 304     decode_block = BasicDecode.subst(iop)
 305     exec_output = BasicExecute.subst(iop)
 306 }};
 307
 308
 309
 310 ////////////////////////////////////////////////////////////////////
 311 //
 312 // Nop
 313 //
 314
 315 output header {{
 316     /**
 317      * Static instruction class for no-ops.  This is a leaf class.
 318      */
 319     class Nop : public AlphaStaticInst
 320     {
 321         /// Disassembly of original instruction.
 322         const std::string originalDisassembly;
 323
 324       public:
 325         /// Constructor
 326         Nop(const std::string _originalDisassembly, MachInst _machInst)
 327             : AlphaStaticInst("nop", _machInst, No_OpClass),
 328               originalDisassembly(_originalDisassembly)
 329         {
 330             flags[IsNop] = true;
 331         }
 332
 333         ~Nop() { }
 334
 335         std::string
 336         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 337
 338         %(BasicExecDeclare)s
 339     };
 340 }};
 341
 342 output decoder {{
 343     std::string Nop::generateDisassembly(Addr pc,
 344                                          const SymbolTable *symtab) const
 345     {
 346 #ifdef SS_COMPATIBLE_DISASSEMBLY
 347         return originalDisassembly;
 348 #else
 349         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 350 #endif
 351     }
 352
 353     /// Helper function for decoding nops.  Substitute Nop object
 354     /// for original inst passed in as arg (and delete latter).
 355     inline
 356     AlphaStaticInst *
 357     makeNop(AlphaStaticInst *inst)
 358     {
 359         AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
 360         delete inst;
 361         return nop;
 362     }
 363 }};
 364
 365 output exec {{
 366     Fault
 367     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
 368     {
 369         return No_Fault;
 370     }
 371 }};
 372
 373 // integer & FP operate instructions use Rc as dest, so check for
 374 // Rc == 31 to detect nops
 375 def template OperateNopCheckDecode {{
 376  {
 377      AlphaStaticInst *i = new %(class_name)s(machInst);
 378      if (RC == 31) {
 379          i = makeNop(i);
 380      }
 381      return i;
 382  }
 383 }};
 384
 385 // Like BasicOperate format, but generates NOP if RC/FC == 31
 386 def format BasicOperateWithNopCheck(code, *opt_args) {{
 387     iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
 388                         opt_args)
 389     header_output = BasicDeclare.subst(iop)
 390     decoder_output = BasicConstructor.subst(iop)
 391     decode_block = OperateNopCheckDecode.subst(iop)
 392     exec_output = BasicExecute.subst(iop)
 393 }};
 394
 395
 396 ////////////////////////////////////////////////////////////////////
 397 //
 398 // Integer operate instructions
 399 //
 400
 401 output header {{
 402     /**
 403      * Base class for integer immediate instructions.
 404      */
 405     class IntegerImm : public AlphaStaticInst
 406     {
 407       protected:
 408         /// Immediate operand value (unsigned 8-bit int).
 409         uint8_t imm;
 410
 411         /// Constructor
 412         IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
 413             : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
 414         {
 415         }
 416
 417         std::string
 418         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 419     };
 420 }};
 421
 422 output decoder {{
 423     std::string
 424     IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 425     {
 426         std::stringstream ss;
 427
 428         ccprintf(ss, "%-10s ", mnemonic);
 429
 430         // just print the first source reg... if there's
 431         // a second one, it's a read-modify-write dest (Rc),
 432         // e.g. for CMOVxx
 433         if (_numSrcRegs > 0) {
 434             printReg(ss, _srcRegIdx[0]);
 435             ss << ",";
 436         }
 437
 438         ss << (int)imm;
 439
 440         if (_numDestRegs > 0) {
 441             ss << ",";
 442             printReg(ss, _destRegIdx[0]);
 443         }
 444
 445         return ss.str();
 446     }
 447 }};
 448
 449
 450 def template RegOrImmDecode {{
 451  {
 452      AlphaStaticInst *i =
 453          (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
 454                : (AlphaStaticInst *)new %(class_name)s(machInst);
 455      if (RC == 31) {
 456          i = makeNop(i);
 457      }
 458      return i;
 459  }
 460 }};
 461
 462 // Primary format for integer operate instructions:
 463 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
 464 // - Generates NOP if RC == 31.
 465 def format IntegerOperate(code, *opt_flags) {{
 466     # If the code block contains 'Rb_or_imm', we define two instructions,
 467     # one using 'Rb' and one using 'imm', and have the decoder select
 468     # the right one.
 469     uses_imm = (code.find('Rb_or_imm') != -1)
 470     if uses_imm:
 471         orig_code = code
 472         # base code is reg version:
 473         # rewrite by substituting 'Rb' for 'Rb_or_imm'
 474         code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
 475         # generate immediate version by substituting 'imm'
 476         # note that imm takes no extenstion, so we extend
 477         # the regexp to replace any extension as well
 478         imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
 479
 480     # generate declaration for register version
 481     cblk = CodeBlock(code)
 482     iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
 483     header_output = BasicDeclare.subst(iop)
 484     decoder_output = BasicConstructor.subst(iop)
 485     exec_output = BasicExecute.subst(iop)
 486
 487     if uses_imm:
 488         # append declaration for imm version
 489         imm_cblk = CodeBlock(imm_code)
 490         imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
 491                                 opt_flags)
 492         header_output += BasicDeclare.subst(imm_iop)
 493         decoder_output += BasicConstructor.subst(imm_iop)
 494         exec_output += BasicExecute.subst(imm_iop)
 495         # decode checks IMM bit to pick correct version
 496         decode_block = RegOrImmDecode.subst(iop)
 497     else:
 498         # no imm version: just check for nop
 499         decode_block = OperateNopCheckDecode.subst(iop)
 500 }};
 501
 502
 503 ////////////////////////////////////////////////////////////////////
 504 //
 505 // Floating-point instructions
 506 //
 507 //      Note that many FP-type instructions which do not support all the
 508 //      various rounding & trapping modes use the simpler format
 509 //      BasicOperateWithNopCheck.
 510 //
 511
 512 output exec {{
 513     /// Check "FP enabled" machine status bit.  Called when executing any FP
 514     /// instruction in full-system mode.
 515     /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
 516     /// if not.  Non-full-system mode: always returns No_Fault.
 517 #ifdef FULL_SYSTEM
 518     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
 519     {
 520         Fault fault = No_Fault; // dummy... this ipr access should not fault
 521         if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
 522             fault = Fen_Fault;
 523         }
 524         return fault;
 525     }
 526 #else
 527     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
 528     {
 529         return No_Fault;
 530     }
 531 #endif
 532 }};
 533
 534 output header {{
 535     /**
 536      * Base class for general floating-point instructions.  Includes
 537      * support for various Alpha rounding and trapping modes.  Only FP
 538      * instructions that require this support are derived from this
 539      * class; the rest derive directly from AlphaStaticInst.
 540      */
 541     class AlphaFP : public  AlphaStaticInst
 542     {
 543       public:
 544         /// Alpha FP rounding modes.
 545         enum RoundingMode {
 546             Chopped = 0,        ///< round toward zero
 547             Minus_Infinity = 1, ///< round toward minus infinity
 548             Normal = 2,         ///< round to nearest (default)
 549             Dynamic = 3,        ///< use FPCR setting (in instruction)
 550             Plus_Infinity = 3   ///< round to plus inifinity (in FPCR)
 551         };
 552
 553         /// Alpha FP trapping modes.
 554         /// For instructions that produce integer results, the
 555         /// "Underflow Enable" modes really mean "Overflow Enable", and
 556         /// the assembly modifier is V rather than U.
 557         enum TrappingMode {
 558             /// default: nothing enabled
 559             Imprecise = 0,                 ///< no modifier
 560             /// underflow/overflow traps enabled, inexact disabled
 561             Underflow_Imprecise = 1,       ///< /U or /V
 562             Underflow_Precise = 5,         ///< /SU or /SV
 563             /// underflow/overflow and inexact traps enabled
 564             Underflow_Inexact_Precise = 7  ///< /SUI or /SVI
 565         };
 566
 567       protected:
 568 #if defined(linux)
 569         static const int alphaToC99RoundingMode[];
 570 #endif
 571
 572         /// Map enum RoundingMode values to disassembly suffixes.
 573         static const char *roundingModeSuffix[];
 574         /// Map enum TrappingMode values to FP disassembly suffixes.
 575         static const char *fpTrappingModeSuffix[];
 576         /// Map enum TrappingMode values to integer disassembly suffixes.
 577         static const char *intTrappingModeSuffix[];
 578
 579         /// This instruction's rounding mode.
 580         RoundingMode roundingMode;
 581         /// This instruction's trapping mode.
 582         TrappingMode trappingMode;
 583
 584         /// Constructor
 585         AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
 586             : AlphaStaticInst(mnem, _machInst, __opClass),
 587               roundingMode((enum RoundingMode)FP_ROUNDMODE),
 588               trappingMode((enum TrappingMode)FP_TRAPMODE)
 589         {
 590             if (trappingMode != Imprecise) {
 591                 warn("precise FP traps unimplemented\n");
 592             }
 593         }
 594
 595 #if defined(linux)
 596         int getC99RoundingMode(uint64_t fpcr_val) const;
 597 #endif
 598
 599         // This differs from the AlphaStaticInst version only in
 600         // printing suffixes for non-default rounding & trapping modes.
 601         std::string
 602         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 603     };
 604
 605 }};
 606
 607
 608 def template FloatingPointDecode {{
 609  {
 610      bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
 611                   && FP_ROUNDMODE == AlphaFP::Normal);
 612      AlphaStaticInst *i =
 613          fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
 614                 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
 615
 616      if (FC == 31) {
 617          i = makeNop(i);
 618      }
 619
 620      return i;
 621  }
 622 }};
 623
 624 output decoder {{
 625 #if defined(linux)
 626     int
 627     AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
 628     {
 629         if (roundingMode == Dynamic) {
 630             return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
 631         }
 632         else {
 633             return alphaToC99RoundingMode[roundingMode];
 634         }
 635     }
 636 #endif
 637
 638     std::string
 639     AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 640     {
 641         std::string mnem_str(mnemonic);
 642
 643 #ifndef SS_COMPATIBLE_DISASSEMBLY
 644         std::string suffix("");
 645         suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
 646                    ? fpTrappingModeSuffix[trappingMode]
 647                    : intTrappingModeSuffix[trappingMode]);
 648         suffix += roundingModeSuffix[roundingMode];
 649
 650         if (suffix != "") {
 651             mnem_str = csprintf("%s/%s", mnemonic, suffix);
 652         }
 653 #endif
 654
 655         std::stringstream ss;
 656         ccprintf(ss, "%-10s ", mnem_str.c_str());
 657
 658         // just print the first two source regs... if there's
 659         // a third one, it's a read-modify-write dest (Rc),
 660         // e.g. for CMOVxx
 661         if (_numSrcRegs > 0) {
 662             printReg(ss, _srcRegIdx[0]);
 663         }
 664         if (_numSrcRegs > 1) {
 665             ss << ",";
 666             printReg(ss, _srcRegIdx[1]);
 667         }
 668
 669         // just print the first dest... if there's a second one,
 670         // it's generally implicit
 671         if (_numDestRegs > 0) {
 672             if (_numSrcRegs > 0)
 673                 ss << ",";
 674             printReg(ss, _destRegIdx[0]);
 675         }
 676
 677         return ss.str();
 678     }
 679
 680 #if defined(linux)
 681     const int AlphaFP::alphaToC99RoundingMode[] = {
 682         FE_TOWARDZERO,  // Chopped
 683         FE_DOWNWARD,    // Minus_Infinity
 684         FE_TONEAREST,   // Normal
 685         FE_UPWARD       // Dynamic in inst, Plus_Infinity in FPCR
 686     };
 687 #endif
 688
 689     const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
 690     // mark invalid trapping modes, but don't fail on them, because
 691     // you could decode anything on a misspeculated path
 692     const char *AlphaFP::fpTrappingModeSuffix[] =
 693         { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
 694     const char *AlphaFP::intTrappingModeSuffix[] =
 695         { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
 696 }};
 697
 698 // General format for floating-point operate instructions:
 699 // - Checks trapping and rounding mode flags.  Trapping modes
 700 //   currently unimplemented (will fail).
 701 // - Generates NOP if FC == 31.
 702 def format FloatingPointOperate(code, *opt_args) {{
 703     iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
 704     decode_block = FloatingPointDecode.subst(iop)
 705
 706     fast_iop = InstObjParams(name, Name + 'Fast', 'AlphaFP',
 707                              CodeBlock(code), opt_args)
 708     header_output = BasicDeclare.subst(fast_iop)
 709     decoder_output = BasicConstructor.subst(fast_iop)
 710     exec_output = BasicExecute.subst(fast_iop)
 711
 712     gen_code_prefix = r'''
 713 #if defined(linux)
 714     fesetround(getC99RoundingMode(xc->readFpcr()));
 715 #endif
 716 '''
 717     gen_code_suffix = r'''
 718 #if defined(linux)
 719     fesetround(FE_TONEAREST);
 720 #endif
 721 '''
 722
 723     gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
 724     CodeBlock(gen_code_prefix + code + gen_code_suffix), opt_args)
 725     header_output += BasicDeclare.subst(gen_iop)
 726     decoder_output += BasicConstructor.subst(gen_iop)
 727     exec_output += BasicExecute.subst(gen_iop)
 728 }};
 729
 730
 731 ////////////////////////////////////////////////////////////////////
 732 //
 733 // Memory-format instructions: LoadAddress, Load, Store
 734 //
 735
 736 output header {{
 737     /**
 738      * Base class for general Alpha memory-format instructions.
 739      */
 740     class Memory : public AlphaStaticInst
 741     {
 742       protected:
 743
 744         /// Memory request flags.  See mem_req_base.hh.
 745         unsigned memAccessFlags;
 746         /// Pointer to EAComp object.
 747         const StaticInstPtr<AlphaISA> eaCompPtr;
 748         /// Pointer to MemAcc object.
 749         const StaticInstPtr<AlphaISA> memAccPtr;
 750
 751         /// Constructor
 752         Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
 753                StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
 754                StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
 755             : AlphaStaticInst(mnem, _machInst, __opClass),
 756               memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
 757         {
 758         }
 759
 760         std::string
 761         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 762
 763       public:
 764
 765         const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
 766         const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
 767     };
 768
 769     /**
 770      * Base class for memory-format instructions using a 32-bit
 771      * displacement (i.e. most of them).
 772      */
 773     class MemoryDisp32 : public Memory
 774     {
 775       protected:
 776         /// Displacement for EA calculation (signed).
 777         int32_t disp;
 778
 779         /// Constructor.
 780         MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
 781                      StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
 782                      StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
 783             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
 784               disp(MEMDISP)
 785         {
 786         }
 787     };
 788
 789
 790     /**
 791      * Base class for a few miscellaneous memory-format insts
 792      * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
 793      * None of these instructions has a destination register either.
 794      */
 795     class MemoryNoDisp : public Memory
 796     {
 797       protected:
 798         /// Constructor
 799         MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
 800                      StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
 801                      StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
 802             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
 803         {
 804         }
 805
 806         std::string
 807         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 808     };
 809 }};
 810
 811
 812 output decoder {{
 813     std::string
 814     Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 815     {
 816         return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
 817                         flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
 818     }
 819
 820     std::string
 821     MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 822     {
 823         return csprintf("%-10s (r%d)", mnemonic, RB);
 824     }
 825 }};
 826
 827 def format LoadAddress(code) {{
 828     iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
 829     header_output = BasicDeclare.subst(iop)
 830     decoder_output = BasicConstructor.subst(iop)
 831     decode_block = BasicDecode.subst(iop)
 832     exec_output = BasicExecute.subst(iop)
 833 }};
 834
 835
 836 def template LoadStoreDeclare {{
 837     /**
 838      * Static instruction class for "%(mnemonic)s".
 839      */
 840     class %(class_name)s : public %(base_class)s
 841     {
 842       protected:
 843
 844         /**
 845          * "Fake" effective address computation class for "%(mnemonic)s".
 846          */
 847         class EAComp : public %(base_class)s
 848         {
 849           public:
 850             /// Constructor
 851             EAComp(MachInst machInst);
 852
 853             %(BasicExecDeclare)s
 854         };
 855
 856         /**
 857          * "Fake" memory access instruction class for "%(mnemonic)s".
 858          */
 859         class MemAcc : public %(base_class)s
 860         {
 861           public:
 862             /// Constructor
 863             MemAcc(MachInst machInst);
 864
 865             %(BasicExecDeclare)s
 866         };
 867
 868       public:
 869
 870         /// Constructor.
 871         %(class_name)s(MachInst machInst);
 872
 873         %(BasicExecDeclare)s
 874     };
 875 }};
 876
 877 def template LoadStoreConstructor {{
 878     /** TODO: change op_class to AddrGenOp or something (requires
 879      * creating new member of OpClass enum in op_class.hh, updating
 880      * config files, etc.). */
 881     inline %(class_name)s::EAComp::EAComp(MachInst machInst)
 882         : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
 883     {
 884         %(ea_constructor)s;
 885     }
 886
 887     inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
 888         : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
 889     {
 890         %(memacc_constructor)s;
 891     }
 892
 893     inline %(class_name)s::%(class_name)s(MachInst machInst)
 894          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 895                           new EAComp(machInst), new MemAcc(machInst))
 896     {
 897         %(constructor)s;
 898     }
 899 }};
 900
 901
 902 def template EACompExecute {{
 903     Fault
 904     %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
 905                                    Trace::InstRecord *traceData) const
 906     {
 907         Addr EA;
 908         Fault fault = No_Fault;
 909
 910         %(fp_enable_check)s;
 911         %(op_decl)s;
 912         %(op_rd)s;
 913         %(code)s;
 914
 915         if (fault == No_Fault) {
 916             %(op_wb)s;
 917             xc->setEA(EA);
 918         }
 919
 920         return fault;
 921     }
 922 }};
 923
 924 def template MemAccExecute {{
 925     Fault
 926     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
 927                                    Trace::InstRecord *traceData) const
 928     {
 929         Addr EA;
 930         Fault fault = No_Fault;
 931
 932         %(fp_enable_check)s;
 933         %(op_decl)s;
 934         %(op_nonmem_rd)s;
 935         EA = xc->getEA();
 936
 937         if (fault == No_Fault) {
 938             %(op_mem_rd)s;
 939             %(code)s;
 940         }
 941
 942         if (fault == No_Fault) {
 943             %(op_mem_wb)s;
 944         }
 945
 946         if (fault == No_Fault) {
 947             %(postacc_code)s;
 948         }
 949
 950         if (fault == No_Fault) {
 951             %(op_nonmem_wb)s;
 952         }
 953
 954         return fault;
 955     }
 956 }};
 957
 958
 959 def template LoadStoreExecute {{
 960     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 961                                   Trace::InstRecord *traceData) const
 962     {
 963         Addr EA;
 964         Fault fault = No_Fault;
 965
 966         %(fp_enable_check)s;
 967         %(op_decl)s;
 968         %(op_nonmem_rd)s;
 969         %(ea_code)s;
 970
 971         if (fault == No_Fault) {
 972             %(op_mem_rd)s;
 973             %(memacc_code)s;
 974         }
 975
 976         if (fault == No_Fault) {
 977             %(op_mem_wb)s;
 978         }
 979
 980         if (fault == No_Fault) {
 981             %(postacc_code)s;
 982         }
 983
 984         if (fault == No_Fault) {
 985             %(op_nonmem_wb)s;
 986         }
 987
 988         return fault;
 989     }
 990 }};
 991
 992
 993 def template PrefetchExecute {{
 994     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
 995                                   Trace::InstRecord *traceData) const
 996     {
 997         Addr EA;
 998         Fault fault = No_Fault;
 999
1000         %(fp_enable_check)s;
1001         %(op_decl)s;
1002         %(op_nonmem_rd)s;
1003         %(ea_code)s;
1004
1005         if (fault == No_Fault) {
1006             xc->prefetch(EA, memAccessFlags);
1007         }
1008
1009         return No_Fault;
1010     }
1011 }};
1012
1013 // load instructions use Ra as dest, so check for
1014 // Ra == 31 to detect nops
1015 def template LoadNopCheckDecode {{
1016  {
1017      AlphaStaticInst *i = new %(class_name)s(machInst);
1018      if (RA == 31) {
1019          i = makeNop(i);
1020      }
1021      return i;
1022  }
1023 }};
1024
1025
1026 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1027 def template LoadPrefetchCheckDecode {{
1028  {
1029      if (RA != 31) {
1030          return new %(class_name)s(machInst);
1031      }
1032      else {
1033          return new %(class_name)sPrefetch(machInst);
1034      }
1035  }
1036 }};
1037
1038
1039 let {{
1040 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1041                   base_class = 'MemoryDisp32', flags = [],
1042                   decode_template = BasicDecode,
1043                   exec_template = LoadStoreExecute):
1044     # Segregate flags into instruction flags (handled by InstObjParams)
1045     # and memory access flags (handled here).
1046
1047     # Would be nice to autogenerate this list, but oh well.
1048     valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1049     mem_flags =  [f for f in flags if f in valid_mem_flags]
1050     inst_flags = [f for f in flags if f not in valid_mem_flags]
1051
1052     # add hook to get effective addresses into execution trace output.
1053     ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
1054
1055     # generate code block objects
1056     ea_cblk = CodeBlock(ea_code)
1057     memacc_cblk = CodeBlock(memacc_code)
1058     postacc_cblk = CodeBlock(postacc_code)
1059
1060     # Some CPU models execute the memory operation as an atomic unit,
1061     # while others want to separate them into an effective address
1062     # computation and a memory access operation.  As a result, we need
1063     # to generate three StaticInst objects.  Note that the latter two
1064     # are nested inside the larger "atomic" one.
1065
1066     # generate InstObjParams for EAComp object
1067     ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
1068
1069     # generate InstObjParams for MemAcc object
1070     memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
1071     # in the split execution model, the MemAcc portion is responsible
1072     # for the post-access code.
1073     memacc_iop.postacc_code = postacc_cblk.code
1074
1075     # generate InstObjParams for unified execution
1076     cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1077     iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1078
1079     iop.ea_constructor = ea_cblk.constructor
1080     iop.ea_code = ea_cblk.code
1081     iop.memacc_constructor = memacc_cblk.constructor
1082     iop.memacc_code = memacc_cblk.code
1083     iop.postacc_code = postacc_cblk.code
1084
1085     if mem_flags:
1086         s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
1087         iop.constructor += s
1088         memacc_iop.constructor += s
1089
1090     # (header_output, decoder_output, decode_block, exec_output)
1091     return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
1092             decode_template.subst(iop),
1093             EACompExecute.subst(ea_iop)
1094             + MemAccExecute.subst(memacc_iop)
1095             + exec_template.subst(iop))
1096 }};
1097
1098
1099 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1100     (header_output, decoder_output, decode_block, exec_output) = \
1101         LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1102                       decode_template = LoadNopCheckDecode)
1103 }};
1104
1105
1106 // Note that the flags passed in apply only to the prefetch version
1107 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1108     # declare the load instruction object and generate the decode block
1109     (header_output, decoder_output, decode_block, exec_output) = \
1110         LoadStoreBase(name, Name, ea_code, memacc_code,
1111                       decode_template = LoadPrefetchCheckDecode)
1112
1113     # Declare the prefetch instruction object.
1114
1115     # convert flags from tuple to list to make them mutable
1116     pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
1117
1118     (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
1119         LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1120                       flags = pf_flags, exec_template = PrefetchExecute)
1121
1122     header_output += pf_header_output
1123     decoder_output += pf_decoder_output
1124     exec_output += pf_exec_output
1125 }};
1126
1127
1128 def format Store(ea_code, memacc_code, *flags) {{
1129     (header_output, decoder_output, decode_block, exec_output) = \
1130         LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags)
1131 }};
1132
1133
1134 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1135     (header_output, decoder_output, decode_block, exec_output) = \
1136         LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1137                       flags = flags)
1138 }};
1139
1140
1141 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1142 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1143     (header_output, decoder_output, decode_block, exec_output) = \
1144         LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1145                       base_class = 'MemoryNoDisp')
1146 }};
1147
1148
1149 ////////////////////////////////////////////////////////////////////
1150 //
1151 // Control transfer instructions
1152 //
1153
1154 output header {{
1155
1156     /**
1157      * Base class for instructions whose disassembly is not purely a
1158      * function of the machine instruction (i.e., it depends on the
1159      * PC).  This class overrides the disassemble() method to check
1160      * the PC and symbol table values before re-using a cached
1161      * disassembly string.  This is necessary for branches and jumps,
1162      * where the disassembly string includes the target address (which
1163      * may depend on the PC and/or symbol table).
1164      */
1165     class PCDependentDisassembly : public AlphaStaticInst
1166     {
1167       protected:
1168         /// Cached program counter from last disassembly
1169         mutable Addr cachedPC;
1170         /// Cached symbol table pointer from last disassembly
1171         mutable const SymbolTable *cachedSymtab;
1172
1173         /// Constructor
1174         PCDependentDisassembly(const char *mnem, MachInst _machInst,
1175                                OpClass __opClass)
1176             : AlphaStaticInst(mnem, _machInst, __opClass),
1177               cachedPC(0), cachedSymtab(0)
1178         {
1179         }
1180
1181         const std::string &
1182         disassemble(Addr pc, const SymbolTable *symtab) const;
1183     };
1184
1185     /**
1186      * Base class for branches (PC-relative control transfers),
1187      * conditional or unconditional.
1188      */
1189     class Branch : public PCDependentDisassembly
1190     {
1191       protected:
1192         /// Displacement to target address (signed).
1193         int32_t disp;
1194
1195         /// Constructor.
1196         Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1197             : PCDependentDisassembly(mnem, _machInst, __opClass),
1198               disp(BRDISP << 2)
1199         {
1200         }
1201
1202         Addr branchTarget(Addr branchPC) const;
1203
1204         std::string
1205         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1206     };
1207
1208     /**
1209      * Base class for jumps (register-indirect control transfers).  In
1210      * the Alpha ISA, these are always unconditional.
1211      */
1212     class Jump : public PCDependentDisassembly
1213     {
1214       protected:
1215
1216         /// Displacement to target address (signed).
1217         int32_t disp;
1218
1219       public:
1220         /// Constructor
1221         Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1222             : PCDependentDisassembly(mnem, _machInst, __opClass),
1223               disp(BRDISP)
1224         {
1225         }
1226
1227         Addr branchTarget(ExecContext *xc) const;
1228
1229         std::string
1230         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1231     };
1232 }};
1233
1234 output decoder {{
1235     Addr
1236     Branch::branchTarget(Addr branchPC) const
1237     {
1238         return branchPC + 4 + disp;
1239     }
1240
1241     Addr
1242     Jump::branchTarget(ExecContext *xc) const
1243     {
1244         Addr NPC = xc->readPC() + 4;
1245         uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
1246         return (Rb & ~3) | (NPC & 1);
1247     }
1248
1249     const std::string &
1250     PCDependentDisassembly::disassemble(Addr pc,
1251                                         const SymbolTable *symtab) const
1252     {
1253         if (!cachedDisassembly ||
1254             pc != cachedPC || symtab != cachedSymtab)
1255         {
1256             if (cachedDisassembly)
1257                 delete cachedDisassembly;
1258
1259             cachedDisassembly =
1260                 new std::string(generateDisassembly(pc, symtab));
1261             cachedPC = pc;
1262             cachedSymtab = symtab;
1263         }
1264
1265         return *cachedDisassembly;
1266     }
1267
1268     std::string
1269     Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1270     {
1271         std::stringstream ss;
1272
1273         ccprintf(ss, "%-10s ", mnemonic);
1274
1275         // There's only one register arg (RA), but it could be
1276         // either a source (the condition for conditional
1277         // branches) or a destination (the link reg for
1278         // unconditional branches)
1279         if (_numSrcRegs > 0) {
1280             printReg(ss, _srcRegIdx[0]);
1281             ss << ",";
1282         }
1283         else if (_numDestRegs > 0) {
1284             printReg(ss, _destRegIdx[0]);
1285             ss << ",";
1286         }
1287
1288 #ifdef SS_COMPATIBLE_DISASSEMBLY
1289         if (_numSrcRegs == 0 && _numDestRegs == 0) {
1290             printReg(ss, 31);
1291             ss << ",";
1292         }
1293 #endif
1294
1295         Addr target = pc + 4 + disp;
1296
1297         std::string str;
1298         if (symtab && symtab->findSymbol(target, str))
1299             ss << str;
1300         else
1301             ccprintf(ss, "0x%x", target);
1302
1303         return ss.str();
1304     }
1305
1306     std::string
1307     Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1308     {
1309         std::stringstream ss;
1310
1311         ccprintf(ss, "%-10s ", mnemonic);
1312
1313 #ifdef SS_COMPATIBLE_DISASSEMBLY
1314         if (_numDestRegs == 0) {
1315             printReg(ss, 31);
1316             ss << ",";
1317         }
1318 #endif
1319
1320         if (_numDestRegs > 0) {
1321             printReg(ss, _destRegIdx[0]);
1322             ss << ",";
1323         }
1324
1325         ccprintf(ss, "(r%d)", RB);
1326
1327         return ss.str();
1328     }
1329 }};
1330
1331 def template JumpOrBranchDecode {{
1332     return (RA == 31)
1333         ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1334         : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1335 }};
1336
1337 def format CondBranch(code) {{
1338     code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1339     iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1340                         ('IsDirectControl', 'IsCondControl'))
1341     header_output = BasicDeclare.subst(iop)
1342     decoder_output = BasicConstructor.subst(iop)
1343     decode_block = BasicDecode.subst(iop)
1344     exec_output = BasicExecute.subst(iop)
1345 }};
1346
1347 let {{
1348 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1349     # Declare basic control transfer w/o link (i.e. link reg is R31)
1350     nolink_code = 'NPC = %s;\n' % npc_expr
1351     nolink_iop = InstObjParams(name, Name, base_class,
1352                                CodeBlock(nolink_code), flags)
1353     header_output = BasicDeclare.subst(nolink_iop)
1354     decoder_output = BasicConstructor.subst(nolink_iop)
1355     exec_output = BasicExecute.subst(nolink_iop)
1356
1357     # Generate declaration of '*AndLink' version, append to decls
1358     link_code = 'Ra = NPC & ~3;\n' + nolink_code
1359     link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1360                              CodeBlock(link_code), flags)
1361     header_output += BasicDeclare.subst(link_iop)
1362     decoder_output += BasicConstructor.subst(link_iop)
1363     exec_output += BasicExecute.subst(link_iop)
1364
1365     # need to use link_iop for the decode template since it is expecting
1366     # the shorter version of class_name (w/o "AndLink")
1367
1368     return (header_output, decoder_output,
1369             JumpOrBranchDecode.subst(nolink_iop), exec_output)
1370 }};
1371
1372 def format UncondBranch(*flags) {{
1373     flags += ('IsUncondControl', 'IsDirectControl')
1374     (header_output, decoder_output, decode_block, exec_output) = \
1375         UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1376 }};
1377
1378 def format Jump(*flags) {{
1379     flags += ('IsUncondControl', 'IsIndirectControl')
1380     (header_output, decoder_output, decode_block, exec_output) = \
1381         UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1382 }};
1383
1384
1385 ////////////////////////////////////////////////////////////////////
1386 //
1387 // PAL calls
1388 //
1389
1390 output header {{
1391     /**
1392      * Base class for emulated call_pal calls (used only in
1393      * non-full-system mode).
1394      */
1395     class EmulatedCallPal : public AlphaStaticInst
1396     {
1397       protected:
1398
1399         /// Constructor.
1400         EmulatedCallPal(const char *mnem, MachInst _machInst,
1401                         OpClass __opClass)
1402             : AlphaStaticInst(mnem, _machInst, __opClass)
1403         {
1404         }
1405
1406         std::string
1407         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1408     };
1409 }};
1410
1411 output decoder {{
1412     std::string
1413     EmulatedCallPal::generateDisassembly(Addr pc,
1414                                          const SymbolTable *symtab) const
1415     {
1416 #ifdef SS_COMPATIBLE_DISASSEMBLY
1417         return csprintf("%s %s", "call_pal", mnemonic);
1418 #else
1419         return csprintf("%-10s %s", "call_pal", mnemonic);
1420 #endif
1421     }
1422 }};
1423
1424 def format EmulatedCallPal(code, *flags) {{
1425     iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
1426     header_output = BasicDeclare.subst(iop)
1427     decoder_output = BasicConstructor.subst(iop)
1428     decode_block = BasicDecode.subst(iop)
1429     exec_output = BasicExecute.subst(iop)
1430 }};
1431
1432 output header {{
1433     /**
1434      * Base class for full-system-mode call_pal instructions.
1435      * Probably could turn this into a leaf class and get rid of the
1436      * parser template.
1437      */
1438     class CallPalBase : public AlphaStaticInst
1439     {
1440       protected:
1441         int palFunc;    ///< Function code part of instruction
1442         int palOffset;  ///< Target PC, offset from IPR_PAL_BASE
1443         bool palValid;  ///< is the function code valid?
1444         bool palPriv;   ///< is this call privileged?
1445
1446         /// Constructor.
1447         CallPalBase(const char *mnem, MachInst _machInst,
1448                     OpClass __opClass);
1449
1450         std::string
1451         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1452     };
1453 }};
1454
1455 output decoder {{
1456     inline
1457     CallPalBase::CallPalBase(const char *mnem, MachInst _machInst,
1458                              OpClass __opClass)
1459         : AlphaStaticInst(mnem, _machInst, __opClass),
1460         palFunc(PALFUNC)
1461     {
1462         // From the 21164 HRM (paraphrased):
1463         // Bit 7 of the function code (mask 0x80) indicates
1464         // whether the call is privileged (bit 7 == 0) or
1465         // unprivileged (bit 7 == 1).  The privileged call table
1466         // starts at 0x2000, the unprivielged call table starts at
1467         // 0x3000.  Bits 5-0 (mask 0x3f) are used to calculate the
1468         // offset.
1469         const int palPrivMask = 0x80;
1470         const int palOffsetMask = 0x3f;
1471
1472         // Pal call is invalid unless all other bits are 0
1473         palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
1474         palPriv = ((machInst & palPrivMask) == 0);
1475         int shortPalFunc = (machInst & palOffsetMask);
1476         // Add 1 to base to set pal-mode bit
1477         palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
1478     }
1479
1480     std::string
1481     CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1482     {
1483         return csprintf("%-10s %#x", "call_pal", palFunc);
1484     }
1485 }};
1486
1487 def format CallPal(code, *flags) {{
1488     iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
1489     header_output = BasicDeclare.subst(iop)
1490     decoder_output = BasicConstructor.subst(iop)
1491     decode_block = BasicDecode.subst(iop)
1492     exec_output = BasicExecute.subst(iop)
1493 }};
1494
1495 ////////////////////////////////////////////////////////////////////
1496 //
1497 // hw_ld, hw_st
1498 //
1499
1500 output header {{
1501     /**
1502      * Base class for hw_ld and hw_st.
1503      */
1504     class HwLoadStore : public Memory
1505     {
1506       protected:
1507
1508         /// Displacement for EA calculation (signed).
1509         int16_t disp;
1510
1511         /// Constructor
1512         HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
1513                     StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
1514                     StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
1515
1516         std::string
1517         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1518     };
1519 }};
1520
1521
1522 output decoder {{
1523     inline
1524     HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
1525                              OpClass __opClass,
1526                              StaticInstPtr<AlphaISA> _eaCompPtr,
1527                              StaticInstPtr<AlphaISA> _memAccPtr)
1528         : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
1529         disp(HW_LDST_DISP)
1530     {
1531         memAccessFlags = 0;
1532         if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1533         if (HW_LDST_ALT)  memAccessFlags |= ALTMODE;
1534         if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1535         if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1536     }
1537
1538     std::string
1539     HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1540     {
1541 #ifdef SS_COMPATIBLE_DISASSEMBLY
1542         return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1543 #else
1544         // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1545         const char *lock_str =
1546             (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1547
1548         return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1549                         mnemonic, RA, disp, RB,
1550                         HW_LDST_PHYS ? ",PHYS" : "",
1551                         HW_LDST_ALT ? ",ALT" : "",
1552                         HW_LDST_QUAD ? ",QUAD" : "",
1553                         HW_LDST_VPTE ? ",VPTE" : "",
1554                         lock_str);
1555 #endif
1556     }
1557 }};
1558
1559 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1560     (header_output, decoder_output, decode_block, exec_output) = \
1561         LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1562                       flags = flags, base_class = 'HwLoadStore')
1563 }};
1564
1565
1566 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1567     (header_output, decoder_output, decode_block, exec_output) = \
1568         LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1569                       postacc_code, flags = flags, base_class = 'HwLoadStore')
1570 }};
1571
1572
1573 output header {{
1574     /**
1575      * Base class for hw_mfpr and hw_mtpr.
1576      */
1577     class HwMoveIPR : public AlphaStaticInst
1578     {
1579       protected:
1580         /// Index of internal processor register.
1581         int ipr_index;
1582
1583         /// Constructor
1584         HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1585             : AlphaStaticInst(mnem, _machInst, __opClass),
1586               ipr_index(HW_IPR_IDX)
1587         {
1588         }
1589
1590         std::string
1591         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1592     };
1593 }};
1594
1595 output decoder {{
1596     std::string
1597     HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1598     {
1599         if (_numSrcRegs > 0) {
1600             // must be mtpr
1601             return csprintf("%-10s r%d,IPR(%#x)",
1602                             mnemonic, RA, ipr_index);
1603         }
1604         else {
1605             // must be mfpr
1606             return csprintf("%-10s IPR(%#x),r%d",
1607                             mnemonic, ipr_index, RA);
1608         }
1609     }
1610 }};
1611
1612 def format HwMoveIPR(code) {{
1613     iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1614     header_output = BasicDeclare.subst(iop)
1615     decoder_output = BasicConstructor.subst(iop)
1616     decode_block = BasicDecode.subst(iop)
1617     exec_output = BasicExecute.subst(iop)
1618 }};
1619
1620
1621 ////////////////////////////////////////////////////////////////////
1622 //
1623 // Unimplemented instructions
1624 //
1625
1626 output header {{
1627     /**
1628      * Static instruction class for unimplemented instructions that
1629      * cause simulator termination.  Note that these are recognized
1630      * (legal) instructions that the simulator does not support; the
1631      * 'Unknown' class is used for unrecognized/illegal instructions.
1632      * This is a leaf class.
1633      */
1634     class FailUnimplemented : public AlphaStaticInst
1635     {
1636       public:
1637         /// Constructor
1638         FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1639             : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1640         {
1641             // don't call execute() (which panics) if we're on a
1642             // speculative path
1643             flags[IsNonSpeculative] = true;
1644         }
1645
1646         %(BasicExecDeclare)s
1647
1648         std::string
1649         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1650     };
1651
1652     /**
1653      * Base class for unimplemented instructions that cause a warning
1654      * to be printed (but do not terminate simulation).  This
1655      * implementation is a little screwy in that it will print a
1656      * warning for each instance of a particular unimplemented machine
1657      * instruction, not just for each unimplemented opcode.  Should
1658      * probably make the 'warned' flag a static member of the derived
1659      * class.
1660      */
1661     class WarnUnimplemented : public AlphaStaticInst
1662     {
1663       private:
1664         /// Have we warned on this instruction yet?
1665         mutable bool warned;
1666
1667       public:
1668         /// Constructor
1669         WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1670             : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1671         {
1672             // don't call execute() (which panics) if we're on a
1673             // speculative path
1674             flags[IsNonSpeculative] = true;
1675         }
1676
1677         %(BasicExecDeclare)s
1678
1679         std::string
1680         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1681     };
1682 }};
1683
1684 output decoder {{
1685     std::string
1686     FailUnimplemented::generateDisassembly(Addr pc,
1687                                            const SymbolTable *symtab) const
1688     {
1689         return csprintf("%-10s (unimplemented)", mnemonic);
1690     }
1691
1692     std::string
1693     WarnUnimplemented::generateDisassembly(Addr pc,
1694                                            const SymbolTable *symtab) const
1695     {
1696 #ifdef SS_COMPATIBLE_DISASSEMBLY
1697         return csprintf("%-10s", mnemonic);
1698 #else
1699         return csprintf("%-10s (unimplemented)", mnemonic);
1700 #endif
1701     }
1702 }};
1703
1704 output exec {{
1705     Fault
1706     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
1707                                Trace::InstRecord *traceData) const
1708     {
1709         panic("attempt to execute unimplemented instruction '%s' "
1710               "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1711         return Unimplemented_Opcode_Fault;
1712     }
1713
1714     Fault
1715     WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
1716                                Trace::InstRecord *traceData) const
1717     {
1718         if (!warned) {
1719             warn("instruction '%s' unimplemented\n", mnemonic);
1720             warned = true;
1721         }
1722
1723         return No_Fault;
1724     }
1725 }};
1726
1727
1728 def format FailUnimpl() {{
1729     iop = InstObjParams(name, 'FailUnimplemented')
1730     decode_block = BasicDecodeWithMnemonic.subst(iop)
1731 }};
1732
1733 def format WarnUnimpl() {{
1734     iop = InstObjParams(name, 'WarnUnimplemented')
1735     decode_block = BasicDecodeWithMnemonic.subst(iop)
1736 }};
1737
1738 output header {{
1739     /**
1740      * Static instruction class for unknown (illegal) instructions.
1741      * These cause simulator termination if they are executed in a
1742      * non-speculative mode.  This is a leaf class.
1743      */
1744     class Unknown : public AlphaStaticInst
1745     {
1746       public:
1747         /// Constructor
1748         Unknown(MachInst _machInst)
1749             : AlphaStaticInst("unknown", _machInst, No_OpClass)
1750         {
1751             // don't call execute() (which panics) if we're on a
1752             // speculative path
1753             flags[IsNonSpeculative] = true;
1754         }
1755
1756         %(BasicExecDeclare)s
1757
1758         std::string
1759         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
1760     };
1761 }};
1762
1763 ////////////////////////////////////////////////////////////////////
1764 //
1765 // Unknown instructions
1766 //
1767
1768 output decoder {{
1769     std::string
1770     Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1771     {
1772         return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1773                         "unknown", machInst, OPCODE);
1774     }
1775 }};
1776
1777 output exec {{
1778     Fault
1779     Unknown::execute(%(CPU_exec_context)s *xc,
1780                      Trace::InstRecord *traceData) const
1781     {
1782         panic("attempt to execute unknown instruction "
1783               "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1784         return Unimplemented_Opcode_Fault;
1785     }
1786 }};
1787
1788 def format Unknown() {{
1789     decode_block = 'return new Unknown(machInst);\n'
1790 }};
1791
1792 ////////////////////////////////////////////////////////////////////
1793 //
1794 // Utility functions for execute methods
1795 //
1796
1797 output exec {{
1798
1799     /// Return opa + opb, summing carry into third arg.
1800     inline uint64_t
1801     addc(uint64_t opa, uint64_t opb, int &carry)
1802     {
1803         uint64_t res = opa + opb;
1804         if (res < opa || res < opb)
1805             ++carry;
1806         return res;
1807     }
1808
1809     /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1810     /// product in res_hi and res_lo.
1811     inline void
1812     mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1813     {
1814         // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1815         uint64_t opa_hi = opa<63:32>;
1816         uint64_t opa_lo = opa<31:0>;
1817         uint64_t opb_hi = opb<63:32>;
1818         uint64_t opb_lo = opb<31:0>;
1819
1820         res_lo = opa_lo * opb_lo;
1821
1822         // The middle partial products logically belong in bit
1823         // positions 95 to 32.  Thus the lower 32 bits of each product
1824         // sum into the upper 32 bits of the low result, while the
1825         // upper 32 sum into the low 32 bits of the upper result.
1826         uint64_t partial1 = opa_hi * opb_lo;
1827         uint64_t partial2 = opa_lo * opb_hi;
1828
1829         uint64_t partial1_lo = partial1<31:0> << 32;
1830         uint64_t partial1_hi = partial1<63:32>;
1831         uint64_t partial2_lo = partial2<31:0> << 32;
1832         uint64_t partial2_hi = partial2<63:32>;
1833
1834         // Add partial1_lo and partial2_lo to res_lo, keeping track
1835         // of any carries out
1836         int carry_out = 0;
1837         res_lo = addc(partial1_lo, res_lo, carry_out);
1838         res_lo = addc(partial2_lo, res_lo, carry_out);
1839
1840         // Now calculate the high 64 bits...
1841         res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1842     }
1843
1844     /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1845     /// See Table 2-2 of Alpha AHB.
1846     inline int
1847     map_s(int old_exp)
1848     {
1849         int hibit = old_exp<7:>;
1850         int lobits = old_exp<6:0>;
1851
1852         if (hibit == 1) {
1853             return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1854         }
1855         else {
1856             return (lobits == 0) ? 0 : (0x380 | lobits);
1857         }
1858     }
1859
1860     /// Convert a 32-bit S-floating value to the equivalent 64-bit
1861     /// representation to be stored in an FP reg.
1862     inline uint64_t
1863     s_to_t(uint32_t s_val)
1864     {
1865         uint64_t tmp = s_val;
1866         return (tmp<31:> << 63 // sign bit
1867                 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1868                 | tmp<22:0> << 29); // fraction
1869     }
1870
1871     /// Convert a 64-bit T-floating value to the equivalent 32-bit
1872     /// S-floating representation to be stored in memory.
1873     inline int32_t
1874     t_to_s(uint64_t t_val)
1875     {
1876         return (t_val<63:62> << 30   // sign bit & hi exp bit
1877                 | t_val<58:29>);     // rest of exp & fraction
1878     }
1879 }};
1880
1881 ////////////////////////////////////////////////////////////////////
1882 //
1883 // The actual decoder specification
1884 //
1885
1886 decode OPCODE default Unknown::unknown() {
1887
1888     format LoadAddress {
1889         0x08: lda({{ Ra = Rb + disp; }});
1890         0x09: ldah({{ Ra = Rb + (disp << 16); }});
1891     }
1892
1893     format LoadOrNop {
1894         0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1895         0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1896         0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1897         0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1898         0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1899         0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1900         0x20: copy_load({{EA = Ra;}},
1901                         {{fault = xc->copySrcTranslate(EA);}},
1902                         IsMemRef, IsLoad, IsCopy);
1903     }
1904
1905     format LoadOrPrefetch {
1906         0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1907         0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1908         // IsFloating flag on lds gets the prefetch to disassemble
1909         // using f31 instead of r31... funcitonally it's unnecessary
1910         0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1911                   PF_EXCLUSIVE, IsFloating);
1912     }
1913
1914     format Store {
1915         0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1916         0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1917         0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1918         0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1919         0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1920         0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1921         0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1922         0x24: copy_store({{EA = Rb;}},
1923                          {{fault = xc->copy(EA);}},
1924                          IsMemRef, IsStore, IsCopy);
1925     }
1926
1927     format StoreCond {
1928         0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1929                     {{
1930                         uint64_t tmp = Mem_write_result;
1931                         // see stq_c
1932                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1933                     }}, LOCKED);
1934         0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1935                     {{
1936                         uint64_t tmp = Mem_write_result;
1937                         // If the write operation returns 0 or 1, then
1938                         // this was a conventional store conditional,
1939                         // and the value indicates the success/failure
1940                         // of the operation.  If another value is
1941                         // returned, then this was a Turbolaser
1942                         // mailbox access, and we don't update the
1943                         // result register at all.
1944                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1945                     }}, LOCKED);
1946     }
1947
1948     format IntegerOperate {
1949
1950         0x10: decode INTFUNC {  // integer arithmetic operations
1951
1952             0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1953             0x40: addlv({{
1954                 uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
1955                 // signed overflow occurs when operands have same sign
1956                 // and sign of result does not match.
1957                 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1958                     fault = Integer_Overflow_Fault;
1959                 Rc.sl = tmp;
1960             }});
1961             0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1962             0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1963
1964             0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1965             0x60: addqv({{
1966                 uint64_t tmp = Ra + Rb_or_imm;
1967                 // signed overflow occurs when operands have same sign
1968                 // and sign of result does not match.
1969                 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1970                     fault = Integer_Overflow_Fault;
1971                 Rc = tmp;
1972             }});
1973             0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1974             0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1975
1976             0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1977             0x49: sublv({{
1978                 uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
1979                 // signed overflow detection is same as for add,
1980                 // except we need to look at the *complemented*
1981                 // sign bit of the subtrahend (Rb), i.e., if the initial
1982                 // signs are the *same* then no overflow can occur
1983                 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1984                     fault = Integer_Overflow_Fault;
1985                 Rc.sl = tmp;
1986             }});
1987             0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1988             0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1989
1990             0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1991             0x69: subqv({{
1992                 uint64_t tmp  = Ra - Rb_or_imm;
1993                 // signed overflow detection is same as for add,
1994                 // except we need to look at the *complemented*
1995                 // sign bit of the subtrahend (Rb), i.e., if the initial
1996                 // signs are the *same* then no overflow can occur
1997                 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1998                     fault = Integer_Overflow_Fault;
1999                 Rc = tmp;
2000             }});
2001             0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
2002             0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
2003
2004             0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
2005             0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
2006             0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
2007             0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
2008             0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
2009
2010             0x0f: cmpbge({{
2011                 int hi = 7;
2012                 int lo = 0;
2013                 uint64_t tmp = 0;
2014                 for (int i = 0; i < 8; ++i) {
2015                     tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
2016                     hi += 8;
2017                     lo += 8;
2018                 }
2019                 Rc = tmp;
2020             }});
2021         }
2022
2023         0x11: decode INTFUNC {  // integer logical operations
2024
2025             0x00: and({{ Rc = Ra & Rb_or_imm; }});
2026             0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
2027             0x20: bis({{ Rc = Ra | Rb_or_imm; }});
2028             0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
2029             0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
2030             0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
2031
2032             // conditional moves
2033             0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
2034             0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
2035             0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
2036             0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
2037             0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
2038             0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
2039             0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
2040             0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
2041
2042             // For AMASK, RA must be R31.
2043             0x61: decode RA {
2044                 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
2045             }
2046
2047             // For IMPLVER, RA must be R31 and the B operand
2048             // must be the immediate value 1.
2049             0x6c: decode RA {
2050                 31: decode IMM {
2051                     1: decode INTIMM {
2052                         // return EV5 for FULL_SYSTEM and EV6 otherwise
2053                         1: implver({{
2054 #ifdef FULL_SYSTEM
2055                              Rc = 1;
2056 #else
2057                              Rc = 2;
2058 #endif
2059                         }});
2060                     }
2061                 }
2062             }
2063
2064 #ifdef FULL_SYSTEM
2065             // The mysterious 11.25...
2066             0x25: WarnUnimpl::eleven25();
2067 #endif
2068         }
2069
2070         0x12: decode INTFUNC {
2071             0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2072             0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2073             0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2074
2075             0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2076             0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2077             0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2078             0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2079
2080             0x52: mskwh({{
2081                 int bv = Rb_or_imm<2:0>;
2082                 Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2083             }});
2084             0x62: msklh({{
2085                 int bv = Rb_or_imm<2:0>;
2086                 Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2087             }});
2088             0x72: mskqh({{
2089                 int bv = Rb_or_imm<2:0>;
2090                 Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2091             }});
2092
2093             0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2094             0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2095             0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2096             0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2097
2098             0x5a: extwh({{
2099                 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2100             0x6a: extlh({{
2101                 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2102             0x7a: extqh({{
2103                 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2104
2105             0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2106             0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2107             0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2108             0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
2109
2110             0x57: inswh({{
2111                 int bv = Rb_or_imm<2:0>;
2112                 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2113             }});
2114             0x67: inslh({{
2115                 int bv = Rb_or_imm<2:0>;
2116                 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2117             }});
2118             0x77: insqh({{
2119                 int bv = Rb_or_imm<2:0>;
2120                 Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
2121             }});
2122
2123             0x30: zap({{
2124                 uint64_t zapmask = 0;
2125                 for (int i = 0; i < 8; ++i) {
2126                     if (Rb_or_imm<i:>)
2127                         zapmask |= (mask(8) << (i * 8));
2128                 }
2129                 Rc = Ra & ~zapmask;
2130             }});
2131             0x31: zapnot({{
2132                 uint64_t zapmask = 0;
2133                 for (int i = 0; i < 8; ++i) {
2134                     if (!Rb_or_imm<i:>)
2135                         zapmask |= (mask(8) << (i * 8));
2136                 }
2137                 Rc = Ra & ~zapmask;
2138             }});
2139         }
2140
2141         0x13: decode INTFUNC {  // integer multiplies
2142             0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2143             0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
2144             0x30: umulh({{
2145                 uint64_t hi, lo;
2146                 mul128(Ra, Rb_or_imm, hi, lo);
2147                 Rc = hi;
2148             }}, IntMultOp);
2149             0x40: mullv({{
2150                 // 32-bit multiply with trap on overflow
2151                 int64_t Rax = Ra.sl;    // sign extended version of Ra.sl
2152                 int64_t Rbx = Rb_or_imm.sl;
2153                 int64_t tmp = Rax * Rbx;
2154                 // To avoid overflow, all the upper 32 bits must match
2155                 // the sign bit of the lower 32.  We code this as
2156                 // checking the upper 33 bits for all 0s or all 1s.
2157                 uint64_t sign_bits = tmp<63:31>;
2158                 if (sign_bits != 0 && sign_bits != mask(33))
2159                     fault = Integer_Overflow_Fault;
2160                 Rc.sl = tmp<31:0>;
2161             }}, IntMultOp);
2162             0x60: mulqv({{
2163                 // 64-bit multiply with trap on overflow
2164                 uint64_t hi, lo;
2165                 mul128(Ra, Rb_or_imm, hi, lo);
2166                 // all the upper 64 bits must match the sign bit of
2167                 // the lower 64
2168                 if (!((hi == 0 && lo<63:> == 0) ||
2169                       (hi == mask(64) && lo<63:> == 1)))
2170                     fault = Integer_Overflow_Fault;
2171                 Rc = lo;
2172             }}, IntMultOp);
2173         }
2174
2175         0x1c: decode INTFUNC {
2176             0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2177             0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2178         0x32: ctlz({{
2179             uint64_t count = 0;
2180             uint64_t temp = Rb;
2181             if (temp<63:32>) temp >>= 32; else count += 32;
2182             if (temp<31:16>) temp >>= 16; else count += 16;
2183             if (temp<15:8>) temp >>= 8; else count += 8;
2184             if (temp<7:4>) temp >>= 4; else count += 4;
2185             if (temp<3:2>) temp >>= 2; else count += 2;
2186             if (temp<1:1>) temp >>= 1; else count += 1;
2187             if ((temp<0:0>) != 0x1) count += 1;
2188             Rc = count;
2189             }}, IntAluOp);
2190
2191         0x33: cttz({{
2192             uint64_t count = 0;
2193             uint64_t temp = Rb;
2194             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
2195             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
2196             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
2197             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
2198             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
2199             if (!(temp<0:0> & ULL(0x1))) count += 1;
2200             Rc = count;
2201         }}, IntAluOp);
2202
2203             format FailUnimpl {
2204                 0x30: ctpop();
2205                 0x31: perr();
2206                 0x34: unpkbw();
2207                 0x35: unpkbl();
2208                 0x36: pkwb();
2209                 0x37: pklb();
2210                 0x38: minsb8();
2211                 0x39: minsw4();
2212                 0x3a: minub8();
2213                 0x3b: minuw4();
2214                 0x3c: maxub8();
2215                 0x3d: maxuw4();
2216                 0x3e: maxsb8();
2217                 0x3f: maxsw4();
2218             }
2219
2220             format BasicOperateWithNopCheck {
2221                 0x70: decode RB {
2222                     31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
2223                 }
2224                 0x78: decode RB {
2225                     31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2226                               FloatCvtOp);
2227                 }
2228             }
2229         }
2230     }
2231
2232     // Conditional branches.
2233     format CondBranch {
2234         0x39: beq({{ cond = (Ra == 0); }});
2235         0x3d: bne({{ cond = (Ra != 0); }});
2236         0x3e: bge({{ cond = (Ra.sq >= 0); }});
2237         0x3f: bgt({{ cond = (Ra.sq >  0); }});
2238         0x3b: ble({{ cond = (Ra.sq <= 0); }});
2239         0x3a: blt({{ cond = (Ra.sq < 0); }});
2240         0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2241         0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2242
2243         0x31: fbeq({{ cond = (Fa == 0); }});
2244         0x35: fbne({{ cond = (Fa != 0); }});
2245         0x36: fbge({{ cond = (Fa >= 0); }});
2246         0x37: fbgt({{ cond = (Fa >  0); }});
2247         0x33: fble({{ cond = (Fa <= 0); }});
2248         0x32: fblt({{ cond = (Fa < 0); }});
2249     }
2250
2251     // unconditional branches
2252     format UncondBranch {
2253         0x30: br();
2254         0x34: bsr(IsCall);
2255     }
2256
2257     // indirect branches
2258     0x1a: decode JMPFUNC {
2259         format Jump {
2260             0: jmp();
2261             1: jsr(IsCall);
2262             2: ret(IsReturn);
2263             3: jsr_coroutine(IsCall, IsReturn);
2264         }
2265     }
2266
2267     // IEEE floating point
2268     0x14: decode FP_SHORTFUNC {
2269         // Integer to FP register moves must have RB == 31
2270         0x4: decode RB {
2271             31: decode FP_FULLFUNC {
2272                 format BasicOperateWithNopCheck {
2273                     0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
2274                     0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
2275                     0x014: FailUnimpl::itoff(); // VAX-format conversion
2276                 }
2277             }
2278         }
2279
2280         // Square root instructions must have FA == 31
2281         0xb: decode FA {
2282             31: decode FP_TYPEFUNC {
2283                 format FloatingPointOperate {
2284 #ifdef SS_COMPATIBLE_FP
2285                     0x0b: sqrts({{
2286                         if (Fb < 0.0)
2287                             fault = Arithmetic_Fault;
2288                         Fc = sqrt(Fb);
2289                     }}, FloatSqrtOp);
2290 #else
2291                     0x0b: sqrts({{
2292                         if (Fb.sf < 0.0)
2293                             fault = Arithmetic_Fault;
2294                         Fc.sf = sqrt(Fb.sf);
2295                     }}, FloatSqrtOp);
2296 #endif
2297                     0x2b: sqrtt({{
2298                         if (Fb < 0.0)
2299                             fault = Arithmetic_Fault;
2300                         Fc = sqrt(Fb);
2301                     }}, FloatSqrtOp);
2302                 }
2303             }
2304         }
2305
2306         // VAX-format sqrtf and sqrtg are not implemented
2307         0xa: FailUnimpl::sqrtfg();
2308     }
2309
2310     // IEEE floating point
2311     0x16: decode FP_SHORTFUNC_TOP2 {
2312         // The top two bits of the short function code break this space
2313         // into four groups: binary ops, compares, reserved, and conversions.
2314         // See Table 4-12 of AHB.
2315         // Most of these instructions may have various trapping and
2316         // rounding mode flags set; these are decoded in the
2317         // FloatingPointDecode template used by the
2318         // FloatingPointOperate format.
2319
2320         // add/sub/mul/div: just decode on the short function code
2321         // and source type.
2322         0: decode FP_TYPEFUNC {
2323             format FloatingPointOperate {
2324 #ifdef SS_COMPATIBLE_FP
2325                 0x00: adds({{ Fc = Fa + Fb; }});
2326                 0x01: subs({{ Fc = Fa - Fb; }});
2327                 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
2328                 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
2329 #else
2330                 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2331                 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2332                 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
2333                 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
2334 #endif
2335
2336                 0x20: addt({{ Fc = Fa + Fb; }});
2337                 0x21: subt({{ Fc = Fa - Fb; }});
2338                 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
2339                 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
2340             }
2341         }
2342
2343         // Floating-point compare instructions must have the default
2344         // rounding mode, and may use the default trapping mode or
2345         // /SU.  Both trapping modes are treated the same by M5; the
2346         // only difference on the real hardware (as far a I can tell)
2347         // is that without /SU you'd get an imprecise trap if you
2348         // tried to compare a NaN with something else (instead of an
2349         // "unordered" result).
2350         1: decode FP_FULLFUNC {
2351             format BasicOperateWithNopCheck {
2352                 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2353                                      FloatCmpOp);
2354                 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2355                                      FloatCmpOp);
2356                 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
2357                                      FloatCmpOp);
2358                 0x0a4, 0x5a4: cmptun({{ // unordered
2359                     Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2360                 }}, FloatCmpOp);
2361             }
2362         }
2363
2364         // The FP-to-integer and integer-to-FP conversion insts
2365         // require that FA be 31.
2366         3: decode FA {
2367             31: decode FP_TYPEFUNC {
2368                 format FloatingPointOperate {
2369                     0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2370
2371                     // The cvtts opcode is overloaded to be cvtst if the trap
2372                     // mode is 2 or 6 (which are not valid otherwise)
2373                     0x2c: decode FP_FULLFUNC {
2374                         format BasicOperateWithNopCheck {
2375                             // trap on denorm version "cvtst/s" is
2376                             // simulated same as cvtst
2377                             0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2378                         }
2379                       default: cvtts({{ Fc.sf = Fb; }});
2380                     }
2381
2382                     // The trapping mode for integer-to-FP conversions
2383                     // must be /SUI or nothing; /U and /SU are not
2384                     // allowed.  The full set of rounding modes are
2385                     // supported though.
2386                     0x3c: decode FP_TRAPMODE {
2387                         0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2388                     }
2389                     0x3e: decode FP_TRAPMODE {
2390                         0,7: cvtqt({{ Fc    = Fb.sq; }});
2391                     }
2392                 }
2393             }
2394         }
2395     }
2396
2397     // misc FP operate
2398     0x17: decode FP_FULLFUNC {
2399         format BasicOperateWithNopCheck {
2400             0x010: cvtlq({{
2401                 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2402             }});
2403             0x030: cvtql({{
2404                 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2405             }});
2406
2407             // We treat the precise & imprecise trapping versions of
2408             // cvtql identically.
2409             0x130, 0x530: cvtqlv({{
2410                 // To avoid overflow, all the upper 32 bits must match
2411                 // the sign bit of the lower 32.  We code this as
2412                 // checking the upper 33 bits for all 0s or all 1s.
2413                 uint64_t sign_bits = Fb.uq<63:31>;
2414                 if (sign_bits != 0 && sign_bits != mask(33))
2415                     fault = Integer_Overflow_Fault;
2416                 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2417             }});
2418
2419             0x020: cpys({{  // copy sign
2420                 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2421             }});
2422             0x021: cpysn({{ // copy sign negated
2423                 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2424             }});
2425             0x022: cpyse({{ // copy sign and exponent
2426                 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2427             }});
2428
2429             0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2430             0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2431             0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
2432             0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2433             0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2434             0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
2435
2436             0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2437             0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2438         }
2439     }
2440
2441     // miscellaneous mem-format ops
2442     0x18: decode MEMFUNC {
2443         format WarnUnimpl {
2444             0x8000: fetch();
2445             0xa000: fetch_m();
2446             0xe800: ecb();
2447         }
2448
2449         format MiscPrefetch {
2450             0xf800: wh64({{ EA = Rb & ~ULL(63); }},
2451                          {{ xc->writeHint(EA, 64, memAccessFlags); }},
2452                          IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
2453                          NO_FAULT);
2454         }
2455
2456         format BasicOperate {
2457             0xc000: rpcc({{
2458 #ifdef FULL_SYSTEM
2459         /* Rb is a fake dependency so here is a fun way to get
2460          * the parser to understand that.
2461          */
2462                 Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
2463
2464 #else
2465                 Ra = curTick;
2466 #endif
2467             }});
2468
2469             // All of the barrier instructions below do nothing in
2470             // their execute() methods (hence the empty code blocks).
2471             // All of their functionality is hard-coded in the
2472             // pipeline based on the flags IsSerializing,
2473             // IsMemBarrier, and IsWriteBarrier.  In the current
2474             // detailed CPU model, the execute() function only gets
2475             // called at fetch, so there's no way to generate pipeline
2476             // behavior at any other stage.  Once we go to an
2477             // exec-in-exec CPU model we should be able to get rid of
2478             // these flags and implement this behavior via the
2479             // execute() methods.
2480
2481             // trapb is just a barrier on integer traps, where excb is
2482             // a barrier on integer and FP traps.  "EXCB is thus a
2483             // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
2484             // them the same though.
2485             0x0000: trapb({{ }}, IsSerializing, No_OpClass);
2486             0x0400: excb({{ }}, IsSerializing, No_OpClass);
2487             0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
2488             0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
2489         }
2490
2491 #ifdef FULL_SYSTEM
2492         format BasicOperate {
2493             0xe000: rc({{
2494                 Ra = xc->readIntrFlag();
2495                 xc->setIntrFlag(0);
2496             }}, IsNonSpeculative);
2497             0xf000: rs({{
2498                 Ra = xc->readIntrFlag();
2499                 xc->setIntrFlag(1);
2500             }}, IsNonSpeculative);
2501         }
2502 #else
2503         format FailUnimpl {
2504             0xe000: rc();
2505             0xf000: rs();
2506         }
2507 #endif
2508     }
2509
2510 #ifdef FULL_SYSTEM
2511     0x00: CallPal::call_pal({{
2512         if (!palValid ||
2513             (palPriv
2514              && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
2515             // invalid pal function code, or attempt to do privileged
2516             // PAL call in non-kernel mode
2517             fault = Unimplemented_Opcode_Fault;
2518         }
2519         else {
2520             // check to see if simulator wants to do something special
2521             // on this PAL call (including maybe suppress it)
2522             bool dopal = xc->simPalCheck(palFunc);
2523
2524             if (dopal) {
2525                 AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
2526                 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2527                 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2528             }
2529         }
2530     }}, IsNonSpeculative);
2531 #else
2532     0x00: decode PALFUNC {
2533         format EmulatedCallPal {
2534             0x00: halt ({{
2535                 SimExit(curTick, "halt instruction encountered");
2536             }}, IsNonSpeculative);
2537             0x83: callsys({{
2538                 xc->syscall();
2539             }}, IsNonSpeculative);
2540             // Read uniq reg into ABI return value register (r0)
2541             0x9e: rduniq({{ R0 = Runiq; }});
2542             // Write uniq reg with value from ABI arg register (r16)
2543             0x9f: wruniq({{ Runiq = R16; }});
2544         }
2545     }
2546 #endif
2547
2548 #ifdef FULL_SYSTEM
2549     format HwLoadStore {
2550         0x1b: decode HW_LDST_QUAD {
2551             0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2552             1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2553         }
2554
2555         0x1f: decode HW_LDST_COND {
2556             0: decode HW_LDST_QUAD {
2557                 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2558                          {{ Mem.ul = Ra<31:0>; }}, L);
2559                 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2560                          {{ Mem.uq = Ra.uq; }}, Q);
2561             }
2562
2563             1: FailUnimpl::hw_st_cond();
2564         }
2565     }
2566
2567     format BasicOperate {
2568         0x1e: hw_rei({{ xc->hwrei(); }});
2569
2570         // M5 special opcodes use the reserved 0x01 opcode space
2571         0x01: decode M5FUNC {
2572             0x00: arm({{
2573                 AlphaPseudo::arm(xc->xcBase());
2574             }}, IsNonSpeculative);
2575             0x01: quiesce({{
2576                 AlphaPseudo::quiesce(xc->xcBase());
2577             }}, IsNonSpeculative);
2578             0x10: ivlb({{
2579                 AlphaPseudo::ivlb(xc->xcBase());
2580             }}, No_OpClass, IsNonSpeculative);
2581             0x11: ivle({{
2582                 AlphaPseudo::ivle(xc->xcBase());
2583             }}, No_OpClass, IsNonSpeculative);
2584             0x20: m5exit_old({{
2585                 AlphaPseudo::m5exit_old(xc->xcBase());
2586             }}, No_OpClass, IsNonSpeculative);
2587             0x21: m5exit({{
2588                 AlphaPseudo::m5exit(xc->xcBase());
2589             }}, No_OpClass, IsNonSpeculative);
2590             0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
2591             0x40: resetstats({{
2592                 AlphaPseudo::resetstats(xc->xcBase());
2593             }}, IsNonSpeculative);
2594             0x41: dumpstats({{
2595                 AlphaPseudo::dumpstats(xc->xcBase());
2596             }}, IsNonSpeculative);
2597             0x42: dumpresetstats({{
2598                 AlphaPseudo::dumpresetstats(xc->xcBase());
2599             }}, IsNonSpeculative);
2600             0x43: m5checkpoint({{
2601                 AlphaPseudo::m5checkpoint(xc->xcBase());
2602             }}, IsNonSpeculative);
2603             0x50: m5readfile({{
2604                 AlphaPseudo::readfile(xc->xcBase());
2605             }}, IsNonSpeculative);
2606             0x51: m5break({{
2607         AlphaPseudo::debugbreak(xc->xcBase());
2608         }}, IsNonSpeculative);
2609             0x52: m5switchcpu({{
2610         AlphaPseudo::switchcpu(xc->xcBase());
2611         }}, IsNonSpeculative);
2612
2613         }
2614     }
2615
2616     format HwMoveIPR {
2617         0x19: hw_mfpr({{
2618             // this instruction is only valid in PAL mode
2619             if (!xc->inPalMode()) {
2620                 fault = Unimplemented_Opcode_Fault;
2621             }
2622             else {
2623                 Ra = xc->readIpr(ipr_index, fault);
2624             }
2625         }});
2626         0x1d: hw_mtpr({{
2627             // this instruction is only valid in PAL mode
2628             if (!xc->inPalMode()) {
2629                 fault = Unimplemented_Opcode_Fault;
2630             }
2631             else {
2632                 xc->setIpr(ipr_index, Ra);
2633                 if (traceData) { traceData->setData(Ra); }
2634             }
2635         }});
2636     }
2637 #endif
2638 }