3 // Alpha ISA description file.
21 #include "base/cprintf.hh"
22 #include "base/misc.hh"
23 #include "cpu/exec_context.hh"
24 #include "cpu/exetrace.hh"
25 #include "cpu/full_cpu/full_cpu.hh"
26 #include "cpu/full_cpu/op_class.hh"
27 #include "cpu/full_cpu/spec_state.hh"
28 #include "cpu/simple_cpu/simple_cpu.hh"
29 #include "cpu/static_inst.hh"
30 #include "sim/annotation.hh"
31 #include "sim/sim_exit.hh"
34 #include "arch/alpha/ev5.hh"
35 #include "arch/alpha/pseudo_inst.hh"
40 // Universal (format-independent) fields
41 def bitfield OPCODE <31:26>;
42 def bitfield RA <25:21>;
43 def bitfield RB <20:16>;
46 def signed bitfield MEMDISP <15: 0>; // displacement
47 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
49 // Memory-format jumps
50 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
51 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
54 def signed bitfield BRDISP <20: 0>; // displacement
56 // Integer operate format(s>;
57 def bitfield INTIMM <20:13>; // integer immediate (literal)
58 def bitfield IMM <12:12>; // immediate flag
59 def bitfield INTFUNC <11: 5>; // function code
60 def bitfield RC < 4: 0>; // dest reg
62 // Floating-point operate format
63 def bitfield FA <25:21>;
64 def bitfield FB <20:16>;
65 def bitfield FP_FULLFUNC <15: 5>; // complete function code
66 def bitfield FP_TRAPMODE <15:13>; // trapping mode
67 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
68 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
69 def bitfield FP_SRCTYPE <10: 9>; // source reg type
70 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
71 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
72 def bitfield FC < 4: 0>; // dest reg
75 def bitfield PALFUNC <25: 0>; // function code
77 // EV5 PAL instructions:
79 def bitfield HW_LDST_PHYS <15>; // address is physical
80 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
81 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
82 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
83 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
84 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
85 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
86 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
89 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
90 def bitfield HW_REI_MBZ <13: 0>; // must be zero
93 def bitfield HW_IPR_IDX <15:0>; // IPR index
96 def bitfield M5FUNC <7:0>;
101 'sb' : ('signed int', 8),
102 'ub' : ('unsigned int', 8),
103 'sw' : ('signed int', 16),
104 'uw' : ('unsigned int', 16),
105 'sl' : ('signed int', 32),
106 'ul' : ('unsigned int', 32),
107 'sq' : ('signed int', 64),
108 'uq' : ('unsigned int', 64),
109 'sf' : ('float', 32),
113 global operandTraitsMap
115 # Int regs default to unsigned, but code should not count on this.
116 # For clarity, descriptions that depend on unsigned behavior should
117 # explicitly specify '.uq'.
118 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
119 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
120 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
121 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
122 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
123 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
124 'Mem': MemOperandTraits('uq', None,
125 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
126 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
127 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
128 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
129 # The next two are hacks for non-full-system call-pal emulation
130 'R0': IntRegOperandTraits('uq', '0', None, 1),
131 'R16': IntRegOperandTraits('uq', '16', None, 1),
134 defineDerivedOperandVars()
138 // just temporary, while comparing with old code for debugging
139 // #define SS_COMPATIBLE_DISASSEMBLY
141 /// Check "FP enabled" machine status bit. Called when executing any FP
142 /// instruction in full-system mode.
143 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
144 /// if not. Non-full-system mode: always returns No_Fault.
146 inline Fault checkFpEnableFault(ExecContext *xc)
148 Fault fault = No_Fault; // dummy... this ipr access should not fault
149 if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
155 inline Fault checkFpEnableFault(ExecContext *xc)
162 * Base class for all Alpha static instructions.
164 class AlphaStaticInst : public StaticInst<AlphaISA>
168 /// Make AlphaISA register dependence tags directly visible in
169 /// this class and derived classes. Maybe these should really
170 /// live here and not in the AlphaISA namespace.
171 enum DependenceTags {
172 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
173 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
174 Uniq_DepTag = AlphaISA::Uniq_DepTag,
175 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
179 AlphaStaticInst(const char *mnem, MachInst _machInst,
181 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
185 /// Print a register name for disassembly given the unique
186 /// dependence tag number (FP or int).
187 void printReg(std::ostream &os, int reg)
189 if (reg < FP_Base_DepTag) {
190 ccprintf(os, "r%d", reg);
193 ccprintf(os, "f%d", reg - FP_Base_DepTag);
197 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
199 std::stringstream ss;
201 ccprintf(ss, "%-10s ", mnemonic);
203 // just print the first two source regs... if there's
204 // a third one, it's a read-modify-write dest (Rc),
206 if (_numSrcRegs > 0) {
207 printReg(ss, _srcRegIdx[0]);
209 if (_numSrcRegs > 1) {
211 printReg(ss, _srcRegIdx[1]);
214 // just print the first dest... if there's a second one,
215 // it's generally implicit
216 if (_numDestRegs > 0) {
219 printReg(ss, _destRegIdx[0]);
228 def template BasicDeclare {{
230 * Static instruction class for "%(mnemonic)s".
232 class %(class_name)s : public %(base_class)s
236 %(class_name)s(MachInst machInst)
237 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
242 Fault execute(SimpleCPU *cpu, ExecContext *xc,
243 Trace::InstRecord *traceData)
245 SimpleCPU *memAccessObj __attribute__((unused)) = cpu;
246 Fault fault = No_Fault;
253 if (fault == No_Fault) {
260 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
261 Trace::InstRecord *traceData)
263 DynInst *memAccessObj __attribute__((unused)) = dynInst;
264 Fault fault = No_Fault;
271 if (fault == No_Fault) {
280 def template BasicDecode {{
281 return new %(class_name)s(machInst);
284 def template BasicDecodeWithMnemonic {{
285 return new %(class_name)s("%(mnemonic)s", machInst);
288 // The most basic instruction format... used only for a few misc. insts
289 def format BasicOperate(code, *flags) {{
290 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
291 return iop.subst('BasicDeclare', 'BasicDecode')
296 ////////////////////////////////////////////////////////////////////
300 * Static instruction class for no-ops. This is a leaf class.
302 class Nop : public AlphaStaticInst
304 /// Disassembly of original instruction.
305 const std::string originalDisassembly;
309 Nop(const std::string _originalDisassembly, MachInst _machInst)
310 : AlphaStaticInst("nop", _machInst, No_OpClass),
311 originalDisassembly(_originalDisassembly)
318 Fault execute(SimpleCPU *cpu, ExecContext *xc,
319 Trace::InstRecord *traceData)
324 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
325 Trace::InstRecord *traceData)
330 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
332 #ifdef SS_COMPATIBLE_DISASSEMBLY
333 return originalDisassembly;
335 return csprintf("%-10s (%s)", "nop", originalDisassembly);
340 /// Helper function for decoding nops. Substitute Nop object
341 /// for original inst passed in as arg (and delete latter).
344 makeNop(AlphaStaticInst *inst)
346 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
353 return ('', 'return new Nop("%s", machInst);\n' % name)
357 // integer & FP operate instructions use Rc as dest, so check for
358 // Rc == 31 to detect nops
359 def template OperateNopCheckDecode {{
361 AlphaStaticInst *i = new %(class_name)s(machInst);
369 // Like BasicOperate format, but generates NOP if RC/FC == 31
370 def format BasicOperateWithNopCheck(code, *opt_args) {{
371 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
373 return iop.subst('BasicDeclare', 'OperateNopCheckDecode')
377 ////////////////////////////////////////////////////////////////////
379 // Integer operate instructions
384 * Base class for integer immediate instructions.
386 class IntegerImm : public AlphaStaticInst
389 /// Immediate operand value (unsigned 8-bit int).
393 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
394 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
398 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
400 std::stringstream ss;
402 ccprintf(ss, "%-10s ", mnemonic);
404 // just print the first source reg... if there's
405 // a second one, it's a read-modify-write dest (Rc),
407 if (_numSrcRegs > 0) {
408 printReg(ss, _srcRegIdx[0]);
414 if (_numDestRegs > 0) {
416 printReg(ss, _destRegIdx[0]);
424 def template RegOrImmDecode {{
427 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
428 : (AlphaStaticInst *)new %(class_name)s(machInst);
436 // Primary format for integer operate instructions:
437 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
438 // - Generates NOP if RC == 31.
439 def format IntegerOperate(code, *opt_flags) {{
440 # If the code block contains 'Rb_or_imm', we define two instructions,
441 # one using 'Rb' and one using 'imm', and have the decoder select
443 uses_imm = (code.find('Rb_or_imm') != -1)
446 # base code is reg version:
447 # rewrite by substituting 'Rb' for 'Rb_or_imm'
448 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
449 # generate immediate version by substituting 'imm'
450 # note that imm takes no extenstion, so we extend
451 # the regexp to replace any extension as well
452 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
454 # generate declaration for register version
455 cblk = CodeBlock(code)
456 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
457 decls = iop.subst('BasicDeclare')
460 # append declaration for imm version
461 imm_cblk = CodeBlock(imm_code)
462 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
464 decls += imm_iop.subst('BasicDeclare')
465 # decode checks IMM bit to pick correct version
466 decode = iop.subst('RegOrImmDecode')
468 # no imm version: just check for nop
469 decode = iop.subst('OperateNopCheckDecode')
471 return (decls, decode)
475 ////////////////////////////////////////////////////////////////////
477 // Floating-point instructions
479 // Note that many FP-type instructions which do not support all the
480 // various rounding & trapping modes use the simpler format
481 // BasicOperateWithNopCheck.
486 * Base class for general floating-point instructions. Includes
487 * support for various Alpha rounding and trapping modes. Only FP
488 * instructions that require this support are derived from this
489 * class; the rest derive directly from AlphaStaticInst.
491 class AlphaFP : public AlphaStaticInst
494 /// Alpha FP rounding modes.
496 Chopped = 0, ///< round toward zero
497 Minus_Infinity = 1, ///< round toward minus infinity
498 Normal = 2, ///< round to nearest (default)
499 Dynamic = 3, ///< use FPCR setting (in instruction)
500 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
503 /// Alpha FP trapping modes.
504 /// For instructions that produce integer results, the
505 /// "Underflow Enable" modes really mean "Overflow Enable", and
506 /// the assembly modifier is V rather than U.
508 /// default: nothing enabled
509 Imprecise = 0, ///< no modifier
510 /// underflow/overflow traps enabled, inexact disabled
511 Underflow_Imprecise = 1, ///< /U or /V
512 Underflow_Precise = 5, ///< /SU or /SV
513 /// underflow/overflow and inexact traps enabled
514 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
519 static const int alphaToC99RoundingMode[];
522 /// Map enum RoundingMode values to disassembly suffixes.
523 static const char *roundingModeSuffix[];
524 /// Map enum TrappingMode values to FP disassembly suffixes.
525 static const char *fpTrappingModeSuffix[];
526 /// Map enum TrappingMode values to integer disassembly suffixes.
527 static const char *intTrappingModeSuffix[];
529 /// This instruction's rounding mode.
530 RoundingMode roundingMode;
531 /// This instruction's trapping mode.
532 TrappingMode trappingMode;
535 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
536 : AlphaStaticInst(mnem, _machInst, __opClass),
537 roundingMode((enum RoundingMode)FP_ROUNDMODE),
538 trappingMode((enum TrappingMode)FP_TRAPMODE)
540 if (trappingMode != Imprecise) {
541 warn("Warning: precise FP traps unimplemented\n");
547 getC99RoundingMode(ExecContext *xc)
549 if (roundingMode == Dynamic) {
550 return alphaToC99RoundingMode[bits(xc->readFpcr(), 59, 58)];
553 return alphaToC99RoundingMode[roundingMode];
558 // This differs from the AlphaStaticInst version only in
559 // printing suffixes for non-default rounding & trapping modes.
560 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
562 std::string mnem_str(mnemonic);
564 mnem_str += ((_destRegIdx[0] >= FP_Base_DepTag)
565 ? fpTrappingModeSuffix[trappingMode]
566 : intTrappingModeSuffix[trappingMode]);
567 mnem_str += roundingModeSuffix[roundingMode];
569 std::stringstream ss;
571 ccprintf(ss, "%-10s ", mnem_str.c_str());
573 // just print the first two source regs... if there's
574 // a third one, it's a read-modify-write dest (Rc),
576 if (_numSrcRegs > 0) {
577 printReg(ss, _srcRegIdx[0]);
579 if (_numSrcRegs > 1) {
581 printReg(ss, _srcRegIdx[1]);
584 // just print the first dest... if there's a second one,
585 // it's generally implicit
586 if (_numDestRegs > 0) {
589 printReg(ss, _destRegIdx[0]);
597 const int AlphaFP::alphaToC99RoundingMode[] = {
598 FE_TOWARDZERO, // Chopped
599 FE_DOWNWARD, // Minus_Infinity
600 FE_TONEAREST, // Normal
601 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
605 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
606 // mark invalid trapping modes, but don't fail on them, because
607 // you could decode anything on a misspeculated path
608 const char *AlphaFP::fpTrappingModeSuffix[] =
609 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
610 const char *AlphaFP::intTrappingModeSuffix[] =
611 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
615 def template FloatingPointDeclare {{
617 * "Fast" static instruction class for "%(mnemonic)s" (imprecise
618 * trapping mode, normal rounding mode).
620 class %(class_name)sFast : public %(base_class)s
624 %(class_name)sFast(MachInst machInst)
625 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
630 Fault execute(SimpleCPU *cpu, ExecContext *xc,
631 Trace::InstRecord *traceData)
633 Fault fault = No_Fault;
640 if (fault == No_Fault) {
647 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
648 Trace::InstRecord *traceData)
650 Fault fault = No_Fault;
657 if (fault == No_Fault) {
666 * General static instruction class for "%(mnemonic)s". Supports
667 * all the various rounding and trapping modes.
669 class %(class_name)sGeneral : public %(base_class)s
673 %(class_name)sGeneral(MachInst machInst)
674 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
679 Fault execute(SimpleCPU *cpu, ExecContext *xc,
680 Trace::InstRecord *traceData)
682 Fault fault = No_Fault;
689 fesetround(getC99RoundingMode(xc));
695 fesetround(FE_TONEAREST);
698 if (fault == No_Fault) {
705 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
706 Trace::InstRecord *traceData)
708 Fault fault = No_Fault;
715 fesetround(getC99RoundingMode(xc));
721 fesetround(FE_TONEAREST);
724 if (fault == No_Fault) {
733 def template FloatingPointDecode {{
735 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
736 && FP_ROUNDMODE == AlphaFP::Normal);
738 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
739 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
750 // General format for floating-point operate instructions:
751 // - Checks trapping and rounding mode flags. Trapping modes
752 // currently unimplemented (will fail).
753 // - Generates NOP if FC == 31.
754 def format FloatingPointOperate(code, *opt_args) {{
755 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code),
757 return iop.subst('FloatingPointDeclare', 'FloatingPointDecode')
761 ////////////////////////////////////////////////////////////////////
763 // Memory-format instructions: LoadAddress, Load, Store
768 * Base class for general Alpha memory-format instructions.
770 class Memory : public AlphaStaticInst
774 /// Displacement for EA calculation (signed).
776 /// Memory request flags. See mem_req_base.hh.
777 unsigned memAccessFlags;
780 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
781 : AlphaStaticInst(mnem, _machInst, __opClass),
782 disp(MEMDISP), memAccessFlags(0)
786 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
788 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
789 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
794 * Base class for a few miscellaneous memory-format insts
795 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
796 * None of these instructions has a destination register either.
798 class MemoryNoDisp : public AlphaStaticInst
801 /// Memory request flags. See mem_req_base.hh.
802 unsigned memAccessFlags;
805 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass)
806 : AlphaStaticInst(mnem, _machInst, __opClass),
811 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
813 return csprintf("%-10s (r%d)", mnemonic, RB);
818 * Base class for "fake" effective-address computation
819 * instructions returnded by eaCompInst().
821 class EACompBase : public AlphaStaticInst
825 EACompBase(MachInst machInst)
826 : AlphaStaticInst("(eacomp)", machInst, IntALU)
830 Fault execute(SimpleCPU *cpu, ExecContext *xc,
831 Trace::InstRecord *traceData)
832 { panic("attempt to execute eacomp"); }
834 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
835 Trace::InstRecord *traceData)
836 { panic("attempt to execute eacomp"); }
840 * Base class for "fake" memory-access instructions returnded by
843 class MemAccBase : public AlphaStaticInst
847 MemAccBase(MachInst machInst, OpClass __opClass)
848 : AlphaStaticInst("(memacc)", machInst, __opClass)
852 Fault execute(SimpleCPU *cpu, ExecContext *xc,
853 Trace::InstRecord *traceData)
854 { panic("attempt to execute memacc"); }
856 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
857 Trace::InstRecord *traceData)
858 { panic("attempt to execute memacc"); }
864 def format LoadAddress(code) {{
865 iop = InstObjParams(name, Name, 'Memory', CodeBlock(code))
866 return iop.subst('BasicDeclare', 'BasicDecode')
870 def template LoadStoreDeclare {{
872 * Static instruction class for "%(mnemonic)s".
874 class %(class_name)s : public %(base_class)s
879 * "Fake" effective address computation class for "%(mnemonic)s".
881 class EAComp : public EACompBase
885 EAComp(MachInst machInst)
886 : EACompBase(machInst)
893 * "Fake" memory access instruction class for "%(mnemonic)s".
895 class MemAcc : public MemAccBase
899 MemAcc(MachInst machInst)
900 : MemAccBase(machInst, %(op_class)s)
902 %(memacc_constructor)s;
906 /// Pointer to EAComp object.
907 StaticInstPtr<AlphaISA> eaCompPtr;
908 /// Pointer to MemAcc object.
909 StaticInstPtr<AlphaISA> memAccPtr;
913 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
914 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
917 %(class_name)s(MachInst machInst)
918 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
919 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
924 Fault execute(SimpleCPU *cpu, ExecContext *xc,
925 Trace::InstRecord *traceData)
927 SimpleCPU *memAccessObj = cpu;
929 Fault fault = No_Fault;
933 %(simple_nonmem_rd)s;
936 if (fault == No_Fault) {
941 if (fault == No_Fault) {
945 if (fault == No_Fault) {
949 if (fault == No_Fault) {
950 %(simple_nonmem_wb)s;
956 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
957 Trace::InstRecord *traceData)
959 DynInst *memAccessObj = dynInst;
961 Fault fault = No_Fault;
968 if (fault == No_Fault) {
973 if (fault == No_Fault) {
977 if (fault == No_Fault) {
981 if (fault == No_Fault) {
991 def template PrefetchDeclare {{
993 * Static instruction class for "%(mnemonic)s".
995 class %(class_name)s : public %(base_class)s
999 %(class_name)s(MachInst machInst)
1000 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
1005 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1006 Trace::InstRecord *traceData)
1009 Fault fault = No_Fault;
1011 %(fp_enable_check)s;
1013 %(simple_nonmem_rd)s;
1016 if (fault == No_Fault) {
1017 cpu->prefetch(EA, memAccessFlags);
1023 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1024 Trace::InstRecord *traceData)
1027 Fault fault = No_Fault;
1029 %(fp_enable_check)s;
1034 if (fault == No_Fault) {
1035 dynInst->prefetch(EA, memAccessFlags);
1044 // load instructions use Ra as dest, so check for
1045 // Ra == 31 to detect nops
1046 def template LoadNopCheckDecode {{
1048 AlphaStaticInst *i = new %(class_name)s(machInst);
1057 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1058 def template LoadPrefetchCheckDecode {{
1061 return new %(class_name)s(machInst);
1064 return new %(class_name)sPrefetch(machInst);
1071 global LoadStoreBase
1072 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1073 base_class = 'Memory', flags = [],
1074 declare_template = 'LoadStoreDeclare',
1075 decode_template = 'BasicDecode'):
1076 # Segregate flags into instruction flags (handled by InstObjParams)
1077 # and memory access flags (handled here).
1079 # Would be nice to autogenerate this list, but oh well.
1080 valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1084 if f in valid_mem_flags:
1087 inst_flags.append(f)
1089 ea_cblk = CodeBlock(ea_code)
1090 memacc_cblk = CodeBlock(memacc_code)
1091 postacc_cblk = CodeBlock(postacc_code)
1093 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1094 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1096 iop.ea_constructor = ea_cblk.constructor
1097 iop.ea_code = ea_cblk.code
1098 iop.memacc_constructor = memacc_cblk.constructor
1099 iop.memacc_code = memacc_cblk.code
1100 iop.postacc_code = postacc_cblk.code
1102 mem_flags = string.join(mem_flags, '|')
1104 iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
1106 return iop.subst(declare_template, decode_template)
1110 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1111 return LoadStoreBase(name, Name, ea_code, memacc_code,
1113 decode_template = 'LoadNopCheckDecode')
1117 // Note that the flags passed in apply only to the prefetch version
1118 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1119 # declare the load instruction object and generate the decode block
1121 LoadStoreBase(name, Name, ea_code, memacc_code,
1122 decode_template = 'LoadPrefetchCheckDecode')
1124 # Declare the prefetch instruction object.
1126 # convert flags from tuple to list to make them mutable
1127 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'RdPort']
1129 (pfdecls, pfdecode) = \
1130 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1132 declare_template = 'PrefetchDeclare')
1134 return (decls + pfdecls, decode)
1138 def format Store(ea_code, memacc_code, *flags) {{
1139 return LoadStoreBase(name, Name, ea_code, memacc_code,
1144 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1145 return LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1150 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1151 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1152 return LoadStoreBase(name, Name, ea_code, memacc_code,
1153 flags = flags, base_class = 'MemoryNoDisp')
1157 ////////////////////////////////////////////////////////////////////
1163 * Base class for instructions whose disassembly is not purely a
1164 * function of the machine instruction (i.e., it depends on the
1165 * PC). This class overrides the disassemble() method to check
1166 * the PC and symbol table values before re-using a cached
1167 * disassembly string. This is necessary for branches and jumps,
1168 * where the disassembly string includes the target address (which
1169 * may depend on the PC and/or symbol table).
1171 class PCDependentDisassembly : public AlphaStaticInst
1174 /// Cached program counter from last disassembly
1176 /// Cached symbol table pointer from last disassembly
1177 const SymbolTable *cachedSymtab;
1180 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1182 : AlphaStaticInst(mnem, _machInst, __opClass),
1183 cachedPC(0), cachedSymtab(0)
1187 const std::string &disassemble(Addr pc, const SymbolTable *symtab)
1189 if (!cachedDisassembly ||
1190 pc != cachedPC || symtab != cachedSymtab)
1192 if (cachedDisassembly)
1193 delete cachedDisassembly;
1196 new std::string(generateDisassembly(pc, symtab));
1198 cachedSymtab = symtab;
1201 return *cachedDisassembly;
1206 * Base class for branches (PC-relative control transfers),
1207 * conditional or unconditional.
1209 class Branch : public PCDependentDisassembly
1212 /// Displacement to target address (signed).
1216 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1217 : PCDependentDisassembly(mnem, _machInst, __opClass),
1222 Addr branchTarget(Addr branchPC)
1224 return branchPC + 4 + disp;
1227 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1229 std::stringstream ss;
1231 ccprintf(ss, "%-10s ", mnemonic);
1233 // There's only one register arg (RA), but it could be
1234 // either a source (the condition for conditional
1235 // branches) or a destination (the link reg for
1236 // unconditional branches)
1237 if (_numSrcRegs > 0) {
1238 printReg(ss, _srcRegIdx[0]);
1241 else if (_numDestRegs > 0) {
1242 printReg(ss, _destRegIdx[0]);
1246 #ifdef SS_COMPATIBLE_DISASSEMBLY
1247 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1253 Addr target = pc + 4 + disp;
1256 if (symtab && symtab->findSymbol(target, str))
1259 ccprintf(ss, "0x%x", target);
1266 * Base class for jumps (register-indirect control transfers). In
1267 * the Alpha ISA, these are always unconditional.
1269 class Jump : public PCDependentDisassembly
1273 /// Displacement to target address (signed).
1278 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1279 : PCDependentDisassembly(mnem, _machInst, __opClass),
1284 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1286 std::stringstream ss;
1288 ccprintf(ss, "%-10s ", mnemonic);
1290 #ifdef SS_COMPATIBLE_DISASSEMBLY
1291 if (_numDestRegs == 0) {
1297 if (_numDestRegs > 0) {
1298 printReg(ss, _destRegIdx[0]);
1302 ccprintf(ss, "(r%d)", RB);
1309 def template JumpOrBranchDecode {{
1311 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1312 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1315 def format CondBranch(code) {{
1316 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1317 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1318 ('IsDirectControl', 'IsCondControl'))
1319 return iop.subst('BasicDeclare', 'BasicDecode')
1323 global UncondCtrlBase
1324 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1325 # Declare basic control transfer w/o link (i.e. link reg is R31)
1326 nolink_code = 'NPC = %s;\n' % npc_expr
1327 nolink_iop = InstObjParams(name, Name, base_class,
1328 CodeBlock(nolink_code), flags)
1329 decls = nolink_iop.subst('BasicDeclare')
1331 # Generate declaration of '*AndLink' version, append to decls
1332 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1333 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1334 CodeBlock(link_code), flags)
1335 decls += link_iop.subst('BasicDeclare')
1337 # need to use link_iop for the decode template since it is expecting
1338 # the shorter version of class_name (w/o "AndLink")
1339 return (decls, nolink_iop.subst('JumpOrBranchDecode'))
1342 def format UncondBranch(*flags) {{
1343 flags += ('IsUncondControl', 'IsDirectControl')
1344 return UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1347 def format Jump(*flags) {{
1348 flags += ('IsUncondControl', 'IsIndirectControl')
1349 return UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1355 * Base class for emulated call_pal calls (used only in
1356 * non-full-system mode).
1358 class EmulatedCallPal : public AlphaStaticInst
1363 EmulatedCallPal(const char *mnem, MachInst _machInst,
1365 : AlphaStaticInst(mnem, _machInst, __opClass)
1369 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1371 #ifdef SS_COMPATIBLE_DISASSEMBLY
1372 return csprintf("%s %s", "call_pal", mnemonic);
1374 return csprintf("%-10s %s", "call_pal", mnemonic);
1380 def format EmulatedCallPal(code) {{
1381 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code))
1382 return iop.subst('BasicDeclare', 'BasicDecode')
1387 * Base class for full-system-mode call_pal instructions.
1388 * Probably could turn this into a leaf class and get rid of the
1391 class CallPalBase : public AlphaStaticInst
1394 int palFunc; ///< Function code part of instruction
1395 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1398 CallPalBase(const char *mnem, MachInst _machInst,
1400 : AlphaStaticInst(mnem, _machInst, __opClass),
1403 int palPriv = ((machInst & 0x80) != 0);
1404 int shortPalFunc = (machInst & 0x3f);
1405 palOffset = 0x2001 + (palPriv << 12) + (shortPalFunc << 6);
1408 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1410 return csprintf("%-10s %#x", "call_pal", palFunc);
1416 def format CallPal(code) {{
1417 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code))
1418 return iop.subst('BasicDeclare', 'BasicDecode')
1426 * Base class for hw_ld and hw_st.
1428 class HwLoadStore : public AlphaStaticInst
1432 /// Displacement for EA calculation (signed).
1434 /// Memory request flags. See mem_req_base.hh.
1435 unsigned memAccessFlags;
1438 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass)
1439 : AlphaStaticInst(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
1442 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1443 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1444 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1445 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1448 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1450 #ifdef SS_COMPATIBLE_DISASSEMBLY
1451 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1453 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1454 const char *lock_str =
1455 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1457 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1458 mnemonic, RA, disp, RB,
1459 HW_LDST_PHYS ? ",PHYS" : "",
1460 HW_LDST_ALT ? ",ALT" : "",
1461 HW_LDST_QUAD ? ",QUAD" : "",
1462 HW_LDST_VPTE ? ",VPTE" : "",
1470 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1471 return LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1473 base_class = 'HwLoadStore')
1477 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1478 return LoadStoreBase(name, Name + class_ext,
1479 ea_code, memacc_code, postacc_code,
1481 base_class = 'HwLoadStore')
1487 * Base class for hw_mfpr and hw_mtpr.
1489 class HwMoveIPR : public AlphaStaticInst
1492 /// Index of internal processor register.
1496 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1497 : AlphaStaticInst(mnem, _machInst, __opClass),
1498 ipr_index(HW_IPR_IDX)
1502 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1504 if (_numSrcRegs > 0) {
1506 return csprintf("%-10s r%d,IPR(%#x)",
1507 mnemonic, RA, ipr_index);
1511 return csprintf("%-10s IPR(%#x),r%d",
1512 mnemonic, ipr_index, RA);
1518 def format HwMoveIPR(code) {{
1519 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1520 return iop.subst('BasicDeclare', 'BasicDecode')
1525 * Static instruction class for unimplemented instructions that
1526 * cause simulator termination. Note that these are recognized
1527 * (legal) instructions that the simulator does not support; the
1528 * 'Unknown' class is used for unrecognized/illegal instructions.
1529 * This is a leaf class.
1531 class FailUnimplemented : public AlphaStaticInst
1535 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1536 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1540 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1541 Trace::InstRecord *traceData)
1543 panic("attempt to execute unimplemented instruction '%s' "
1544 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1545 return Unimplemented_Opcode_Fault;
1548 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1549 Trace::InstRecord *traceData)
1551 // don't panic if this is a misspeculated instruction
1553 panic("attempt to execute unimplemented instruction '%s' "
1554 "(inst 0x%08x, opcode 0x%x)",
1555 mnemonic, machInst, OPCODE);
1556 return Unimplemented_Opcode_Fault;
1559 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1561 return csprintf("%-10s (unimplemented)", mnemonic);
1566 * Base class for unimplemented instructions that cause a warning
1567 * to be printed (but do not terminate simulation). This
1568 * implementation is a little screwy in that it will print a
1569 * warning for each instance of a particular unimplemented machine
1570 * instruction, not just for each unimplemented opcode. Should
1571 * probably make the 'warned' flag a static member of the derived
1574 class WarnUnimplemented : public AlphaStaticInst
1577 /// Have we warned on this instruction yet?
1582 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1583 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1587 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1588 Trace::InstRecord *traceData)
1591 warn("Warning: instruction '%s' unimplemented\n", mnemonic);
1598 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1599 Trace::InstRecord *traceData)
1601 if (!xc->spec_mode && !warned) {
1602 warn("Warning: instruction '%s' unimplemented\n", mnemonic);
1609 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1611 #ifdef SS_COMPATIBLE_DISASSEMBLY
1612 return csprintf("%-10s", mnemonic);
1614 return csprintf("%-10s (unimplemented)", mnemonic);
1620 def template WarnUnimplDeclare {{
1622 * Static instruction class for "%(mnemonic)s".
1624 class %(class_name)s : public %(base_class)s
1628 %(class_name)s(MachInst machInst)
1629 : %(base_class)s("%(mnemonic)s", machInst)
1636 def format FailUnimpl() {{
1637 iop = InstObjParams(name, 'FailUnimplemented')
1638 return ('', iop.subst('BasicDecodeWithMnemonic'))
1641 def format WarnUnimpl() {{
1642 iop = InstObjParams(name, Name, 'WarnUnimplemented')
1643 return iop.subst('WarnUnimplDeclare', 'BasicDecode')
1648 * Static instruction class for unknown (illegal) instructions.
1649 * These cause simulator termination if they are executed in a
1650 * non-speculative mode. This is a leaf class.
1652 class Unknown : public AlphaStaticInst
1656 Unknown(MachInst _machInst)
1657 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1661 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1662 Trace::InstRecord *traceData)
1664 panic("attempt to execute unknown instruction "
1665 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1666 return Unimplemented_Opcode_Fault;
1669 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1670 Trace::InstRecord *traceData)
1672 // don't panic if this is a misspeculated instruction
1674 panic("attempt to execute unknown instruction "
1675 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1676 return Unimplemented_Opcode_Fault;
1679 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1681 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1682 "unknown", machInst, OPCODE);
1687 def format Unknown() {{
1688 return ('', 'return new Unknown(machInst);\n')
1693 /// Return opa + opb, summing carry into third arg.
1695 addc(uint64_t opa, uint64_t opb, int &carry)
1697 uint64_t res = opa + opb;
1698 if (res < opa || res < opb)
1703 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1704 /// product in res_hi and res_lo.
1706 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1708 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1709 uint64_t opa_hi = opa<63:32>;
1710 uint64_t opa_lo = opa<31:0>;
1711 uint64_t opb_hi = opb<63:32>;
1712 uint64_t opb_lo = opb<31:0>;
1714 res_lo = opa_lo * opb_lo;
1716 // The middle partial products logically belong in bit
1717 // positions 95 to 32. Thus the lower 32 bits of each product
1718 // sum into the upper 32 bits of the low result, while the
1719 // upper 32 sum into the low 32 bits of the upper result.
1720 uint64_t partial1 = opa_hi * opb_lo;
1721 uint64_t partial2 = opa_lo * opb_hi;
1723 uint64_t partial1_lo = partial1<31:0> << 32;
1724 uint64_t partial1_hi = partial1<63:32>;
1725 uint64_t partial2_lo = partial2<31:0> << 32;
1726 uint64_t partial2_hi = partial2<63:32>;
1728 // Add partial1_lo and partial2_lo to res_lo, keeping track
1729 // of any carries out
1731 res_lo = addc(partial1_lo, res_lo, carry_out);
1732 res_lo = addc(partial2_lo, res_lo, carry_out);
1734 // Now calculate the high 64 bits...
1735 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1738 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1739 /// See Table 2-2 of Alpha AHB.
1743 int hibit = old_exp<7:>;
1744 int lobits = old_exp<6:0>;
1747 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1750 return (lobits == 0) ? 0 : (0x380 | lobits);
1754 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1755 /// representation to be stored in an FP reg.
1757 s_to_t(uint32_t s_val)
1759 uint64_t tmp = s_val;
1760 return (tmp<31:> << 63 // sign bit
1761 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1762 | tmp<22:0> << 29); // fraction
1765 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1766 /// S-floating representation to be stored in memory.
1768 t_to_s(uint64_t t_val)
1770 return (t_val<63:62> << 30 // sign bit & hi exp bit
1771 | t_val<58:29>); // rest of exp & fraction
1775 decode OPCODE default Unknown::unknown() {
1777 format LoadAddress {
1778 0x08: lda({{ Ra = Rb + disp; }});
1779 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1783 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1784 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1785 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1786 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1787 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1788 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1791 format LoadOrPrefetch {
1792 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1793 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1794 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1799 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1800 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1801 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1802 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1803 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1804 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1805 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1809 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1811 uint64_t tmp = Mem_write_result;
1813 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1815 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1817 uint64_t tmp = Mem_write_result;
1818 // If the write operation returns 0 or 1, then
1819 // this was a conventional store conditional,
1820 // and the value indicates the success/failure
1821 // of the operation. If another value is
1822 // returned, then this was a Turbolaser
1823 // mailbox access, and we don't update the
1824 // result register at all.
1825 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1829 format IntegerOperate {
1831 0x10: decode INTFUNC { // integer arithmetic operations
1833 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1835 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1836 // signed overflow occurs when operands have same sign
1837 // and sign of result does not match.
1838 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1839 fault = Integer_Overflow_Fault;
1842 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1843 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1845 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1847 uint64_t tmp = Ra + Rb_or_imm;
1848 // signed overflow occurs when operands have same sign
1849 // and sign of result does not match.
1850 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1851 fault = Integer_Overflow_Fault;
1854 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1855 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1857 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1859 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1860 // signed overflow detection is same as for add,
1861 // except we need to look at the *complemented*
1862 // sign bit of the subtrahend (Rb), i.e., if the initial
1863 // signs are the *same* then no overflow can occur
1864 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1865 fault = Integer_Overflow_Fault;
1868 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1869 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1871 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1873 uint64_t tmp = Ra - Rb_or_imm;
1874 // signed overflow detection is same as for add,
1875 // except we need to look at the *complemented*
1876 // sign bit of the subtrahend (Rb), i.e., if the initial
1877 // signs are the *same* then no overflow can occur
1878 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1879 fault = Integer_Overflow_Fault;
1882 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1883 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1885 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1886 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1887 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1888 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1889 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1895 for (int i = 0; i < 8; ++i) {
1896 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1904 0x11: decode INTFUNC { // integer logical operations
1906 0x00: and({{ Rc = Ra & Rb_or_imm; }});
1907 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1908 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1909 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1910 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1911 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1913 // conditional moves
1914 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1915 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1916 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1917 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1918 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
1919 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1920 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1921 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
1923 // For AMASK, RA must be R31.
1925 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1928 // For IMPLVER, RA must be R31 and the B operand
1929 // must be the immediate value 1.
1933 // return EV5 for FULL_SYSTEM and EV6 otherwise
1946 // The mysterious 11.25...
1947 0x25: WarnUnimpl::eleven25();
1951 0x12: decode INTFUNC {
1952 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
1953 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
1954 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
1956 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
1957 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
1958 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
1959 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
1962 int bv = Rb_or_imm<2:0>;
1963 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
1966 int bv = Rb_or_imm<2:0>;
1967 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
1970 int bv = Rb_or_imm<2:0>;
1971 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
1974 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
1975 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
1976 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
1977 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
1980 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
1982 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
1984 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
1986 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
1987 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
1988 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
1989 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
1992 int bv = Rb_or_imm<2:0>;
1993 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
1996 int bv = Rb_or_imm<2:0>;
1997 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2000 int bv = Rb_or_imm<2:0>;
2001 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
2005 uint64_t zapmask = 0;
2006 for (int i = 0; i < 8; ++i) {
2008 zapmask |= (mask(8) << (i * 8));
2013 uint64_t zapmask = 0;
2014 for (int i = 0; i < 8; ++i) {
2016 zapmask |= (mask(8) << (i * 8));
2022 0x13: decode INTFUNC { // integer multiplies
2023 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMULT);
2024 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMULT);
2027 mul128(Ra, Rb_or_imm, hi, lo);
2031 // 32-bit multiply with trap on overflow
2032 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
2033 int64_t Rbx = Rb_or_imm.sl;
2034 int64_t tmp = Rax * Rbx;
2035 // To avoid overflow, all the upper 32 bits must match
2036 // the sign bit of the lower 32. We code this as
2037 // checking the upper 33 bits for all 0s or all 1s.
2038 uint64_t sign_bits = tmp<63:31>;
2039 if (sign_bits != 0 && sign_bits != mask(33))
2040 fault = Integer_Overflow_Fault;
2044 // 64-bit multiply with trap on overflow
2046 mul128(Ra, Rb_or_imm, hi, lo);
2047 // all the upper 64 bits must match the sign bit of
2049 if (!((hi == 0 && lo<63:> == 0) ||
2050 (hi == mask(64) && lo<63:> == 1)))
2051 fault = Integer_Overflow_Fault;
2056 0x1c: decode INTFUNC {
2057 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2058 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2079 format BasicOperateWithNopCheck {
2081 31: ftoit({{ Rc = Fa.uq; }}, FloatCVT);
2084 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2091 // Conditional branches.
2093 0x39: beq({{ cond = (Ra == 0); }});
2094 0x3d: bne({{ cond = (Ra != 0); }});
2095 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2096 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2097 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2098 0x3a: blt({{ cond = (Ra.sq < 0); }});
2099 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2100 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2102 0x31: fbeq({{ cond = (Fa == 0); }});
2103 0x35: fbne({{ cond = (Fa != 0); }});
2104 0x36: fbge({{ cond = (Fa >= 0); }});
2105 0x37: fbgt({{ cond = (Fa > 0); }});
2106 0x33: fble({{ cond = (Fa <= 0); }});
2107 0x32: fblt({{ cond = (Fa < 0); }});
2110 // unconditional branches
2111 format UncondBranch {
2116 // indirect branches
2117 0x1a: decode JMPFUNC {
2122 3: jsr_coroutine(IsCall, IsReturn);
2126 // IEEE floating point
2127 0x14: decode FP_SHORTFUNC {
2128 // Integer to FP register moves must have RB == 31
2130 31: decode FP_FULLFUNC {
2131 format BasicOperateWithNopCheck {
2132 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCVT);
2133 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCVT);
2134 0x014: FailUnimpl::itoff(); // VAX-format conversion
2139 // Square root instructions must have FA == 31
2141 31: decode FP_TYPEFUNC {
2142 format FloatingPointOperate {
2143 #ifdef SS_COMPATIBLE_FP
2146 fault = Arithmetic_Fault;
2152 fault = Arithmetic_Fault;
2153 Fc.sf = sqrt(Fb.sf);
2158 fault = Arithmetic_Fault;
2165 // VAX-format sqrtf and sqrtg are not implemented
2166 0xa: FailUnimpl::sqrtfg();
2169 // IEEE floating point
2170 0x16: decode FP_SHORTFUNC_TOP2 {
2171 // The top two bits of the short function code break this space
2172 // into four groups: binary ops, compares, reserved, and conversions.
2173 // See Table 4-12 of AHB.
2174 // Most of these instructions may have various trapping and
2175 // rounding mode flags set; these are decoded in the
2176 // FloatingPointDecode template used by the
2177 // FloatingPointOperate format.
2179 // add/sub/mul/div: just decode on the short function code
2181 0: decode FP_TYPEFUNC {
2182 format FloatingPointOperate {
2183 #ifdef SS_COMPATIBLE_FP
2184 0x00: adds({{ Fc = Fa + Fb; }});
2185 0x01: subs({{ Fc = Fa - Fb; }});
2186 0x02: muls({{ Fc = Fa * Fb; }}, FloatMULT);
2187 0x03: divs({{ Fc = Fa / Fb; }}, FloatDIV);
2189 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2190 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2191 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMULT);
2192 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDIV);
2195 0x20: addt({{ Fc = Fa + Fb; }});
2196 0x21: subt({{ Fc = Fa - Fb; }});
2197 0x22: mult({{ Fc = Fa * Fb; }}, FloatMULT);
2198 0x23: divt({{ Fc = Fa / Fb; }}, FloatDIV);
2202 // Floating-point compare instructions must have the default
2203 // rounding mode, and may use the default trapping mode or
2204 // /SU. Both trapping modes are treated the same by M5; the
2205 // only difference on the real hardware (as far a I can tell)
2206 // is that without /SU you'd get an imprecise trap if you
2207 // tried to compare a NaN with something else (instead of an
2208 // "unordered" result).
2209 1: decode FP_FULLFUNC {
2210 format BasicOperateWithNopCheck {
2211 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2213 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2215 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2217 0x0a4, 0x5a4: cmptun({{ // unordered
2218 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2223 // The FP-to-integer and integer-to-FP conversion insts
2224 // require that FA be 31.
2226 31: decode FP_TYPEFUNC {
2227 format FloatingPointOperate {
2228 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2230 // The cvtts opcode is overloaded to be cvtst if the trap
2231 // mode is 2 or 6 (which are not valid otherwise)
2232 0x2c: decode FP_FULLFUNC {
2233 format BasicOperateWithNopCheck {
2234 // trap on denorm version "cvtst/s" is
2235 // simulated same as cvtst
2236 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2238 default: cvtts({{ Fc.sf = Fb; }});
2241 // The trapping mode for integer-to-FP conversions
2242 // must be /SUI or nothing; /U and /SU are not
2243 // allowed. The full set of rounding modes are
2244 // supported though.
2245 0x3c: decode FP_TRAPMODE {
2246 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2248 0x3e: decode FP_TRAPMODE {
2249 0,7: cvtqt({{ Fc = Fb.sq; }});
2257 0x17: decode FP_FULLFUNC {
2258 format BasicOperateWithNopCheck {
2260 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2263 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2266 // We treat the precise & imprecise trapping versions of
2267 // cvtql identically.
2268 0x130, 0x530: cvtqlv({{
2269 // To avoid overflow, all the upper 32 bits must match
2270 // the sign bit of the lower 32. We code this as
2271 // checking the upper 33 bits for all 0s or all 1s.
2272 uint64_t sign_bits = Fb.uq<63:31>;
2273 if (sign_bits != 0 && sign_bits != mask(33))
2274 fault = Integer_Overflow_Fault;
2275 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2278 0x020: cpys({{ // copy sign
2279 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2281 0x021: cpysn({{ // copy sign negated
2282 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2284 0x022: cpyse({{ // copy sign and exponent
2285 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2288 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2289 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2290 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2291 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2292 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2293 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2295 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2296 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2300 // miscellaneous mem-format ops
2301 0x18: decode MEMFUNC {
2312 format MiscPrefetch {
2313 0xf800: wh64({{ EA = Rb; }},
2314 {{ memAccessObj->writeHint(EA, 64); }},
2315 IsMemRef, IsStore, WrPort);
2318 format BasicOperate {
2319 0xc000: rpcc({{ Ra = curTick; }});
2323 format BasicOperate {
2325 Ra = xc->regs.intrflag;
2326 if (!xc->misspeculating()) {
2327 xc->regs.intrflag = 0;
2331 Ra = xc->regs.intrflag;
2332 if (!xc->misspeculating()) {
2333 xc->regs.intrflag = 1;
2346 0x00: CallPal::call_pal({{
2347 // check to see if simulator wants to do something special
2348 // on this PAL call (including maybe suppress it)
2349 bool dopal = xc->simPalCheck(palFunc);
2351 if (!xc->misspeculating()) {
2352 Annotate::Callpal(xc, palFunc);
2356 if (!xc->misspeculating()) {
2357 AlphaISA::swap_palshadow(&xc->regs, true);
2359 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2360 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2364 0x00: decode PALFUNC {
2365 format EmulatedCallPal {
2367 if (!xc->misspeculating())
2368 SimExit(curTick, "halt instruction encountered");
2371 if (!xc->misspeculating())
2374 // Read uniq reg into ABI return value register (r0)
2375 0x9e: rduniq({{ R0 = Runiq; }});
2376 // Write uniq reg with value from ABI arg register (r16)
2377 0x9f: wruniq({{ Runiq = R16; }});
2383 format HwLoadStore {
2384 0x1b: decode HW_LDST_QUAD {
2385 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2386 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2389 0x1f: decode HW_LDST_COND {
2390 0: decode HW_LDST_QUAD {
2391 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2392 {{ Mem.ul = Ra<31:0>; }}, L);
2393 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2394 {{ Mem.uq = Ra.uq; }}, Q);
2397 1: FailUnimpl::hw_st_cond();
2401 format BasicOperate {
2402 0x1e: hw_rei({{ xc->hwrei(); }});
2404 // M5 special opcodes use the reserved 0x01 opcode space
2405 0x01: decode M5FUNC {
2407 if (!xc->misspeculating()) {
2409 xc->kernelStats.arm();
2413 if (!xc->misspeculating())
2414 AlphaPseudo::quiesce(xc);
2417 if (!xc->misspeculating()) {
2418 Annotate::BeginInterval(xc);
2419 xc->kernelStats.ivlb();
2423 if (!xc->misspeculating())
2424 Annotate::EndInterval(xc);
2427 if (!xc->misspeculating())
2428 AlphaPseudo::m5exit_old(xc);
2431 if (!xc->misspeculating())
2432 AlphaPseudo::m5exit(xc);
2434 0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
2436 if (!xc->misspeculating())
2437 AlphaPseudo::resetstats(xc);
2440 if (!xc->misspeculating())
2441 AlphaPseudo::dumpstats(xc);
2443 0x42: dumpresetstats({{
2444 if (!xc->misspeculating())
2445 AlphaPseudo::dumpresetstats(xc);
2447 0x43: m5checkpoint({{
2448 if (!xc->misspeculating())
2449 AlphaPseudo::m5checkpoint(xc);
2456 // this instruction is only valid in PAL mode
2457 if (!PC_PAL(xc->regs.pc)) {
2458 fault = Unimplemented_Opcode_Fault;
2461 Ra = xc->readIpr(ipr_index, fault);
2465 // this instruction is only valid in PAL mode
2466 if (!PC_PAL(xc->regs.pc)) {
2467 fault = Unimplemented_Opcode_Fault;
2470 xc->setIpr(ipr_index, Ra);
2471 if (traceData) { traceData->setData(Ra); }