3 // Alpha ISA description file.
21 #include "base/cprintf.hh"
22 #include "base/misc.hh"
23 #include "cpu/exec_context.hh"
24 #include "cpu/exetrace.hh"
25 #include "cpu/full_cpu/dyn_inst.hh"
26 #include "cpu/simple_cpu/simple_cpu.hh"
27 #include "cpu/static_inst.hh"
28 #include "sim/sim_exit.hh"
31 #include "arch/alpha/ev5.hh"
32 #include "arch/alpha/pseudo_inst.hh"
37 // Universal (format-independent) fields
38 def bitfield OPCODE <31:26>;
39 def bitfield RA <25:21>;
40 def bitfield RB <20:16>;
43 def signed bitfield MEMDISP <15: 0>; // displacement
44 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
46 // Memory-format jumps
47 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
48 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
51 def signed bitfield BRDISP <20: 0>; // displacement
53 // Integer operate format(s>;
54 def bitfield INTIMM <20:13>; // integer immediate (literal)
55 def bitfield IMM <12:12>; // immediate flag
56 def bitfield INTFUNC <11: 5>; // function code
57 def bitfield RC < 4: 0>; // dest reg
59 // Floating-point operate format
60 def bitfield FA <25:21>;
61 def bitfield FB <20:16>;
62 def bitfield FP_FULLFUNC <15: 5>; // complete function code
63 def bitfield FP_TRAPMODE <15:13>; // trapping mode
64 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
65 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
66 def bitfield FP_SRCTYPE <10: 9>; // source reg type
67 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
68 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
69 def bitfield FC < 4: 0>; // dest reg
72 def bitfield PALFUNC <25: 0>; // function code
74 // EV5 PAL instructions:
76 def bitfield HW_LDST_PHYS <15>; // address is physical
77 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
78 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
79 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
80 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
81 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
82 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
83 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
86 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
87 def bitfield HW_REI_MBZ <13: 0>; // must be zero
90 def bitfield HW_IPR_IDX <15:0>; // IPR index
93 def bitfield M5FUNC <7:0>;
98 'sb' : ('signed int', 8),
99 'ub' : ('unsigned int', 8),
100 'sw' : ('signed int', 16),
101 'uw' : ('unsigned int', 16),
102 'sl' : ('signed int', 32),
103 'ul' : ('unsigned int', 32),
104 'sq' : ('signed int', 64),
105 'uq' : ('unsigned int', 64),
106 'sf' : ('float', 32),
110 global operandTraitsMap
112 # Int regs default to unsigned, but code should not count on this.
113 # For clarity, descriptions that depend on unsigned behavior should
114 # explicitly specify '.uq'.
115 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
116 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
117 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
118 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
119 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
120 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
121 'Mem': MemOperandTraits('uq', None,
122 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
123 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
124 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
125 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
126 # The next two are hacks for non-full-system call-pal emulation
127 'R0': IntRegOperandTraits('uq', '0', None, 1),
128 'R16': IntRegOperandTraits('uq', '16', None, 1),
131 defineDerivedOperandVars()
135 // just temporary, while comparing with old code for debugging
136 // #define SS_COMPATIBLE_DISASSEMBLY
138 /// Check "FP enabled" machine status bit. Called when executing any FP
139 /// instruction in full-system mode.
140 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
141 /// if not. Non-full-system mode: always returns No_Fault.
144 inline Fault checkFpEnableFault(XC *xc)
146 Fault fault = No_Fault; // dummy... this ipr access should not fault
147 if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
154 inline Fault checkFpEnableFault(XC *xc)
161 * Base class for all Alpha static instructions.
163 class AlphaStaticInst : public StaticInst<AlphaISA>
167 /// Make AlphaISA register dependence tags directly visible in
168 /// this class and derived classes. Maybe these should really
169 /// live here and not in the AlphaISA namespace.
170 enum DependenceTags {
171 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
172 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
173 Uniq_DepTag = AlphaISA::Uniq_DepTag,
174 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
178 AlphaStaticInst(const char *mnem, MachInst _machInst,
180 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
184 /// Print a register name for disassembly given the unique
185 /// dependence tag number (FP or int).
186 void printReg(std::ostream &os, int reg)
188 if (reg < FP_Base_DepTag) {
189 ccprintf(os, "r%d", reg);
192 ccprintf(os, "f%d", reg - FP_Base_DepTag);
196 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
198 std::stringstream ss;
200 ccprintf(ss, "%-10s ", mnemonic);
202 // just print the first two source regs... if there's
203 // a third one, it's a read-modify-write dest (Rc),
205 if (_numSrcRegs > 0) {
206 printReg(ss, _srcRegIdx[0]);
208 if (_numSrcRegs > 1) {
210 printReg(ss, _srcRegIdx[1]);
213 // just print the first dest... if there's a second one,
214 // it's generally implicit
215 if (_numDestRegs > 0) {
218 printReg(ss, _destRegIdx[0]);
227 def template BasicDeclare {{
229 * Static instruction class for "%(mnemonic)s".
231 class %(class_name)s : public %(base_class)s
235 %(class_name)s(MachInst machInst)
236 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
241 %(exec_func_declarations)s
245 def template BasicExecute {{
246 Fault %(class_name)s::execute(%(cpu_model)s *xc,
247 Trace::InstRecord *traceData)
249 Fault fault = No_Fault;
256 if (fault == No_Fault) {
264 def template BasicDecode {{
265 return new %(class_name)s(machInst);
268 def template BasicDecodeWithMnemonic {{
269 return new %(class_name)s("%(mnemonic)s", machInst);
272 // The most basic instruction format... used only for a few misc. insts
273 def format BasicOperate(code, *flags) {{
274 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
275 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
280 ////////////////////////////////////////////////////////////////////
284 * Static instruction class for no-ops. This is a leaf class.
286 class Nop : public AlphaStaticInst
288 /// Disassembly of original instruction.
289 const std::string originalDisassembly;
293 Nop(const std::string _originalDisassembly, MachInst _machInst)
294 : AlphaStaticInst("nop", _machInst, No_OpClass),
295 originalDisassembly(_originalDisassembly)
302 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
304 #ifdef SS_COMPATIBLE_DISASSEMBLY
305 return originalDisassembly;
307 return csprintf("%-10s (%s)", "nop", originalDisassembly);
311 Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
314 Fault execute(FullCPUExecContext *, Trace::InstRecord *)
318 /// Helper function for decoding nops. Substitute Nop object
319 /// for original inst passed in as arg (and delete latter).
322 makeNop(AlphaStaticInst *inst)
324 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
331 return ('', 'return new Nop("%s", machInst);\n' % name, 'return No_Fault;')
335 // integer & FP operate instructions use Rc as dest, so check for
336 // Rc == 31 to detect nops
337 def template OperateNopCheckDecode {{
339 AlphaStaticInst *i = new %(class_name)s(machInst);
347 // Like BasicOperate format, but generates NOP if RC/FC == 31
348 def format BasicOperateWithNopCheck(code, *opt_args) {{
349 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
351 return iop.subst('BasicDeclare', 'OperateNopCheckDecode', 'BasicExecute')
355 ////////////////////////////////////////////////////////////////////
357 // Integer operate instructions
362 * Base class for integer immediate instructions.
364 class IntegerImm : public AlphaStaticInst
367 /// Immediate operand value (unsigned 8-bit int).
371 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
372 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
376 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
378 std::stringstream ss;
380 ccprintf(ss, "%-10s ", mnemonic);
382 // just print the first source reg... if there's
383 // a second one, it's a read-modify-write dest (Rc),
385 if (_numSrcRegs > 0) {
386 printReg(ss, _srcRegIdx[0]);
392 if (_numDestRegs > 0) {
394 printReg(ss, _destRegIdx[0]);
402 def template RegOrImmDecode {{
405 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
406 : (AlphaStaticInst *)new %(class_name)s(machInst);
414 // Primary format for integer operate instructions:
415 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
416 // - Generates NOP if RC == 31.
417 def format IntegerOperate(code, *opt_flags) {{
418 # If the code block contains 'Rb_or_imm', we define two instructions,
419 # one using 'Rb' and one using 'imm', and have the decoder select
421 uses_imm = (code.find('Rb_or_imm') != -1)
424 # base code is reg version:
425 # rewrite by substituting 'Rb' for 'Rb_or_imm'
426 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
427 # generate immediate version by substituting 'imm'
428 # note that imm takes no extenstion, so we extend
429 # the regexp to replace any extension as well
430 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
432 # generate declaration for register version
433 cblk = CodeBlock(code)
434 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
435 (decls, exec_code) = iop.subst('BasicDeclare', 'BasicExecute')
438 # append declaration for imm version
439 imm_cblk = CodeBlock(imm_code)
440 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
442 (imm_decls, imm_exec_code) = \
443 imm_iop.subst('BasicDeclare', 'BasicExecute')
445 exec_code += imm_exec_code
446 # decode checks IMM bit to pick correct version
447 decode = iop.subst('RegOrImmDecode')
449 # no imm version: just check for nop
450 decode = iop.subst('OperateNopCheckDecode')
452 return (decls, decode, exec_code)
456 ////////////////////////////////////////////////////////////////////
458 // Floating-point instructions
460 // Note that many FP-type instructions which do not support all the
461 // various rounding & trapping modes use the simpler format
462 // BasicOperateWithNopCheck.
467 * Base class for general floating-point instructions. Includes
468 * support for various Alpha rounding and trapping modes. Only FP
469 * instructions that require this support are derived from this
470 * class; the rest derive directly from AlphaStaticInst.
472 class AlphaFP : public AlphaStaticInst
475 /// Alpha FP rounding modes.
477 Chopped = 0, ///< round toward zero
478 Minus_Infinity = 1, ///< round toward minus infinity
479 Normal = 2, ///< round to nearest (default)
480 Dynamic = 3, ///< use FPCR setting (in instruction)
481 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
484 /// Alpha FP trapping modes.
485 /// For instructions that produce integer results, the
486 /// "Underflow Enable" modes really mean "Overflow Enable", and
487 /// the assembly modifier is V rather than U.
489 /// default: nothing enabled
490 Imprecise = 0, ///< no modifier
491 /// underflow/overflow traps enabled, inexact disabled
492 Underflow_Imprecise = 1, ///< /U or /V
493 Underflow_Precise = 5, ///< /SU or /SV
494 /// underflow/overflow and inexact traps enabled
495 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
500 static const int alphaToC99RoundingMode[];
503 /// Map enum RoundingMode values to disassembly suffixes.
504 static const char *roundingModeSuffix[];
505 /// Map enum TrappingMode values to FP disassembly suffixes.
506 static const char *fpTrappingModeSuffix[];
507 /// Map enum TrappingMode values to integer disassembly suffixes.
508 static const char *intTrappingModeSuffix[];
510 /// This instruction's rounding mode.
511 RoundingMode roundingMode;
512 /// This instruction's trapping mode.
513 TrappingMode trappingMode;
516 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
517 : AlphaStaticInst(mnem, _machInst, __opClass),
518 roundingMode((enum RoundingMode)FP_ROUNDMODE),
519 trappingMode((enum TrappingMode)FP_TRAPMODE)
521 if (trappingMode != Imprecise) {
522 warn("precise FP traps unimplemented\n");
528 getC99RoundingMode(uint64_t fpcr_val)
530 if (roundingMode == Dynamic) {
531 return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
534 return alphaToC99RoundingMode[roundingMode];
539 // This differs from the AlphaStaticInst version only in
540 // printing suffixes for non-default rounding & trapping modes.
541 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
543 std::string mnem_str(mnemonic);
545 #ifndef SS_COMPATIBLE_DISASSEMBLY
546 std::string suffix("");
547 suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
548 ? fpTrappingModeSuffix[trappingMode]
549 : intTrappingModeSuffix[trappingMode]);
550 suffix += roundingModeSuffix[roundingMode];
553 mnem_str = csprintf("%s/%s", mnemonic, suffix);
557 std::stringstream ss;
558 ccprintf(ss, "%-10s ", mnem_str.c_str());
560 // just print the first two source regs... if there's
561 // a third one, it's a read-modify-write dest (Rc),
563 if (_numSrcRegs > 0) {
564 printReg(ss, _srcRegIdx[0]);
566 if (_numSrcRegs > 1) {
568 printReg(ss, _srcRegIdx[1]);
571 // just print the first dest... if there's a second one,
572 // it's generally implicit
573 if (_numDestRegs > 0) {
576 printReg(ss, _destRegIdx[0]);
584 const int AlphaFP::alphaToC99RoundingMode[] = {
585 FE_TOWARDZERO, // Chopped
586 FE_DOWNWARD, // Minus_Infinity
587 FE_TONEAREST, // Normal
588 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
592 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
593 // mark invalid trapping modes, but don't fail on them, because
594 // you could decode anything on a misspeculated path
595 const char *AlphaFP::fpTrappingModeSuffix[] =
596 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
597 const char *AlphaFP::intTrappingModeSuffix[] =
598 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
602 def template FloatingPointDecode {{
604 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
605 && FP_ROUNDMODE == AlphaFP::Normal);
607 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
608 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
618 // General format for floating-point operate instructions:
619 // - Checks trapping and rounding mode flags. Trapping modes
620 // currently unimplemented (will fail).
621 // - Generates NOP if FC == 31.
622 def format FloatingPointOperate(code, *opt_args) {{
623 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
624 decode = iop.subst('FloatingPointDecode')
626 fast_iop = InstObjParams(name, Name + 'Fast', 'AlphaFP',
627 CodeBlock(code), opt_args)
628 (fast_declare, fast_exec) = fast_iop.subst('BasicDeclare', 'BasicExecute')
630 gen_code_prefix = r'''
632 fesetround(getC99RoundingMode(xc->readFpcr()));
635 gen_code_suffix = r'''
637 fesetround(FE_TONEAREST);
641 gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
642 CodeBlock(gen_code_prefix + code + gen_code_suffix), opt_args)
643 (gen_declare, gen_exec) = gen_iop.subst('BasicDeclare', 'BasicExecute')
645 return (fast_declare + gen_declare, decode, fast_exec + gen_exec)
649 ////////////////////////////////////////////////////////////////////
651 // Memory-format instructions: LoadAddress, Load, Store
656 * Base class for general Alpha memory-format instructions.
658 class Memory : public AlphaStaticInst
662 /// Displacement for EA calculation (signed).
664 /// Memory request flags. See mem_req_base.hh.
665 unsigned memAccessFlags;
668 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
669 : AlphaStaticInst(mnem, _machInst, __opClass),
670 disp(MEMDISP), memAccessFlags(0)
674 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
676 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
677 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
682 * Base class for a few miscellaneous memory-format insts
683 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
684 * None of these instructions has a destination register either.
686 class MemoryNoDisp : public AlphaStaticInst
689 /// Memory request flags. See mem_req_base.hh.
690 unsigned memAccessFlags;
693 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass)
694 : AlphaStaticInst(mnem, _machInst, __opClass),
699 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
701 return csprintf("%-10s (r%d)", mnemonic, RB);
706 * Base class for "fake" effective-address computation
707 * instructions returnded by eaCompInst().
709 class EACompBase : public AlphaStaticInst
713 EACompBase(MachInst machInst)
714 : AlphaStaticInst("(eacomp)", machInst, IntALU)
718 Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
719 { panic("attempt to execute eacomp"); }
721 Fault execute(FullCPUExecContext *, Trace::InstRecord *)
722 { panic("attempt to execute eacomp"); }
726 * Base class for "fake" memory-access instructions returnded by
729 class MemAccBase : public AlphaStaticInst
733 MemAccBase(MachInst machInst, OpClass __opClass)
734 : AlphaStaticInst("(memacc)", machInst, __opClass)
738 Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
739 { panic("attempt to execute memacc"); }
741 Fault execute(FullCPUExecContext *, Trace::InstRecord *)
742 { panic("attempt to execute memacc"); }
748 def format LoadAddress(code) {{
749 iop = InstObjParams(name, Name, 'Memory', CodeBlock(code))
750 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
754 def template LoadStoreDeclare {{
756 * Static instruction class for "%(mnemonic)s".
758 class %(class_name)s : public %(base_class)s
763 * "Fake" effective address computation class for "%(mnemonic)s".
765 class EAComp : public EACompBase
769 EAComp(MachInst machInst)
770 : EACompBase(machInst)
777 * "Fake" memory access instruction class for "%(mnemonic)s".
779 class MemAcc : public MemAccBase
783 MemAcc(MachInst machInst)
784 : MemAccBase(machInst, %(op_class)s)
786 %(memacc_constructor)s;
790 /// Pointer to EAComp object.
791 StaticInstPtr<AlphaISA> eaCompPtr;
792 /// Pointer to MemAcc object.
793 StaticInstPtr<AlphaISA> memAccPtr;
797 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
798 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
801 %(class_name)s(MachInst machInst)
802 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
803 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
808 %(exec_func_declarations)s
812 def template LoadStoreExecute {{
813 Fault %(class_name)s::execute(%(cpu_model)s *xc,
814 Trace::InstRecord *traceData)
817 Fault fault = No_Fault;
824 if (fault == No_Fault) {
829 if (fault == No_Fault) {
833 if (fault == No_Fault) {
837 if (fault == No_Fault) {
845 def template PrefetchDeclare {{
847 * Static instruction class for "%(mnemonic)s".
849 class %(class_name)s : public %(base_class)s
854 * "Fake" effective address computation class for "%(mnemonic)s".
856 class EAComp : public EACompBase
860 EAComp(MachInst machInst)
861 : EACompBase(machInst)
868 * "Fake" memory access instruction class for "%(mnemonic)s".
870 class MemAcc : public MemAccBase
874 MemAcc(MachInst machInst)
875 : MemAccBase(machInst, %(op_class)s)
877 %(memacc_constructor)s;
881 /// Pointer to EAComp object.
882 StaticInstPtr<AlphaISA> eaCompPtr;
883 /// Pointer to MemAcc object.
884 StaticInstPtr<AlphaISA> memAccPtr;
888 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
889 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
892 %(class_name)s(MachInst machInst)
893 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
894 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
899 %(exec_func_declarations)s
903 def template PrefetchExecute {{
904 Fault %(class_name)s::execute(%(cpu_model)s *xc,
905 Trace::InstRecord *traceData)
908 Fault fault = No_Fault;
915 if (fault == No_Fault) {
916 xc->prefetch(EA, memAccessFlags);
923 // load instructions use Ra as dest, so check for
924 // Ra == 31 to detect nops
925 def template LoadNopCheckDecode {{
927 AlphaStaticInst *i = new %(class_name)s(machInst);
936 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
937 def template LoadPrefetchCheckDecode {{
940 return new %(class_name)s(machInst);
943 return new %(class_name)sPrefetch(machInst);
951 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
952 base_class = 'Memory', flags = [],
953 declare_template = 'LoadStoreDeclare',
954 decode_template = 'BasicDecode',
955 exec_template = 'LoadStoreExecute'):
956 # Segregate flags into instruction flags (handled by InstObjParams)
957 # and memory access flags (handled here).
959 # Would be nice to autogenerate this list, but oh well.
960 valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
964 if f in valid_mem_flags:
969 ea_cblk = CodeBlock(ea_code)
970 memacc_cblk = CodeBlock(memacc_code)
971 postacc_cblk = CodeBlock(postacc_code)
973 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
974 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
976 iop.ea_constructor = ea_cblk.constructor
977 iop.ea_code = ea_cblk.code
978 iop.memacc_constructor = memacc_cblk.constructor
979 iop.memacc_code = memacc_cblk.code
980 iop.postacc_code = postacc_cblk.code
982 mem_flags = string.join(mem_flags, '|')
984 iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
986 return iop.subst(declare_template, decode_template, exec_template)
990 def format LoadOrNop(ea_code, memacc_code, *flags) {{
991 return LoadStoreBase(name, Name, ea_code, memacc_code,
993 decode_template = 'LoadNopCheckDecode')
997 // Note that the flags passed in apply only to the prefetch version
998 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
999 # declare the load instruction object and generate the decode block
1000 (decls, decode, exec_code) = \
1001 LoadStoreBase(name, Name, ea_code, memacc_code,
1002 decode_template = 'LoadPrefetchCheckDecode')
1004 # Declare the prefetch instruction object.
1006 # convert flags from tuple to list to make them mutable
1007 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'RdPort']
1009 (pfdecls, pfdecode, pfexec) = \
1010 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1012 declare_template = 'PrefetchDeclare',
1013 exec_template = 'PrefetchExecute')
1015 return (decls + pfdecls, decode, exec_code + pfexec)
1019 def format Store(ea_code, memacc_code, *flags) {{
1020 return LoadStoreBase(name, Name, ea_code, memacc_code,
1025 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1026 return LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1031 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1032 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1033 return LoadStoreBase(name, Name, ea_code, memacc_code,
1034 flags = flags, base_class = 'MemoryNoDisp')
1038 ////////////////////////////////////////////////////////////////////
1044 * Base class for instructions whose disassembly is not purely a
1045 * function of the machine instruction (i.e., it depends on the
1046 * PC). This class overrides the disassemble() method to check
1047 * the PC and symbol table values before re-using a cached
1048 * disassembly string. This is necessary for branches and jumps,
1049 * where the disassembly string includes the target address (which
1050 * may depend on the PC and/or symbol table).
1052 class PCDependentDisassembly : public AlphaStaticInst
1055 /// Cached program counter from last disassembly
1057 /// Cached symbol table pointer from last disassembly
1058 const SymbolTable *cachedSymtab;
1061 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1063 : AlphaStaticInst(mnem, _machInst, __opClass),
1064 cachedPC(0), cachedSymtab(0)
1068 const std::string &disassemble(Addr pc, const SymbolTable *symtab)
1070 if (!cachedDisassembly ||
1071 pc != cachedPC || symtab != cachedSymtab)
1073 if (cachedDisassembly)
1074 delete cachedDisassembly;
1077 new std::string(generateDisassembly(pc, symtab));
1079 cachedSymtab = symtab;
1082 return *cachedDisassembly;
1087 * Base class for branches (PC-relative control transfers),
1088 * conditional or unconditional.
1090 class Branch : public PCDependentDisassembly
1093 /// Displacement to target address (signed).
1097 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1098 : PCDependentDisassembly(mnem, _machInst, __opClass),
1103 Addr branchTarget(Addr branchPC) const
1105 return branchPC + 4 + disp;
1108 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1110 std::stringstream ss;
1112 ccprintf(ss, "%-10s ", mnemonic);
1114 // There's only one register arg (RA), but it could be
1115 // either a source (the condition for conditional
1116 // branches) or a destination (the link reg for
1117 // unconditional branches)
1118 if (_numSrcRegs > 0) {
1119 printReg(ss, _srcRegIdx[0]);
1122 else if (_numDestRegs > 0) {
1123 printReg(ss, _destRegIdx[0]);
1127 #ifdef SS_COMPATIBLE_DISASSEMBLY
1128 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1134 Addr target = pc + 4 + disp;
1137 if (symtab && symtab->findSymbol(target, str))
1140 ccprintf(ss, "0x%x", target);
1147 * Base class for jumps (register-indirect control transfers). In
1148 * the Alpha ISA, these are always unconditional.
1150 class Jump : public PCDependentDisassembly
1154 /// Displacement to target address (signed).
1159 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1160 : PCDependentDisassembly(mnem, _machInst, __opClass),
1165 Addr branchTarget(ExecContext *xc) const
1167 Addr NPC = xc->readPC() + 4;
1168 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
1169 return (Rb & ~3) | (NPC & 1);
1172 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1174 std::stringstream ss;
1176 ccprintf(ss, "%-10s ", mnemonic);
1178 #ifdef SS_COMPATIBLE_DISASSEMBLY
1179 if (_numDestRegs == 0) {
1185 if (_numDestRegs > 0) {
1186 printReg(ss, _destRegIdx[0]);
1190 ccprintf(ss, "(r%d)", RB);
1197 def template JumpOrBranchDecode {{
1199 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1200 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1203 def format CondBranch(code) {{
1204 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1205 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1206 ('IsDirectControl', 'IsCondControl'))
1207 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1211 global UncondCtrlBase
1212 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1213 # Declare basic control transfer w/o link (i.e. link reg is R31)
1214 nolink_code = 'NPC = %s;\n' % npc_expr
1215 nolink_iop = InstObjParams(name, Name, base_class,
1216 CodeBlock(nolink_code), flags)
1217 (decls, exec_code) = nolink_iop.subst('BasicDeclare', 'BasicExecute')
1219 # Generate declaration of '*AndLink' version, append to decls
1220 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1221 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1222 CodeBlock(link_code), flags)
1223 (link_decls, link_exec_code) = \
1224 link_iop.subst('BasicDeclare', 'BasicExecute')
1226 exec_code += link_exec_code
1228 # need to use link_iop for the decode template since it is expecting
1229 # the shorter version of class_name (w/o "AndLink")
1230 return (decls, nolink_iop.subst('JumpOrBranchDecode'), exec_code)
1233 def format UncondBranch(*flags) {{
1234 flags += ('IsUncondControl', 'IsDirectControl')
1235 return UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1238 def format Jump(*flags) {{
1239 flags += ('IsUncondControl', 'IsIndirectControl')
1240 return UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1246 * Base class for emulated call_pal calls (used only in
1247 * non-full-system mode).
1249 class EmulatedCallPal : public AlphaStaticInst
1254 EmulatedCallPal(const char *mnem, MachInst _machInst,
1256 : AlphaStaticInst(mnem, _machInst, __opClass)
1260 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1262 #ifdef SS_COMPATIBLE_DISASSEMBLY
1263 return csprintf("%s %s", "call_pal", mnemonic);
1265 return csprintf("%-10s %s", "call_pal", mnemonic);
1271 def format EmulatedCallPal(code) {{
1272 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code))
1273 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1278 * Base class for full-system-mode call_pal instructions.
1279 * Probably could turn this into a leaf class and get rid of the
1282 class CallPalBase : public AlphaStaticInst
1285 int palFunc; ///< Function code part of instruction
1286 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1287 bool palValid; ///< is the function code valid?
1288 bool palPriv; ///< is this call privileged?
1291 CallPalBase(const char *mnem, MachInst _machInst,
1293 : AlphaStaticInst(mnem, _machInst, __opClass),
1296 // From the 21164 HRM (paraphrased):
1297 // Bit 7 of the function code (mask 0x80) indicates
1298 // whether the call is privileged (bit 7 == 0) or
1299 // unprivileged (bit 7 == 1). The privileged call table
1300 // starts at 0x2000, the unprivielged call table starts at
1301 // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
1303 const int palPrivMask = 0x80;
1304 const int palOffsetMask = 0x3f;
1306 // Pal call is invalid unless all other bits are 0
1307 palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
1308 palPriv = ((machInst & palPrivMask) == 0);
1309 int shortPalFunc = (machInst & palOffsetMask);
1310 // Add 1 to base to set pal-mode bit
1311 palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
1314 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1316 return csprintf("%-10s %#x", "call_pal", palFunc);
1322 def format CallPal(code) {{
1323 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code))
1324 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1332 * Base class for hw_ld and hw_st.
1334 class HwLoadStore : public AlphaStaticInst
1338 /// Displacement for EA calculation (signed).
1340 /// Memory request flags. See mem_req_base.hh.
1341 unsigned memAccessFlags;
1344 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass)
1345 : AlphaStaticInst(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
1348 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1349 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1350 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1351 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1354 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1356 #ifdef SS_COMPATIBLE_DISASSEMBLY
1357 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1359 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1360 const char *lock_str =
1361 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1363 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1364 mnemonic, RA, disp, RB,
1365 HW_LDST_PHYS ? ",PHYS" : "",
1366 HW_LDST_ALT ? ",ALT" : "",
1367 HW_LDST_QUAD ? ",QUAD" : "",
1368 HW_LDST_VPTE ? ",VPTE" : "",
1376 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1377 return LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1379 base_class = 'HwLoadStore')
1383 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1384 return LoadStoreBase(name, Name + class_ext,
1385 ea_code, memacc_code, postacc_code,
1387 base_class = 'HwLoadStore')
1393 * Base class for hw_mfpr and hw_mtpr.
1395 class HwMoveIPR : public AlphaStaticInst
1398 /// Index of internal processor register.
1402 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1403 : AlphaStaticInst(mnem, _machInst, __opClass),
1404 ipr_index(HW_IPR_IDX)
1408 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1410 if (_numSrcRegs > 0) {
1412 return csprintf("%-10s r%d,IPR(%#x)",
1413 mnemonic, RA, ipr_index);
1417 return csprintf("%-10s IPR(%#x),r%d",
1418 mnemonic, ipr_index, RA);
1424 def format HwMoveIPR(code) {{
1425 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1426 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1431 * Static instruction class for unimplemented instructions that
1432 * cause simulator termination. Note that these are recognized
1433 * (legal) instructions that the simulator does not support; the
1434 * 'Unknown' class is used for unrecognized/illegal instructions.
1435 * This is a leaf class.
1437 class FailUnimplemented : public AlphaStaticInst
1441 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1442 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1446 Fault execute(SimpleCPUExecContext *xc,
1447 Trace::InstRecord *traceData)
1449 panic("attempt to execute unimplemented instruction '%s' "
1450 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1451 return Unimplemented_Opcode_Fault;
1454 Fault execute(FullCPUExecContext *xc,
1455 Trace::InstRecord *traceData)
1457 // don't panic if this is a misspeculated instruction
1458 if (!xc->misspeculating())
1459 panic("attempt to execute unimplemented instruction '%s' "
1460 "(inst 0x%08x, opcode 0x%x)",
1461 mnemonic, machInst, OPCODE);
1462 return Unimplemented_Opcode_Fault;
1465 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1467 return csprintf("%-10s (unimplemented)", mnemonic);
1472 * Base class for unimplemented instructions that cause a warning
1473 * to be printed (but do not terminate simulation). This
1474 * implementation is a little screwy in that it will print a
1475 * warning for each instance of a particular unimplemented machine
1476 * instruction, not just for each unimplemented opcode. Should
1477 * probably make the 'warned' flag a static member of the derived
1480 class WarnUnimplemented : public AlphaStaticInst
1483 /// Have we warned on this instruction yet?
1488 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1489 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1493 Fault execute(SimpleCPUExecContext *xc,
1494 Trace::InstRecord *traceData)
1497 warn("instruction '%s' unimplemented\n", mnemonic);
1504 Fault execute(FullCPUExecContext *xc,
1505 Trace::InstRecord *traceData)
1507 if (!xc->misspeculating() && !warned) {
1508 warn("instruction '%s' unimplemented\n", mnemonic);
1515 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1517 #ifdef SS_COMPATIBLE_DISASSEMBLY
1518 return csprintf("%-10s", mnemonic);
1520 return csprintf("%-10s (unimplemented)", mnemonic);
1526 def template WarnUnimplDeclare {{
1528 * Static instruction class for "%(mnemonic)s".
1530 class %(class_name)s : public %(base_class)s
1534 %(class_name)s(MachInst machInst)
1535 : %(base_class)s("%(mnemonic)s", machInst)
1542 def format FailUnimpl() {{
1543 iop = InstObjParams(name, 'FailUnimplemented')
1544 return ('', iop.subst('BasicDecodeWithMnemonic'), '')
1547 def format WarnUnimpl() {{
1548 iop = InstObjParams(name, Name, 'WarnUnimplemented')
1549 return iop.subst('WarnUnimplDeclare', 'BasicDecode') + ['']
1554 * Static instruction class for unknown (illegal) instructions.
1555 * These cause simulator termination if they are executed in a
1556 * non-speculative mode. This is a leaf class.
1558 class Unknown : public AlphaStaticInst
1562 Unknown(MachInst _machInst)
1563 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1567 Fault execute(SimpleCPUExecContext *xc,
1568 Trace::InstRecord *traceData)
1570 panic("attempt to execute unknown instruction "
1571 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1572 return Unimplemented_Opcode_Fault;
1575 Fault execute(FullCPUExecContext *xc,
1576 Trace::InstRecord *traceData)
1578 // don't panic if this is a misspeculated instruction
1579 if (!xc->misspeculating())
1580 panic("attempt to execute unknown instruction "
1581 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1582 return Unimplemented_Opcode_Fault;
1585 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1587 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1588 "unknown", machInst, OPCODE);
1593 def format Unknown() {{
1594 return ('', 'return new Unknown(machInst);\n', '')
1599 /// Return opa + opb, summing carry into third arg.
1601 addc(uint64_t opa, uint64_t opb, int &carry)
1603 uint64_t res = opa + opb;
1604 if (res < opa || res < opb)
1609 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1610 /// product in res_hi and res_lo.
1612 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1614 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1615 uint64_t opa_hi = opa<63:32>;
1616 uint64_t opa_lo = opa<31:0>;
1617 uint64_t opb_hi = opb<63:32>;
1618 uint64_t opb_lo = opb<31:0>;
1620 res_lo = opa_lo * opb_lo;
1622 // The middle partial products logically belong in bit
1623 // positions 95 to 32. Thus the lower 32 bits of each product
1624 // sum into the upper 32 bits of the low result, while the
1625 // upper 32 sum into the low 32 bits of the upper result.
1626 uint64_t partial1 = opa_hi * opb_lo;
1627 uint64_t partial2 = opa_lo * opb_hi;
1629 uint64_t partial1_lo = partial1<31:0> << 32;
1630 uint64_t partial1_hi = partial1<63:32>;
1631 uint64_t partial2_lo = partial2<31:0> << 32;
1632 uint64_t partial2_hi = partial2<63:32>;
1634 // Add partial1_lo and partial2_lo to res_lo, keeping track
1635 // of any carries out
1637 res_lo = addc(partial1_lo, res_lo, carry_out);
1638 res_lo = addc(partial2_lo, res_lo, carry_out);
1640 // Now calculate the high 64 bits...
1641 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1644 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1645 /// See Table 2-2 of Alpha AHB.
1649 int hibit = old_exp<7:>;
1650 int lobits = old_exp<6:0>;
1653 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1656 return (lobits == 0) ? 0 : (0x380 | lobits);
1660 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1661 /// representation to be stored in an FP reg.
1663 s_to_t(uint32_t s_val)
1665 uint64_t tmp = s_val;
1666 return (tmp<31:> << 63 // sign bit
1667 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1668 | tmp<22:0> << 29); // fraction
1671 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1672 /// S-floating representation to be stored in memory.
1674 t_to_s(uint64_t t_val)
1676 return (t_val<63:62> << 30 // sign bit & hi exp bit
1677 | t_val<58:29>); // rest of exp & fraction
1681 decode OPCODE default Unknown::unknown() {
1683 format LoadAddress {
1684 0x08: lda({{ Ra = Rb + disp; }});
1685 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1689 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1690 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1691 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1692 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1693 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1694 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1695 0x20: copy_load({{EA = Ra;}},
1696 {{ fault = xc->copySrcTranslate(EA);}},
1697 IsMemRef, IsLoad, IsCopy);
1700 format LoadOrPrefetch {
1701 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1702 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1703 // IsFloating flag on lds gets the prefetch to disassemble
1704 // using f31 instead of r31... funcitonally it's unnecessary
1705 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1706 PF_EXCLUSIVE, IsFloating);
1710 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1711 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1712 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1713 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1714 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1715 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1716 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1717 0x24: copy_store({{EA = Rb;}},
1718 {{ fault = xc->copy(EA);}},
1719 IsMemRef, IsStore, IsCopy);
1723 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1725 uint64_t tmp = Mem_write_result;
1727 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1729 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1731 uint64_t tmp = Mem_write_result;
1732 // If the write operation returns 0 or 1, then
1733 // this was a conventional store conditional,
1734 // and the value indicates the success/failure
1735 // of the operation. If another value is
1736 // returned, then this was a Turbolaser
1737 // mailbox access, and we don't update the
1738 // result register at all.
1739 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1743 format IntegerOperate {
1745 0x10: decode INTFUNC { // integer arithmetic operations
1747 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1749 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1750 // signed overflow occurs when operands have same sign
1751 // and sign of result does not match.
1752 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1753 fault = Integer_Overflow_Fault;
1756 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1757 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1759 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1761 uint64_t tmp = Ra + Rb_or_imm;
1762 // signed overflow occurs when operands have same sign
1763 // and sign of result does not match.
1764 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1765 fault = Integer_Overflow_Fault;
1768 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1769 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1771 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1773 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1774 // signed overflow detection is same as for add,
1775 // except we need to look at the *complemented*
1776 // sign bit of the subtrahend (Rb), i.e., if the initial
1777 // signs are the *same* then no overflow can occur
1778 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1779 fault = Integer_Overflow_Fault;
1782 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1783 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1785 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1787 uint64_t tmp = Ra - Rb_or_imm;
1788 // signed overflow detection is same as for add,
1789 // except we need to look at the *complemented*
1790 // sign bit of the subtrahend (Rb), i.e., if the initial
1791 // signs are the *same* then no overflow can occur
1792 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1793 fault = Integer_Overflow_Fault;
1796 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1797 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1799 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1800 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1801 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1802 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1803 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1809 for (int i = 0; i < 8; ++i) {
1810 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1818 0x11: decode INTFUNC { // integer logical operations
1820 0x00: and({{ Rc = Ra & Rb_or_imm; }});
1821 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1822 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1823 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1824 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1825 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1827 // conditional moves
1828 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1829 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1830 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1831 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1832 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
1833 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1834 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1835 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
1837 // For AMASK, RA must be R31.
1839 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1842 // For IMPLVER, RA must be R31 and the B operand
1843 // must be the immediate value 1.
1847 // return EV5 for FULL_SYSTEM and EV6 otherwise
1860 // The mysterious 11.25...
1861 0x25: WarnUnimpl::eleven25();
1865 0x12: decode INTFUNC {
1866 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
1867 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
1868 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
1870 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
1871 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
1872 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
1873 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
1876 int bv = Rb_or_imm<2:0>;
1877 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
1880 int bv = Rb_or_imm<2:0>;
1881 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
1884 int bv = Rb_or_imm<2:0>;
1885 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
1888 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
1889 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
1890 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
1891 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
1894 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
1896 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
1898 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
1900 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
1901 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
1902 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
1903 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
1906 int bv = Rb_or_imm<2:0>;
1907 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
1910 int bv = Rb_or_imm<2:0>;
1911 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
1914 int bv = Rb_or_imm<2:0>;
1915 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
1919 uint64_t zapmask = 0;
1920 for (int i = 0; i < 8; ++i) {
1922 zapmask |= (mask(8) << (i * 8));
1927 uint64_t zapmask = 0;
1928 for (int i = 0; i < 8; ++i) {
1930 zapmask |= (mask(8) << (i * 8));
1936 0x13: decode INTFUNC { // integer multiplies
1937 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMULT);
1938 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMULT);
1941 mul128(Ra, Rb_or_imm, hi, lo);
1945 // 32-bit multiply with trap on overflow
1946 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
1947 int64_t Rbx = Rb_or_imm.sl;
1948 int64_t tmp = Rax * Rbx;
1949 // To avoid overflow, all the upper 32 bits must match
1950 // the sign bit of the lower 32. We code this as
1951 // checking the upper 33 bits for all 0s or all 1s.
1952 uint64_t sign_bits = tmp<63:31>;
1953 if (sign_bits != 0 && sign_bits != mask(33))
1954 fault = Integer_Overflow_Fault;
1958 // 64-bit multiply with trap on overflow
1960 mul128(Ra, Rb_or_imm, hi, lo);
1961 // all the upper 64 bits must match the sign bit of
1963 if (!((hi == 0 && lo<63:> == 0) ||
1964 (hi == mask(64) && lo<63:> == 1)))
1965 fault = Integer_Overflow_Fault;
1970 0x1c: decode INTFUNC {
1971 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
1972 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
1993 format BasicOperateWithNopCheck {
1995 31: ftoit({{ Rc = Fa.uq; }}, FloatCVT);
1998 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2005 // Conditional branches.
2007 0x39: beq({{ cond = (Ra == 0); }});
2008 0x3d: bne({{ cond = (Ra != 0); }});
2009 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2010 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2011 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2012 0x3a: blt({{ cond = (Ra.sq < 0); }});
2013 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2014 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2016 0x31: fbeq({{ cond = (Fa == 0); }});
2017 0x35: fbne({{ cond = (Fa != 0); }});
2018 0x36: fbge({{ cond = (Fa >= 0); }});
2019 0x37: fbgt({{ cond = (Fa > 0); }});
2020 0x33: fble({{ cond = (Fa <= 0); }});
2021 0x32: fblt({{ cond = (Fa < 0); }});
2024 // unconditional branches
2025 format UncondBranch {
2030 // indirect branches
2031 0x1a: decode JMPFUNC {
2036 3: jsr_coroutine(IsCall, IsReturn);
2040 // IEEE floating point
2041 0x14: decode FP_SHORTFUNC {
2042 // Integer to FP register moves must have RB == 31
2044 31: decode FP_FULLFUNC {
2045 format BasicOperateWithNopCheck {
2046 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCVT);
2047 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCVT);
2048 0x014: FailUnimpl::itoff(); // VAX-format conversion
2053 // Square root instructions must have FA == 31
2055 31: decode FP_TYPEFUNC {
2056 format FloatingPointOperate {
2057 #ifdef SS_COMPATIBLE_FP
2060 fault = Arithmetic_Fault;
2066 fault = Arithmetic_Fault;
2067 Fc.sf = sqrt(Fb.sf);
2072 fault = Arithmetic_Fault;
2079 // VAX-format sqrtf and sqrtg are not implemented
2080 0xa: FailUnimpl::sqrtfg();
2083 // IEEE floating point
2084 0x16: decode FP_SHORTFUNC_TOP2 {
2085 // The top two bits of the short function code break this space
2086 // into four groups: binary ops, compares, reserved, and conversions.
2087 // See Table 4-12 of AHB.
2088 // Most of these instructions may have various trapping and
2089 // rounding mode flags set; these are decoded in the
2090 // FloatingPointDecode template used by the
2091 // FloatingPointOperate format.
2093 // add/sub/mul/div: just decode on the short function code
2095 0: decode FP_TYPEFUNC {
2096 format FloatingPointOperate {
2097 #ifdef SS_COMPATIBLE_FP
2098 0x00: adds({{ Fc = Fa + Fb; }});
2099 0x01: subs({{ Fc = Fa - Fb; }});
2100 0x02: muls({{ Fc = Fa * Fb; }}, FloatMULT);
2101 0x03: divs({{ Fc = Fa / Fb; }}, FloatDIV);
2103 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2104 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2105 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMULT);
2106 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDIV);
2109 0x20: addt({{ Fc = Fa + Fb; }});
2110 0x21: subt({{ Fc = Fa - Fb; }});
2111 0x22: mult({{ Fc = Fa * Fb; }}, FloatMULT);
2112 0x23: divt({{ Fc = Fa / Fb; }}, FloatDIV);
2116 // Floating-point compare instructions must have the default
2117 // rounding mode, and may use the default trapping mode or
2118 // /SU. Both trapping modes are treated the same by M5; the
2119 // only difference on the real hardware (as far a I can tell)
2120 // is that without /SU you'd get an imprecise trap if you
2121 // tried to compare a NaN with something else (instead of an
2122 // "unordered" result).
2123 1: decode FP_FULLFUNC {
2124 format BasicOperateWithNopCheck {
2125 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2127 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2129 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2131 0x0a4, 0x5a4: cmptun({{ // unordered
2132 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2137 // The FP-to-integer and integer-to-FP conversion insts
2138 // require that FA be 31.
2140 31: decode FP_TYPEFUNC {
2141 format FloatingPointOperate {
2142 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2144 // The cvtts opcode is overloaded to be cvtst if the trap
2145 // mode is 2 or 6 (which are not valid otherwise)
2146 0x2c: decode FP_FULLFUNC {
2147 format BasicOperateWithNopCheck {
2148 // trap on denorm version "cvtst/s" is
2149 // simulated same as cvtst
2150 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2152 default: cvtts({{ Fc.sf = Fb; }});
2155 // The trapping mode for integer-to-FP conversions
2156 // must be /SUI or nothing; /U and /SU are not
2157 // allowed. The full set of rounding modes are
2158 // supported though.
2159 0x3c: decode FP_TRAPMODE {
2160 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2162 0x3e: decode FP_TRAPMODE {
2163 0,7: cvtqt({{ Fc = Fb.sq; }});
2171 0x17: decode FP_FULLFUNC {
2172 format BasicOperateWithNopCheck {
2174 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2177 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2180 // We treat the precise & imprecise trapping versions of
2181 // cvtql identically.
2182 0x130, 0x530: cvtqlv({{
2183 // To avoid overflow, all the upper 32 bits must match
2184 // the sign bit of the lower 32. We code this as
2185 // checking the upper 33 bits for all 0s or all 1s.
2186 uint64_t sign_bits = Fb.uq<63:31>;
2187 if (sign_bits != 0 && sign_bits != mask(33))
2188 fault = Integer_Overflow_Fault;
2189 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2192 0x020: cpys({{ // copy sign
2193 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2195 0x021: cpysn({{ // copy sign negated
2196 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2198 0x022: cpyse({{ // copy sign and exponent
2199 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2202 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2203 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2204 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2205 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2206 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2207 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2209 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2210 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2214 // miscellaneous mem-format ops
2215 0x18: decode MEMFUNC {
2222 format MiscPrefetch {
2223 0xf800: wh64({{ EA = Rb; }},
2224 {{ xc->writeHint(EA, 64); }},
2225 IsMemRef, IsStore, WrPort);
2228 format BasicOperate {
2231 Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
2237 // All of the barrier instructions below do nothing in
2238 // their execute() methods (hence the empty code blocks).
2239 // All of their functionality is hard-coded in the
2240 // pipeline based on the flags IsSerializing,
2241 // IsMemBarrier, and IsWriteBarrier. In the current
2242 // detailed CPU model, the execute() function only gets
2243 // called at fetch, so there's no way to generate pipeline
2244 // behavior at any other stage. Once we go to an
2245 // exec-in-exec CPU model we should be able to get rid of
2246 // these flags and implement this behavior via the
2247 // execute() methods.
2249 // trapb is just a barrier on integer traps, where excb is
2250 // a barrier on integer and FP traps. "EXCB is thus a
2251 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
2252 // them the same though.
2253 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
2254 0x0400: excb({{ }}, IsSerializing, No_OpClass);
2255 0x4000: mb({{ }}, IsMemBarrier, RdPort);
2256 0x4400: wmb({{ }}, IsWriteBarrier, WrPort);
2260 format BasicOperate {
2262 Ra = xc->readIntrFlag();
2263 if (!xc->misspeculating()) {
2268 Ra = xc->readIntrFlag();
2269 if (!xc->misspeculating()) {
2283 0x00: CallPal::call_pal({{
2286 && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
2287 // invalid pal function code, or attempt to do privileged
2288 // PAL call in non-kernel mode
2289 fault = Unimplemented_Opcode_Fault;
2294 if (!xc->misspeculating()) {
2295 // check to see if simulator wants to do something special
2296 // on this PAL call (including maybe suppress it)
2297 dopal = xc->simPalCheck(palFunc);
2300 AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
2301 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2305 // if we're misspeculating, it's still safe (if
2306 // unrealistic) to set NPC, as the control-flow change
2307 // won't get committed.
2309 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2314 0x00: decode PALFUNC {
2315 format EmulatedCallPal {
2317 if (!xc->misspeculating())
2318 SimExit(curTick, "halt instruction encountered");
2321 if (!xc->misspeculating())
2324 // Read uniq reg into ABI return value register (r0)
2325 0x9e: rduniq({{ R0 = Runiq; }});
2326 // Write uniq reg with value from ABI arg register (r16)
2327 0x9f: wruniq({{ Runiq = R16; }});
2333 format HwLoadStore {
2334 0x1b: decode HW_LDST_QUAD {
2335 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2336 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2339 0x1f: decode HW_LDST_COND {
2340 0: decode HW_LDST_QUAD {
2341 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2342 {{ Mem.ul = Ra<31:0>; }}, L);
2343 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2344 {{ Mem.uq = Ra.uq; }}, Q);
2347 1: FailUnimpl::hw_st_cond();
2351 format BasicOperate {
2352 0x1e: hw_rei({{ xc->hwrei(); }});
2354 // M5 special opcodes use the reserved 0x01 opcode space
2355 0x01: decode M5FUNC {
2357 if (!xc->misspeculating())
2358 AlphaPseudo::arm(xc->xcBase());
2361 if (!xc->misspeculating())
2362 AlphaPseudo::quiesce(xc->xcBase());
2365 if (!xc->misspeculating())
2366 AlphaPseudo::ivlb(xc->xcBase());
2369 if (!xc->misspeculating())
2370 AlphaPseudo::ivle(xc->xcBase());
2373 if (!xc->misspeculating())
2374 AlphaPseudo::m5exit_old(xc->xcBase());
2377 if (!xc->misspeculating())
2378 AlphaPseudo::m5exit(xc->xcBase());
2380 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
2382 if (!xc->misspeculating())
2383 AlphaPseudo::resetstats(xc->xcBase());
2386 if (!xc->misspeculating())
2387 AlphaPseudo::dumpstats(xc->xcBase());
2389 0x42: dumpresetstats({{
2390 if (!xc->misspeculating())
2391 AlphaPseudo::dumpresetstats(xc->xcBase());
2393 0x43: m5checkpoint({{
2394 if (!xc->misspeculating())
2395 AlphaPseudo::m5checkpoint(xc->xcBase());
2402 // this instruction is only valid in PAL mode
2403 if (!xc->inPalMode()) {
2404 fault = Unimplemented_Opcode_Fault;
2407 Ra = xc->readIpr(ipr_index, fault);
2411 // this instruction is only valid in PAL mode
2412 if (!xc->inPalMode()) {
2413 fault = Unimplemented_Opcode_Fault;
2416 xc->setIpr(ipr_index, Ra);
2417 if (traceData) { traceData->setData(Ra); }