3 // Alpha ISA description file.
21 #include "base/cprintf.hh"
22 #include "base/misc.hh"
23 #include "cpu/exec_context.hh"
24 #include "cpu/exetrace.hh"
25 #include "cpu/full_cpu/dyn_inst.hh"
26 #include "cpu/simple_cpu/simple_cpu.hh"
27 #include "cpu/static_inst.hh"
28 #include "sim/annotation.hh"
29 #include "sim/sim_exit.hh"
32 #include "arch/alpha/ev5.hh"
33 #include "arch/alpha/pseudo_inst.hh"
38 // Universal (format-independent) fields
39 def bitfield OPCODE <31:26>;
40 def bitfield RA <25:21>;
41 def bitfield RB <20:16>;
44 def signed bitfield MEMDISP <15: 0>; // displacement
45 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
47 // Memory-format jumps
48 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
49 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
52 def signed bitfield BRDISP <20: 0>; // displacement
54 // Integer operate format(s>;
55 def bitfield INTIMM <20:13>; // integer immediate (literal)
56 def bitfield IMM <12:12>; // immediate flag
57 def bitfield INTFUNC <11: 5>; // function code
58 def bitfield RC < 4: 0>; // dest reg
60 // Floating-point operate format
61 def bitfield FA <25:21>;
62 def bitfield FB <20:16>;
63 def bitfield FP_FULLFUNC <15: 5>; // complete function code
64 def bitfield FP_TRAPMODE <15:13>; // trapping mode
65 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
66 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
67 def bitfield FP_SRCTYPE <10: 9>; // source reg type
68 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
69 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
70 def bitfield FC < 4: 0>; // dest reg
73 def bitfield PALFUNC <25: 0>; // function code
75 // EV5 PAL instructions:
77 def bitfield HW_LDST_PHYS <15>; // address is physical
78 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
79 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
80 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
81 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
82 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
83 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
84 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
87 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
88 def bitfield HW_REI_MBZ <13: 0>; // must be zero
91 def bitfield HW_IPR_IDX <15:0>; // IPR index
94 def bitfield M5FUNC <7:0>;
99 'sb' : ('signed int', 8),
100 'ub' : ('unsigned int', 8),
101 'sw' : ('signed int', 16),
102 'uw' : ('unsigned int', 16),
103 'sl' : ('signed int', 32),
104 'ul' : ('unsigned int', 32),
105 'sq' : ('signed int', 64),
106 'uq' : ('unsigned int', 64),
107 'sf' : ('float', 32),
111 global operandTraitsMap
113 # Int regs default to unsigned, but code should not count on this.
114 # For clarity, descriptions that depend on unsigned behavior should
115 # explicitly specify '.uq'.
116 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
117 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
118 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
119 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
120 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
121 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
122 'Mem': MemOperandTraits('uq', None,
123 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
124 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
125 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
126 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
127 # The next two are hacks for non-full-system call-pal emulation
128 'R0': IntRegOperandTraits('uq', '0', None, 1),
129 'R16': IntRegOperandTraits('uq', '16', None, 1),
132 defineDerivedOperandVars()
136 // just temporary, while comparing with old code for debugging
137 // #define SS_COMPATIBLE_DISASSEMBLY
139 /// Check "FP enabled" machine status bit. Called when executing any FP
140 /// instruction in full-system mode.
141 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
142 /// if not. Non-full-system mode: always returns No_Fault.
145 inline Fault checkFpEnableFault(XC *xc)
147 Fault fault = No_Fault; // dummy... this ipr access should not fault
148 if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
155 inline Fault checkFpEnableFault(XC *xc)
162 * Base class for all Alpha static instructions.
164 class AlphaStaticInst : public StaticInst<AlphaISA>
168 /// Make AlphaISA register dependence tags directly visible in
169 /// this class and derived classes. Maybe these should really
170 /// live here and not in the AlphaISA namespace.
171 enum DependenceTags {
172 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
173 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
174 Uniq_DepTag = AlphaISA::Uniq_DepTag,
175 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
179 AlphaStaticInst(const char *mnem, MachInst _machInst,
181 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
185 /// Print a register name for disassembly given the unique
186 /// dependence tag number (FP or int).
187 void printReg(std::ostream &os, int reg)
189 if (reg < FP_Base_DepTag) {
190 ccprintf(os, "r%d", reg);
193 ccprintf(os, "f%d", reg - FP_Base_DepTag);
197 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
199 std::stringstream ss;
201 ccprintf(ss, "%-10s ", mnemonic);
203 // just print the first two source regs... if there's
204 // a third one, it's a read-modify-write dest (Rc),
206 if (_numSrcRegs > 0) {
207 printReg(ss, _srcRegIdx[0]);
209 if (_numSrcRegs > 1) {
211 printReg(ss, _srcRegIdx[1]);
214 // just print the first dest... if there's a second one,
215 // it's generally implicit
216 if (_numDestRegs > 0) {
219 printReg(ss, _destRegIdx[0]);
228 def template BasicDeclare {{
230 * Static instruction class for "%(mnemonic)s".
232 class %(class_name)s : public %(base_class)s
236 %(class_name)s(MachInst machInst)
237 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
242 %(exec_func_declarations)s
246 def template BasicExecute {{
247 Fault %(class_name)s::execute(%(cpu_model)s *xc,
248 Trace::InstRecord *traceData)
250 Fault fault = No_Fault;
257 if (fault == No_Fault) {
265 def template BasicDecode {{
266 return new %(class_name)s(machInst);
269 def template BasicDecodeWithMnemonic {{
270 return new %(class_name)s("%(mnemonic)s", machInst);
273 // The most basic instruction format... used only for a few misc. insts
274 def format BasicOperate(code, *flags) {{
275 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
276 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
281 ////////////////////////////////////////////////////////////////////
285 * Static instruction class for no-ops. This is a leaf class.
287 class Nop : public AlphaStaticInst
289 /// Disassembly of original instruction.
290 const std::string originalDisassembly;
294 Nop(const std::string _originalDisassembly, MachInst _machInst)
295 : AlphaStaticInst("nop", _machInst, No_OpClass),
296 originalDisassembly(_originalDisassembly)
303 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
305 #ifdef SS_COMPATIBLE_DISASSEMBLY
306 return originalDisassembly;
308 return csprintf("%-10s (%s)", "nop", originalDisassembly);
312 Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
315 Fault execute(FullCPUExecContext *, Trace::InstRecord *)
319 /// Helper function for decoding nops. Substitute Nop object
320 /// for original inst passed in as arg (and delete latter).
323 makeNop(AlphaStaticInst *inst)
325 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
332 return ('', 'return new Nop("%s", machInst);\n' % name, 'return No_Fault;')
336 // integer & FP operate instructions use Rc as dest, so check for
337 // Rc == 31 to detect nops
338 def template OperateNopCheckDecode {{
340 AlphaStaticInst *i = new %(class_name)s(machInst);
348 // Like BasicOperate format, but generates NOP if RC/FC == 31
349 def format BasicOperateWithNopCheck(code, *opt_args) {{
350 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
352 return iop.subst('BasicDeclare', 'OperateNopCheckDecode', 'BasicExecute')
356 ////////////////////////////////////////////////////////////////////
358 // Integer operate instructions
363 * Base class for integer immediate instructions.
365 class IntegerImm : public AlphaStaticInst
368 /// Immediate operand value (unsigned 8-bit int).
372 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
373 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
377 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
379 std::stringstream ss;
381 ccprintf(ss, "%-10s ", mnemonic);
383 // just print the first source reg... if there's
384 // a second one, it's a read-modify-write dest (Rc),
386 if (_numSrcRegs > 0) {
387 printReg(ss, _srcRegIdx[0]);
393 if (_numDestRegs > 0) {
395 printReg(ss, _destRegIdx[0]);
403 def template RegOrImmDecode {{
406 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
407 : (AlphaStaticInst *)new %(class_name)s(machInst);
415 // Primary format for integer operate instructions:
416 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
417 // - Generates NOP if RC == 31.
418 def format IntegerOperate(code, *opt_flags) {{
419 # If the code block contains 'Rb_or_imm', we define two instructions,
420 # one using 'Rb' and one using 'imm', and have the decoder select
422 uses_imm = (code.find('Rb_or_imm') != -1)
425 # base code is reg version:
426 # rewrite by substituting 'Rb' for 'Rb_or_imm'
427 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
428 # generate immediate version by substituting 'imm'
429 # note that imm takes no extenstion, so we extend
430 # the regexp to replace any extension as well
431 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
433 # generate declaration for register version
434 cblk = CodeBlock(code)
435 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
436 (decls, exec_code) = iop.subst('BasicDeclare', 'BasicExecute')
439 # append declaration for imm version
440 imm_cblk = CodeBlock(imm_code)
441 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
443 (imm_decls, imm_exec_code) = \
444 imm_iop.subst('BasicDeclare', 'BasicExecute')
446 exec_code += imm_exec_code
447 # decode checks IMM bit to pick correct version
448 decode = iop.subst('RegOrImmDecode')
450 # no imm version: just check for nop
451 decode = iop.subst('OperateNopCheckDecode')
453 return (decls, decode, exec_code)
457 ////////////////////////////////////////////////////////////////////
459 // Floating-point instructions
461 // Note that many FP-type instructions which do not support all the
462 // various rounding & trapping modes use the simpler format
463 // BasicOperateWithNopCheck.
468 * Base class for general floating-point instructions. Includes
469 * support for various Alpha rounding and trapping modes. Only FP
470 * instructions that require this support are derived from this
471 * class; the rest derive directly from AlphaStaticInst.
473 class AlphaFP : public AlphaStaticInst
476 /// Alpha FP rounding modes.
478 Chopped = 0, ///< round toward zero
479 Minus_Infinity = 1, ///< round toward minus infinity
480 Normal = 2, ///< round to nearest (default)
481 Dynamic = 3, ///< use FPCR setting (in instruction)
482 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
485 /// Alpha FP trapping modes.
486 /// For instructions that produce integer results, the
487 /// "Underflow Enable" modes really mean "Overflow Enable", and
488 /// the assembly modifier is V rather than U.
490 /// default: nothing enabled
491 Imprecise = 0, ///< no modifier
492 /// underflow/overflow traps enabled, inexact disabled
493 Underflow_Imprecise = 1, ///< /U or /V
494 Underflow_Precise = 5, ///< /SU or /SV
495 /// underflow/overflow and inexact traps enabled
496 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
501 static const int alphaToC99RoundingMode[];
504 /// Map enum RoundingMode values to disassembly suffixes.
505 static const char *roundingModeSuffix[];
506 /// Map enum TrappingMode values to FP disassembly suffixes.
507 static const char *fpTrappingModeSuffix[];
508 /// Map enum TrappingMode values to integer disassembly suffixes.
509 static const char *intTrappingModeSuffix[];
511 /// This instruction's rounding mode.
512 RoundingMode roundingMode;
513 /// This instruction's trapping mode.
514 TrappingMode trappingMode;
517 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
518 : AlphaStaticInst(mnem, _machInst, __opClass),
519 roundingMode((enum RoundingMode)FP_ROUNDMODE),
520 trappingMode((enum TrappingMode)FP_TRAPMODE)
522 if (trappingMode != Imprecise) {
523 warn("precise FP traps unimplemented\n");
529 getC99RoundingMode(uint64_t fpcr_val)
531 if (roundingMode == Dynamic) {
532 return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
535 return alphaToC99RoundingMode[roundingMode];
540 // This differs from the AlphaStaticInst version only in
541 // printing suffixes for non-default rounding & trapping modes.
542 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
544 std::string mnem_str(mnemonic);
546 #ifndef SS_COMPATIBLE_DISASSEMBLY
547 std::string suffix("");
548 suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
549 ? fpTrappingModeSuffix[trappingMode]
550 : intTrappingModeSuffix[trappingMode]);
551 suffix += roundingModeSuffix[roundingMode];
554 mnem_str = csprintf("%s/%s", mnemonic, suffix);
558 std::stringstream ss;
559 ccprintf(ss, "%-10s ", mnem_str.c_str());
561 // just print the first two source regs... if there's
562 // a third one, it's a read-modify-write dest (Rc),
564 if (_numSrcRegs > 0) {
565 printReg(ss, _srcRegIdx[0]);
567 if (_numSrcRegs > 1) {
569 printReg(ss, _srcRegIdx[1]);
572 // just print the first dest... if there's a second one,
573 // it's generally implicit
574 if (_numDestRegs > 0) {
577 printReg(ss, _destRegIdx[0]);
585 const int AlphaFP::alphaToC99RoundingMode[] = {
586 FE_TOWARDZERO, // Chopped
587 FE_DOWNWARD, // Minus_Infinity
588 FE_TONEAREST, // Normal
589 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
593 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
594 // mark invalid trapping modes, but don't fail on them, because
595 // you could decode anything on a misspeculated path
596 const char *AlphaFP::fpTrappingModeSuffix[] =
597 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
598 const char *AlphaFP::intTrappingModeSuffix[] =
599 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
603 def template FloatingPointDecode {{
605 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
606 && FP_ROUNDMODE == AlphaFP::Normal);
608 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
609 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
619 // General format for floating-point operate instructions:
620 // - Checks trapping and rounding mode flags. Trapping modes
621 // currently unimplemented (will fail).
622 // - Generates NOP if FC == 31.
623 def format FloatingPointOperate(code, *opt_args) {{
624 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
625 decode = iop.subst('FloatingPointDecode')
627 fast_iop = InstObjParams(name, Name + 'Fast', 'AlphaFP',
628 CodeBlock(code), opt_args)
629 (fast_declare, fast_exec) = fast_iop.subst('BasicDeclare', 'BasicExecute')
631 gen_code_prefix = r'''
633 fesetround(getC99RoundingMode(xc->readFpcr()));
636 gen_code_suffix = r'''
638 fesetround(FE_TONEAREST);
642 gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
643 CodeBlock(gen_code_prefix + code + gen_code_suffix), opt_args)
644 (gen_declare, gen_exec) = gen_iop.subst('BasicDeclare', 'BasicExecute')
646 return (fast_declare + gen_declare, decode, fast_exec + gen_exec)
650 ////////////////////////////////////////////////////////////////////
652 // Memory-format instructions: LoadAddress, Load, Store
657 * Base class for general Alpha memory-format instructions.
659 class Memory : public AlphaStaticInst
663 /// Displacement for EA calculation (signed).
665 /// Memory request flags. See mem_req_base.hh.
666 unsigned memAccessFlags;
669 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
670 : AlphaStaticInst(mnem, _machInst, __opClass),
671 disp(MEMDISP), memAccessFlags(0)
675 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
677 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
678 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
683 * Base class for a few miscellaneous memory-format insts
684 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
685 * None of these instructions has a destination register either.
687 class MemoryNoDisp : public AlphaStaticInst
690 /// Memory request flags. See mem_req_base.hh.
691 unsigned memAccessFlags;
694 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass)
695 : AlphaStaticInst(mnem, _machInst, __opClass),
700 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
702 return csprintf("%-10s (r%d)", mnemonic, RB);
707 * Base class for "fake" effective-address computation
708 * instructions returnded by eaCompInst().
710 class EACompBase : public AlphaStaticInst
714 EACompBase(MachInst machInst)
715 : AlphaStaticInst("(eacomp)", machInst, IntALU)
719 Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
720 { panic("attempt to execute eacomp"); }
722 Fault execute(FullCPUExecContext *, Trace::InstRecord *)
723 { panic("attempt to execute eacomp"); }
727 * Base class for "fake" memory-access instructions returnded by
730 class MemAccBase : public AlphaStaticInst
734 MemAccBase(MachInst machInst, OpClass __opClass)
735 : AlphaStaticInst("(memacc)", machInst, __opClass)
739 Fault execute(SimpleCPUExecContext *, Trace::InstRecord *)
740 { panic("attempt to execute memacc"); }
742 Fault execute(FullCPUExecContext *, Trace::InstRecord *)
743 { panic("attempt to execute memacc"); }
749 def format LoadAddress(code) {{
750 iop = InstObjParams(name, Name, 'Memory', CodeBlock(code))
751 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
755 def template LoadStoreDeclare {{
757 * Static instruction class for "%(mnemonic)s".
759 class %(class_name)s : public %(base_class)s
764 * "Fake" effective address computation class for "%(mnemonic)s".
766 class EAComp : public EACompBase
770 EAComp(MachInst machInst)
771 : EACompBase(machInst)
778 * "Fake" memory access instruction class for "%(mnemonic)s".
780 class MemAcc : public MemAccBase
784 MemAcc(MachInst machInst)
785 : MemAccBase(machInst, %(op_class)s)
787 %(memacc_constructor)s;
791 /// Pointer to EAComp object.
792 StaticInstPtr<AlphaISA> eaCompPtr;
793 /// Pointer to MemAcc object.
794 StaticInstPtr<AlphaISA> memAccPtr;
798 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
799 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
802 %(class_name)s(MachInst machInst)
803 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
804 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
809 %(exec_func_declarations)s
813 def template LoadStoreExecute {{
814 Fault %(class_name)s::execute(%(cpu_model)s *xc,
815 Trace::InstRecord *traceData)
818 Fault fault = No_Fault;
825 if (fault == No_Fault) {
830 if (fault == No_Fault) {
834 if (fault == No_Fault) {
838 if (fault == No_Fault) {
846 def template PrefetchDeclare {{
848 * Static instruction class for "%(mnemonic)s".
850 class %(class_name)s : public %(base_class)s
855 * "Fake" effective address computation class for "%(mnemonic)s".
857 class EAComp : public EACompBase
861 EAComp(MachInst machInst)
862 : EACompBase(machInst)
869 * "Fake" memory access instruction class for "%(mnemonic)s".
871 class MemAcc : public MemAccBase
875 MemAcc(MachInst machInst)
876 : MemAccBase(machInst, %(op_class)s)
878 %(memacc_constructor)s;
882 /// Pointer to EAComp object.
883 StaticInstPtr<AlphaISA> eaCompPtr;
884 /// Pointer to MemAcc object.
885 StaticInstPtr<AlphaISA> memAccPtr;
889 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
890 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
893 %(class_name)s(MachInst machInst)
894 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
895 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
900 %(exec_func_declarations)s
904 def template PrefetchExecute {{
905 Fault %(class_name)s::execute(%(cpu_model)s *xc,
906 Trace::InstRecord *traceData)
909 Fault fault = No_Fault;
916 if (fault == No_Fault) {
917 xc->prefetch(EA, memAccessFlags);
924 // load instructions use Ra as dest, so check for
925 // Ra == 31 to detect nops
926 def template LoadNopCheckDecode {{
928 AlphaStaticInst *i = new %(class_name)s(machInst);
937 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
938 def template LoadPrefetchCheckDecode {{
941 return new %(class_name)s(machInst);
944 return new %(class_name)sPrefetch(machInst);
952 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
953 base_class = 'Memory', flags = [],
954 declare_template = 'LoadStoreDeclare',
955 decode_template = 'BasicDecode',
956 exec_template = 'LoadStoreExecute'):
957 # Segregate flags into instruction flags (handled by InstObjParams)
958 # and memory access flags (handled here).
960 # Would be nice to autogenerate this list, but oh well.
961 valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
965 if f in valid_mem_flags:
970 ea_cblk = CodeBlock(ea_code)
971 memacc_cblk = CodeBlock(memacc_code)
972 postacc_cblk = CodeBlock(postacc_code)
974 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
975 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
977 iop.ea_constructor = ea_cblk.constructor
978 iop.ea_code = ea_cblk.code
979 iop.memacc_constructor = memacc_cblk.constructor
980 iop.memacc_code = memacc_cblk.code
981 iop.postacc_code = postacc_cblk.code
983 mem_flags = string.join(mem_flags, '|')
985 iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
987 return iop.subst(declare_template, decode_template, exec_template)
991 def format LoadOrNop(ea_code, memacc_code, *flags) {{
992 return LoadStoreBase(name, Name, ea_code, memacc_code,
994 decode_template = 'LoadNopCheckDecode')
998 // Note that the flags passed in apply only to the prefetch version
999 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1000 # declare the load instruction object and generate the decode block
1001 (decls, decode, exec_code) = \
1002 LoadStoreBase(name, Name, ea_code, memacc_code,
1003 decode_template = 'LoadPrefetchCheckDecode')
1005 # Declare the prefetch instruction object.
1007 # convert flags from tuple to list to make them mutable
1008 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'RdPort']
1010 (pfdecls, pfdecode, pfexec) = \
1011 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1013 declare_template = 'PrefetchDeclare',
1014 exec_template = 'PrefetchExecute')
1016 return (decls + pfdecls, decode, exec_code + pfexec)
1020 def format Store(ea_code, memacc_code, *flags) {{
1021 return LoadStoreBase(name, Name, ea_code, memacc_code,
1026 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1027 return LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1032 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1033 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1034 return LoadStoreBase(name, Name, ea_code, memacc_code,
1035 flags = flags, base_class = 'MemoryNoDisp')
1039 ////////////////////////////////////////////////////////////////////
1045 * Base class for instructions whose disassembly is not purely a
1046 * function of the machine instruction (i.e., it depends on the
1047 * PC). This class overrides the disassemble() method to check
1048 * the PC and symbol table values before re-using a cached
1049 * disassembly string. This is necessary for branches and jumps,
1050 * where the disassembly string includes the target address (which
1051 * may depend on the PC and/or symbol table).
1053 class PCDependentDisassembly : public AlphaStaticInst
1056 /// Cached program counter from last disassembly
1058 /// Cached symbol table pointer from last disassembly
1059 const SymbolTable *cachedSymtab;
1062 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1064 : AlphaStaticInst(mnem, _machInst, __opClass),
1065 cachedPC(0), cachedSymtab(0)
1069 const std::string &disassemble(Addr pc, const SymbolTable *symtab)
1071 if (!cachedDisassembly ||
1072 pc != cachedPC || symtab != cachedSymtab)
1074 if (cachedDisassembly)
1075 delete cachedDisassembly;
1078 new std::string(generateDisassembly(pc, symtab));
1080 cachedSymtab = symtab;
1083 return *cachedDisassembly;
1088 * Base class for branches (PC-relative control transfers),
1089 * conditional or unconditional.
1091 class Branch : public PCDependentDisassembly
1094 /// Displacement to target address (signed).
1098 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1099 : PCDependentDisassembly(mnem, _machInst, __opClass),
1104 Addr branchTarget(Addr branchPC) const
1106 return branchPC + 4 + disp;
1109 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1111 std::stringstream ss;
1113 ccprintf(ss, "%-10s ", mnemonic);
1115 // There's only one register arg (RA), but it could be
1116 // either a source (the condition for conditional
1117 // branches) or a destination (the link reg for
1118 // unconditional branches)
1119 if (_numSrcRegs > 0) {
1120 printReg(ss, _srcRegIdx[0]);
1123 else if (_numDestRegs > 0) {
1124 printReg(ss, _destRegIdx[0]);
1128 #ifdef SS_COMPATIBLE_DISASSEMBLY
1129 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1135 Addr target = pc + 4 + disp;
1138 if (symtab && symtab->findSymbol(target, str))
1141 ccprintf(ss, "0x%x", target);
1148 * Base class for jumps (register-indirect control transfers). In
1149 * the Alpha ISA, these are always unconditional.
1151 class Jump : public PCDependentDisassembly
1155 /// Displacement to target address (signed).
1160 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1161 : PCDependentDisassembly(mnem, _machInst, __opClass),
1166 Addr branchTarget(ExecContext *xc) const
1168 Addr NPC = xc->readPC() + 4;
1169 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
1170 return (Rb & ~3) | (NPC & 1);
1173 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1175 std::stringstream ss;
1177 ccprintf(ss, "%-10s ", mnemonic);
1179 #ifdef SS_COMPATIBLE_DISASSEMBLY
1180 if (_numDestRegs == 0) {
1186 if (_numDestRegs > 0) {
1187 printReg(ss, _destRegIdx[0]);
1191 ccprintf(ss, "(r%d)", RB);
1198 def template JumpOrBranchDecode {{
1200 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1201 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1204 def format CondBranch(code) {{
1205 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1206 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1207 ('IsDirectControl', 'IsCondControl'))
1208 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1212 global UncondCtrlBase
1213 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1214 # Declare basic control transfer w/o link (i.e. link reg is R31)
1215 nolink_code = 'NPC = %s;\n' % npc_expr
1216 nolink_iop = InstObjParams(name, Name, base_class,
1217 CodeBlock(nolink_code), flags)
1218 (decls, exec_code) = nolink_iop.subst('BasicDeclare', 'BasicExecute')
1220 # Generate declaration of '*AndLink' version, append to decls
1221 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1222 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1223 CodeBlock(link_code), flags)
1224 (link_decls, link_exec_code) = \
1225 link_iop.subst('BasicDeclare', 'BasicExecute')
1227 exec_code += link_exec_code
1229 # need to use link_iop for the decode template since it is expecting
1230 # the shorter version of class_name (w/o "AndLink")
1231 return (decls, nolink_iop.subst('JumpOrBranchDecode'), exec_code)
1234 def format UncondBranch(*flags) {{
1235 flags += ('IsUncondControl', 'IsDirectControl')
1236 return UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1239 def format Jump(*flags) {{
1240 flags += ('IsUncondControl', 'IsIndirectControl')
1241 return UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1247 * Base class for emulated call_pal calls (used only in
1248 * non-full-system mode).
1250 class EmulatedCallPal : public AlphaStaticInst
1255 EmulatedCallPal(const char *mnem, MachInst _machInst,
1257 : AlphaStaticInst(mnem, _machInst, __opClass)
1261 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1263 #ifdef SS_COMPATIBLE_DISASSEMBLY
1264 return csprintf("%s %s", "call_pal", mnemonic);
1266 return csprintf("%-10s %s", "call_pal", mnemonic);
1272 def format EmulatedCallPal(code) {{
1273 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code))
1274 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1279 * Base class for full-system-mode call_pal instructions.
1280 * Probably could turn this into a leaf class and get rid of the
1283 class CallPalBase : public AlphaStaticInst
1286 int palFunc; ///< Function code part of instruction
1287 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1288 bool palValid; ///< is the function code valid?
1289 bool palPriv; ///< is this call privileged?
1292 CallPalBase(const char *mnem, MachInst _machInst,
1294 : AlphaStaticInst(mnem, _machInst, __opClass),
1297 // From the 21164 HRM (paraphrased):
1298 // Bit 7 of the function code (mask 0x80) indicates
1299 // whether the call is privileged (bit 7 == 0) or
1300 // unprivileged (bit 7 == 1). The privileged call table
1301 // starts at 0x2000, the unprivielged call table starts at
1302 // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
1304 const int palPrivMask = 0x80;
1305 const int palOffsetMask = 0x3f;
1307 // Pal call is invalid unless all other bits are 0
1308 palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
1309 palPriv = ((machInst & palPrivMask) == 0);
1310 int shortPalFunc = (machInst & palOffsetMask);
1311 // Add 1 to base to set pal-mode bit
1312 palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
1315 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1317 return csprintf("%-10s %#x", "call_pal", palFunc);
1323 def format CallPal(code) {{
1324 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code))
1325 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1333 * Base class for hw_ld and hw_st.
1335 class HwLoadStore : public AlphaStaticInst
1339 /// Displacement for EA calculation (signed).
1341 /// Memory request flags. See mem_req_base.hh.
1342 unsigned memAccessFlags;
1345 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass)
1346 : AlphaStaticInst(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
1349 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1350 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1351 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1352 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1355 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1357 #ifdef SS_COMPATIBLE_DISASSEMBLY
1358 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1360 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1361 const char *lock_str =
1362 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1364 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1365 mnemonic, RA, disp, RB,
1366 HW_LDST_PHYS ? ",PHYS" : "",
1367 HW_LDST_ALT ? ",ALT" : "",
1368 HW_LDST_QUAD ? ",QUAD" : "",
1369 HW_LDST_VPTE ? ",VPTE" : "",
1377 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1378 return LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1380 base_class = 'HwLoadStore')
1384 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1385 return LoadStoreBase(name, Name + class_ext,
1386 ea_code, memacc_code, postacc_code,
1388 base_class = 'HwLoadStore')
1394 * Base class for hw_mfpr and hw_mtpr.
1396 class HwMoveIPR : public AlphaStaticInst
1399 /// Index of internal processor register.
1403 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1404 : AlphaStaticInst(mnem, _machInst, __opClass),
1405 ipr_index(HW_IPR_IDX)
1409 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1411 if (_numSrcRegs > 0) {
1413 return csprintf("%-10s r%d,IPR(%#x)",
1414 mnemonic, RA, ipr_index);
1418 return csprintf("%-10s IPR(%#x),r%d",
1419 mnemonic, ipr_index, RA);
1425 def format HwMoveIPR(code) {{
1426 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1427 return iop.subst('BasicDeclare', 'BasicDecode', 'BasicExecute')
1432 * Static instruction class for unimplemented instructions that
1433 * cause simulator termination. Note that these are recognized
1434 * (legal) instructions that the simulator does not support; the
1435 * 'Unknown' class is used for unrecognized/illegal instructions.
1436 * This is a leaf class.
1438 class FailUnimplemented : public AlphaStaticInst
1442 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1443 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1447 Fault execute(SimpleCPUExecContext *xc,
1448 Trace::InstRecord *traceData)
1450 panic("attempt to execute unimplemented instruction '%s' "
1451 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1452 return Unimplemented_Opcode_Fault;
1455 Fault execute(FullCPUExecContext *xc,
1456 Trace::InstRecord *traceData)
1458 // don't panic if this is a misspeculated instruction
1459 if (!xc->misspeculating())
1460 panic("attempt to execute unimplemented instruction '%s' "
1461 "(inst 0x%08x, opcode 0x%x)",
1462 mnemonic, machInst, OPCODE);
1463 return Unimplemented_Opcode_Fault;
1466 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1468 return csprintf("%-10s (unimplemented)", mnemonic);
1473 * Base class for unimplemented instructions that cause a warning
1474 * to be printed (but do not terminate simulation). This
1475 * implementation is a little screwy in that it will print a
1476 * warning for each instance of a particular unimplemented machine
1477 * instruction, not just for each unimplemented opcode. Should
1478 * probably make the 'warned' flag a static member of the derived
1481 class WarnUnimplemented : public AlphaStaticInst
1484 /// Have we warned on this instruction yet?
1489 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1490 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1494 Fault execute(SimpleCPUExecContext *xc,
1495 Trace::InstRecord *traceData)
1498 warn("instruction '%s' unimplemented\n", mnemonic);
1505 Fault execute(FullCPUExecContext *xc,
1506 Trace::InstRecord *traceData)
1508 if (!xc->misspeculating() && !warned) {
1509 warn("instruction '%s' unimplemented\n", mnemonic);
1516 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1518 #ifdef SS_COMPATIBLE_DISASSEMBLY
1519 return csprintf("%-10s", mnemonic);
1521 return csprintf("%-10s (unimplemented)", mnemonic);
1527 def template WarnUnimplDeclare {{
1529 * Static instruction class for "%(mnemonic)s".
1531 class %(class_name)s : public %(base_class)s
1535 %(class_name)s(MachInst machInst)
1536 : %(base_class)s("%(mnemonic)s", machInst)
1543 def format FailUnimpl() {{
1544 iop = InstObjParams(name, 'FailUnimplemented')
1545 return ('', iop.subst('BasicDecodeWithMnemonic'), '')
1548 def format WarnUnimpl() {{
1549 iop = InstObjParams(name, Name, 'WarnUnimplemented')
1550 return iop.subst('WarnUnimplDeclare', 'BasicDecode') + ['']
1555 * Static instruction class for unknown (illegal) instructions.
1556 * These cause simulator termination if they are executed in a
1557 * non-speculative mode. This is a leaf class.
1559 class Unknown : public AlphaStaticInst
1563 Unknown(MachInst _machInst)
1564 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1568 Fault execute(SimpleCPUExecContext *xc,
1569 Trace::InstRecord *traceData)
1571 panic("attempt to execute unknown instruction "
1572 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1573 return Unimplemented_Opcode_Fault;
1576 Fault execute(FullCPUExecContext *xc,
1577 Trace::InstRecord *traceData)
1579 // don't panic if this is a misspeculated instruction
1580 if (!xc->misspeculating())
1581 panic("attempt to execute unknown instruction "
1582 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1583 return Unimplemented_Opcode_Fault;
1586 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1588 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1589 "unknown", machInst, OPCODE);
1594 def format Unknown() {{
1595 return ('', 'return new Unknown(machInst);\n', '')
1600 /// Return opa + opb, summing carry into third arg.
1602 addc(uint64_t opa, uint64_t opb, int &carry)
1604 uint64_t res = opa + opb;
1605 if (res < opa || res < opb)
1610 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1611 /// product in res_hi and res_lo.
1613 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1615 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1616 uint64_t opa_hi = opa<63:32>;
1617 uint64_t opa_lo = opa<31:0>;
1618 uint64_t opb_hi = opb<63:32>;
1619 uint64_t opb_lo = opb<31:0>;
1621 res_lo = opa_lo * opb_lo;
1623 // The middle partial products logically belong in bit
1624 // positions 95 to 32. Thus the lower 32 bits of each product
1625 // sum into the upper 32 bits of the low result, while the
1626 // upper 32 sum into the low 32 bits of the upper result.
1627 uint64_t partial1 = opa_hi * opb_lo;
1628 uint64_t partial2 = opa_lo * opb_hi;
1630 uint64_t partial1_lo = partial1<31:0> << 32;
1631 uint64_t partial1_hi = partial1<63:32>;
1632 uint64_t partial2_lo = partial2<31:0> << 32;
1633 uint64_t partial2_hi = partial2<63:32>;
1635 // Add partial1_lo and partial2_lo to res_lo, keeping track
1636 // of any carries out
1638 res_lo = addc(partial1_lo, res_lo, carry_out);
1639 res_lo = addc(partial2_lo, res_lo, carry_out);
1641 // Now calculate the high 64 bits...
1642 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1645 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1646 /// See Table 2-2 of Alpha AHB.
1650 int hibit = old_exp<7:>;
1651 int lobits = old_exp<6:0>;
1654 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1657 return (lobits == 0) ? 0 : (0x380 | lobits);
1661 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1662 /// representation to be stored in an FP reg.
1664 s_to_t(uint32_t s_val)
1666 uint64_t tmp = s_val;
1667 return (tmp<31:> << 63 // sign bit
1668 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1669 | tmp<22:0> << 29); // fraction
1672 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1673 /// S-floating representation to be stored in memory.
1675 t_to_s(uint64_t t_val)
1677 return (t_val<63:62> << 30 // sign bit & hi exp bit
1678 | t_val<58:29>); // rest of exp & fraction
1682 decode OPCODE default Unknown::unknown() {
1684 format LoadAddress {
1685 0x08: lda({{ Ra = Rb + disp; }});
1686 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1690 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1691 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1692 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1693 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1694 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1695 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1696 0x20: copy_load({{EA = Ra;}},
1697 {{ fault = xc->copySrcTranslate(EA);}},
1698 IsMemRef, IsLoad, IsCopy);
1701 format LoadOrPrefetch {
1702 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1703 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1704 // IsFloating flag on lds gets the prefetch to disassemble
1705 // using f31 instead of r31... funcitonally it's unnecessary
1706 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1707 PF_EXCLUSIVE, IsFloating);
1711 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1712 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1713 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1714 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1715 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1716 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1717 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1718 0x24: copy_store({{EA = Rb;}},
1719 {{ fault = xc->copy(EA);}},
1720 IsMemRef, IsStore, IsCopy);
1724 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1726 uint64_t tmp = Mem_write_result;
1728 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1730 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1732 uint64_t tmp = Mem_write_result;
1733 // If the write operation returns 0 or 1, then
1734 // this was a conventional store conditional,
1735 // and the value indicates the success/failure
1736 // of the operation. If another value is
1737 // returned, then this was a Turbolaser
1738 // mailbox access, and we don't update the
1739 // result register at all.
1740 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1744 format IntegerOperate {
1746 0x10: decode INTFUNC { // integer arithmetic operations
1748 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1750 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1751 // signed overflow occurs when operands have same sign
1752 // and sign of result does not match.
1753 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1754 fault = Integer_Overflow_Fault;
1757 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1758 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1760 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1762 uint64_t tmp = Ra + Rb_or_imm;
1763 // signed overflow occurs when operands have same sign
1764 // and sign of result does not match.
1765 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1766 fault = Integer_Overflow_Fault;
1769 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1770 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1772 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1774 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1775 // signed overflow detection is same as for add,
1776 // except we need to look at the *complemented*
1777 // sign bit of the subtrahend (Rb), i.e., if the initial
1778 // signs are the *same* then no overflow can occur
1779 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1780 fault = Integer_Overflow_Fault;
1783 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1784 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1786 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1788 uint64_t tmp = Ra - Rb_or_imm;
1789 // signed overflow detection is same as for add,
1790 // except we need to look at the *complemented*
1791 // sign bit of the subtrahend (Rb), i.e., if the initial
1792 // signs are the *same* then no overflow can occur
1793 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1794 fault = Integer_Overflow_Fault;
1797 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1798 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1800 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1801 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1802 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1803 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1804 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1810 for (int i = 0; i < 8; ++i) {
1811 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1819 0x11: decode INTFUNC { // integer logical operations
1821 0x00: and({{ Rc = Ra & Rb_or_imm; }});
1822 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1823 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1824 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1825 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1826 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1828 // conditional moves
1829 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1830 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1831 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1832 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1833 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
1834 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1835 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1836 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
1838 // For AMASK, RA must be R31.
1840 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1843 // For IMPLVER, RA must be R31 and the B operand
1844 // must be the immediate value 1.
1848 // return EV5 for FULL_SYSTEM and EV6 otherwise
1861 // The mysterious 11.25...
1862 0x25: WarnUnimpl::eleven25();
1866 0x12: decode INTFUNC {
1867 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
1868 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
1869 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
1871 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
1872 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
1873 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
1874 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
1877 int bv = Rb_or_imm<2:0>;
1878 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
1881 int bv = Rb_or_imm<2:0>;
1882 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
1885 int bv = Rb_or_imm<2:0>;
1886 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
1889 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
1890 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
1891 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
1892 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
1895 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
1897 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
1899 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
1901 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
1902 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
1903 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
1904 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
1907 int bv = Rb_or_imm<2:0>;
1908 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
1911 int bv = Rb_or_imm<2:0>;
1912 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
1915 int bv = Rb_or_imm<2:0>;
1916 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
1920 uint64_t zapmask = 0;
1921 for (int i = 0; i < 8; ++i) {
1923 zapmask |= (mask(8) << (i * 8));
1928 uint64_t zapmask = 0;
1929 for (int i = 0; i < 8; ++i) {
1931 zapmask |= (mask(8) << (i * 8));
1937 0x13: decode INTFUNC { // integer multiplies
1938 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMULT);
1939 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMULT);
1942 mul128(Ra, Rb_or_imm, hi, lo);
1946 // 32-bit multiply with trap on overflow
1947 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
1948 int64_t Rbx = Rb_or_imm.sl;
1949 int64_t tmp = Rax * Rbx;
1950 // To avoid overflow, all the upper 32 bits must match
1951 // the sign bit of the lower 32. We code this as
1952 // checking the upper 33 bits for all 0s or all 1s.
1953 uint64_t sign_bits = tmp<63:31>;
1954 if (sign_bits != 0 && sign_bits != mask(33))
1955 fault = Integer_Overflow_Fault;
1959 // 64-bit multiply with trap on overflow
1961 mul128(Ra, Rb_or_imm, hi, lo);
1962 // all the upper 64 bits must match the sign bit of
1964 if (!((hi == 0 && lo<63:> == 0) ||
1965 (hi == mask(64) && lo<63:> == 1)))
1966 fault = Integer_Overflow_Fault;
1971 0x1c: decode INTFUNC {
1972 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
1973 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
1994 format BasicOperateWithNopCheck {
1996 31: ftoit({{ Rc = Fa.uq; }}, FloatCVT);
1999 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2006 // Conditional branches.
2008 0x39: beq({{ cond = (Ra == 0); }});
2009 0x3d: bne({{ cond = (Ra != 0); }});
2010 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2011 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2012 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2013 0x3a: blt({{ cond = (Ra.sq < 0); }});
2014 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2015 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2017 0x31: fbeq({{ cond = (Fa == 0); }});
2018 0x35: fbne({{ cond = (Fa != 0); }});
2019 0x36: fbge({{ cond = (Fa >= 0); }});
2020 0x37: fbgt({{ cond = (Fa > 0); }});
2021 0x33: fble({{ cond = (Fa <= 0); }});
2022 0x32: fblt({{ cond = (Fa < 0); }});
2025 // unconditional branches
2026 format UncondBranch {
2031 // indirect branches
2032 0x1a: decode JMPFUNC {
2037 3: jsr_coroutine(IsCall, IsReturn);
2041 // IEEE floating point
2042 0x14: decode FP_SHORTFUNC {
2043 // Integer to FP register moves must have RB == 31
2045 31: decode FP_FULLFUNC {
2046 format BasicOperateWithNopCheck {
2047 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCVT);
2048 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCVT);
2049 0x014: FailUnimpl::itoff(); // VAX-format conversion
2054 // Square root instructions must have FA == 31
2056 31: decode FP_TYPEFUNC {
2057 format FloatingPointOperate {
2058 #ifdef SS_COMPATIBLE_FP
2061 fault = Arithmetic_Fault;
2067 fault = Arithmetic_Fault;
2068 Fc.sf = sqrt(Fb.sf);
2073 fault = Arithmetic_Fault;
2080 // VAX-format sqrtf and sqrtg are not implemented
2081 0xa: FailUnimpl::sqrtfg();
2084 // IEEE floating point
2085 0x16: decode FP_SHORTFUNC_TOP2 {
2086 // The top two bits of the short function code break this space
2087 // into four groups: binary ops, compares, reserved, and conversions.
2088 // See Table 4-12 of AHB.
2089 // Most of these instructions may have various trapping and
2090 // rounding mode flags set; these are decoded in the
2091 // FloatingPointDecode template used by the
2092 // FloatingPointOperate format.
2094 // add/sub/mul/div: just decode on the short function code
2096 0: decode FP_TYPEFUNC {
2097 format FloatingPointOperate {
2098 #ifdef SS_COMPATIBLE_FP
2099 0x00: adds({{ Fc = Fa + Fb; }});
2100 0x01: subs({{ Fc = Fa - Fb; }});
2101 0x02: muls({{ Fc = Fa * Fb; }}, FloatMULT);
2102 0x03: divs({{ Fc = Fa / Fb; }}, FloatDIV);
2104 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2105 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2106 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMULT);
2107 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDIV);
2110 0x20: addt({{ Fc = Fa + Fb; }});
2111 0x21: subt({{ Fc = Fa - Fb; }});
2112 0x22: mult({{ Fc = Fa * Fb; }}, FloatMULT);
2113 0x23: divt({{ Fc = Fa / Fb; }}, FloatDIV);
2117 // Floating-point compare instructions must have the default
2118 // rounding mode, and may use the default trapping mode or
2119 // /SU. Both trapping modes are treated the same by M5; the
2120 // only difference on the real hardware (as far a I can tell)
2121 // is that without /SU you'd get an imprecise trap if you
2122 // tried to compare a NaN with something else (instead of an
2123 // "unordered" result).
2124 1: decode FP_FULLFUNC {
2125 format BasicOperateWithNopCheck {
2126 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2128 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2130 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2132 0x0a4, 0x5a4: cmptun({{ // unordered
2133 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2138 // The FP-to-integer and integer-to-FP conversion insts
2139 // require that FA be 31.
2141 31: decode FP_TYPEFUNC {
2142 format FloatingPointOperate {
2143 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2145 // The cvtts opcode is overloaded to be cvtst if the trap
2146 // mode is 2 or 6 (which are not valid otherwise)
2147 0x2c: decode FP_FULLFUNC {
2148 format BasicOperateWithNopCheck {
2149 // trap on denorm version "cvtst/s" is
2150 // simulated same as cvtst
2151 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2153 default: cvtts({{ Fc.sf = Fb; }});
2156 // The trapping mode for integer-to-FP conversions
2157 // must be /SUI or nothing; /U and /SU are not
2158 // allowed. The full set of rounding modes are
2159 // supported though.
2160 0x3c: decode FP_TRAPMODE {
2161 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2163 0x3e: decode FP_TRAPMODE {
2164 0,7: cvtqt({{ Fc = Fb.sq; }});
2172 0x17: decode FP_FULLFUNC {
2173 format BasicOperateWithNopCheck {
2175 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2178 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2181 // We treat the precise & imprecise trapping versions of
2182 // cvtql identically.
2183 0x130, 0x530: cvtqlv({{
2184 // To avoid overflow, all the upper 32 bits must match
2185 // the sign bit of the lower 32. We code this as
2186 // checking the upper 33 bits for all 0s or all 1s.
2187 uint64_t sign_bits = Fb.uq<63:31>;
2188 if (sign_bits != 0 && sign_bits != mask(33))
2189 fault = Integer_Overflow_Fault;
2190 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2193 0x020: cpys({{ // copy sign
2194 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2196 0x021: cpysn({{ // copy sign negated
2197 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2199 0x022: cpyse({{ // copy sign and exponent
2200 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2203 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2204 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2205 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2206 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2207 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2208 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2210 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2211 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2215 // miscellaneous mem-format ops
2216 0x18: decode MEMFUNC {
2223 format MiscPrefetch {
2224 0xf800: wh64({{ EA = Rb; }},
2225 {{ xc->writeHint(EA, 64); }},
2226 IsMemRef, IsStore, WrPort);
2229 format BasicOperate {
2232 Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
2238 // All of the barrier instructions below do nothing in
2239 // their execute() methods (hence the empty code blocks).
2240 // All of their functionality is hard-coded in the
2241 // pipeline based on the flags IsSerializing,
2242 // IsMemBarrier, and IsWriteBarrier. In the current
2243 // detailed CPU model, the execute() function only gets
2244 // called at fetch, so there's no way to generate pipeline
2245 // behavior at any other stage. Once we go to an
2246 // exec-in-exec CPU model we should be able to get rid of
2247 // these flags and implement this behavior via the
2248 // execute() methods.
2250 // trapb is just a barrier on integer traps, where excb is
2251 // a barrier on integer and FP traps. "EXCB is thus a
2252 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
2253 // them the same though.
2254 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
2255 0x0400: excb({{ }}, IsSerializing, No_OpClass);
2256 0x4000: mb({{ }}, IsMemBarrier, RdPort);
2257 0x4400: wmb({{ }}, IsWriteBarrier, WrPort);
2261 format BasicOperate {
2263 Ra = xc->readIntrFlag();
2264 if (!xc->misspeculating()) {
2269 Ra = xc->readIntrFlag();
2270 if (!xc->misspeculating()) {
2284 0x00: CallPal::call_pal({{
2287 && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
2288 // invalid pal function code, or attempt to do privileged
2289 // PAL call in non-kernel mode
2290 fault = Unimplemented_Opcode_Fault;
2295 if (!xc->misspeculating()) {
2296 // check to see if simulator wants to do something special
2297 // on this PAL call (including maybe suppress it)
2298 dopal = xc->simPalCheck(palFunc);
2300 Annotate::Callpal(xc->xcBase(), palFunc);
2303 AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
2304 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2308 // if we're misspeculating, it's still safe (if
2309 // unrealistic) to set NPC, as the control-flow change
2310 // won't get committed.
2312 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2317 0x00: decode PALFUNC {
2318 format EmulatedCallPal {
2320 if (!xc->misspeculating())
2321 SimExit(curTick, "halt instruction encountered");
2324 if (!xc->misspeculating())
2327 // Read uniq reg into ABI return value register (r0)
2328 0x9e: rduniq({{ R0 = Runiq; }});
2329 // Write uniq reg with value from ABI arg register (r16)
2330 0x9f: wruniq({{ Runiq = R16; }});
2336 format HwLoadStore {
2337 0x1b: decode HW_LDST_QUAD {
2338 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2339 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2342 0x1f: decode HW_LDST_COND {
2343 0: decode HW_LDST_QUAD {
2344 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2345 {{ Mem.ul = Ra<31:0>; }}, L);
2346 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2347 {{ Mem.uq = Ra.uq; }}, Q);
2350 1: FailUnimpl::hw_st_cond();
2354 format BasicOperate {
2355 0x1e: hw_rei({{ xc->hwrei(); }});
2357 // M5 special opcodes use the reserved 0x01 opcode space
2358 0x01: decode M5FUNC {
2360 if (!xc->misspeculating()) {
2361 Annotate::ARM(xc->xcBase());
2362 xc->xcBase()->kernelStats.arm();
2366 if (!xc->misspeculating())
2367 AlphaPseudo::quiesce(xc->xcBase());
2370 if (!xc->misspeculating()) {
2371 Annotate::BeginInterval(xc->xcBase());
2372 xc->xcBase()->kernelStats.ivlb();
2376 if (!xc->misspeculating())
2377 Annotate::EndInterval(xc->xcBase());
2380 if (!xc->misspeculating())
2381 AlphaPseudo::m5exit_old(xc->xcBase());
2384 if (!xc->misspeculating())
2385 AlphaPseudo::m5exit(xc->xcBase());
2387 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
2389 if (!xc->misspeculating())
2390 AlphaPseudo::resetstats(xc->xcBase());
2393 if (!xc->misspeculating())
2394 AlphaPseudo::dumpstats(xc->xcBase());
2396 0x42: dumpresetstats({{
2397 if (!xc->misspeculating())
2398 AlphaPseudo::dumpresetstats(xc->xcBase());
2400 0x43: m5checkpoint({{
2401 if (!xc->misspeculating())
2402 AlphaPseudo::m5checkpoint(xc->xcBase());
2409 // this instruction is only valid in PAL mode
2410 if (!xc->inPalMode()) {
2411 fault = Unimplemented_Opcode_Fault;
2414 Ra = xc->readIpr(ipr_index, fault);
2418 // this instruction is only valid in PAL mode
2419 if (!xc->inPalMode()) {
2420 fault = Unimplemented_Opcode_Fault;
2423 xc->setIpr(ipr_index, Ra);
2424 if (traceData) { traceData->setData(Ra); }