3 ////////////////////////////////////////////////////////////////////
5 // Alpha ISA description file.
7 ////////////////////////////////////////////////////////////////////
10 ////////////////////////////////////////////////////////////////////
12 // Output include file directives.
20 #include "cpu/static_inst.hh"
21 #include "mem/mem_req.hh" // some constructors use MemReq flags
25 #include "base/cprintf.hh"
26 #include "base/loader/symtab.hh"
27 #include "cpu/exec_context.hh" // for Jump::branchTarget()
41 #include "cpu/base_cpu.hh"
42 #include "cpu/exetrace.hh"
43 #include "sim/sim_exit.hh"
46 #include "arch/alpha/ev5.hh"
47 #include "arch/alpha/pseudo_inst.hh"
51 ////////////////////////////////////////////////////////////////////
53 // Namespace statement. Everything below this line will be in the
54 // AlphaISAInst namespace.
60 ////////////////////////////////////////////////////////////////////
62 // Bitfield definitions.
65 // Universal (format-independent) fields
66 def bitfield OPCODE <31:26>;
67 def bitfield RA <25:21>;
68 def bitfield RB <20:16>;
71 def signed bitfield MEMDISP <15: 0>; // displacement
72 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
74 // Memory-format jumps
75 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
76 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
79 def signed bitfield BRDISP <20: 0>; // displacement
81 // Integer operate format(s>;
82 def bitfield INTIMM <20:13>; // integer immediate (literal)
83 def bitfield IMM <12:12>; // immediate flag
84 def bitfield INTFUNC <11: 5>; // function code
85 def bitfield RC < 4: 0>; // dest reg
87 // Floating-point operate format
88 def bitfield FA <25:21>;
89 def bitfield FB <20:16>;
90 def bitfield FP_FULLFUNC <15: 5>; // complete function code
91 def bitfield FP_TRAPMODE <15:13>; // trapping mode
92 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
93 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
94 def bitfield FP_SRCTYPE <10: 9>; // source reg type
95 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
96 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
97 def bitfield FC < 4: 0>; // dest reg
100 def bitfield PALFUNC <25: 0>; // function code
102 // EV5 PAL instructions:
104 def bitfield HW_LDST_PHYS <15>; // address is physical
105 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
106 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
107 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
108 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
109 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
110 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
111 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
114 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
115 def bitfield HW_REI_MBZ <13: 0>; // must be zero
118 def bitfield HW_IPR_IDX <15:0>; // IPR index
121 def bitfield M5FUNC <7:0>;
124 'sb' : ('signed int', 8),
125 'ub' : ('unsigned int', 8),
126 'sw' : ('signed int', 16),
127 'uw' : ('unsigned int', 16),
128 'sl' : ('signed int', 32),
129 'ul' : ('unsigned int', 32),
130 'sq' : ('signed int', 64),
131 'uq' : ('unsigned int', 64),
132 'sf' : ('float', 32),
137 # Int regs default to unsigned, but code should not count on this.
138 # For clarity, descriptions that depend on unsigned behavior should
139 # explicitly specify '.uq'.
140 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
141 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
142 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
143 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
144 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
145 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
146 'Mem': MemOperandTraits('uq', None,
147 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
148 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
149 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
150 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
151 # The next two are hacks for non-full-system call-pal emulation
152 'R0': IntRegOperandTraits('uq', '0', None, 1),
153 'R16': IntRegOperandTraits('uq', '16', None, 1)
156 ////////////////////////////////////////////////////////////////////
158 // Basic instruction classes/templates/formats etc.
162 // uncomment the following to get SimpleScalar-compatible disassembly
163 // (useful for diffing output traces).
164 // #define SS_COMPATIBLE_DISASSEMBLY
167 * Base class for all Alpha static instructions.
169 class AlphaStaticInst : public StaticInst<AlphaISA>
173 /// Make AlphaISA register dependence tags directly visible in
174 /// this class and derived classes. Maybe these should really
175 /// live here and not in the AlphaISA namespace.
176 enum DependenceTags {
177 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
178 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
179 Uniq_DepTag = AlphaISA::Uniq_DepTag,
180 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
184 AlphaStaticInst(const char *mnem, MachInst _machInst,
186 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
190 /// Print a register name for disassembly given the unique
191 /// dependence tag number (FP or int).
192 void printReg(std::ostream &os, int reg);
194 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
200 AlphaStaticInst::printReg(std::ostream &os, int reg)
202 if (reg < FP_Base_DepTag) {
203 ccprintf(os, "r%d", reg);
206 ccprintf(os, "f%d", reg - FP_Base_DepTag);
211 AlphaStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab)
213 std::stringstream ss;
215 ccprintf(ss, "%-10s ", mnemonic);
217 // just print the first two source regs... if there's
218 // a third one, it's a read-modify-write dest (Rc),
220 if (_numSrcRegs > 0) {
221 printReg(ss, _srcRegIdx[0]);
223 if (_numSrcRegs > 1) {
225 printReg(ss, _srcRegIdx[1]);
228 // just print the first dest... if there's a second one,
229 // it's generally implicit
230 if (_numDestRegs > 0) {
233 printReg(ss, _destRegIdx[0]);
240 // Declarations for execute() methods.
241 def template BasicExecDeclare {{
242 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *);
245 // Basic instruction class declaration template.
246 def template BasicDeclare {{
248 * Static instruction class for "%(mnemonic)s".
250 class %(class_name)s : public %(base_class)s
254 %(class_name)s(MachInst machInst);
260 // Basic instruction class constructor template.
261 def template BasicConstructor {{
262 inline %(class_name)s::%(class_name)s(MachInst machInst)
263 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
269 // Basic instruction class execute method template.
270 def template BasicExecute {{
271 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
272 Trace::InstRecord *traceData)
274 Fault fault = No_Fault;
281 if (fault == No_Fault) {
289 // Basic decode template.
290 def template BasicDecode {{
291 return new %(class_name)s(machInst);
294 // Basic decode template, passing mnemonic in as string arg to constructor.
295 def template BasicDecodeWithMnemonic {{
296 return new %(class_name)s("%(mnemonic)s", machInst);
299 // The most basic instruction format... used only for a few misc. insts
300 def format BasicOperate(code, *flags) {{
301 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
302 header_output = BasicDeclare.subst(iop)
303 decoder_output = BasicConstructor.subst(iop)
304 decode_block = BasicDecode.subst(iop)
305 exec_output = BasicExecute.subst(iop)
310 ////////////////////////////////////////////////////////////////////
317 * Static instruction class for no-ops. This is a leaf class.
319 class Nop : public AlphaStaticInst
321 /// Disassembly of original instruction.
322 const std::string originalDisassembly;
326 Nop(const std::string _originalDisassembly, MachInst _machInst)
327 : AlphaStaticInst("nop", _machInst, No_OpClass),
328 originalDisassembly(_originalDisassembly)
335 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
342 std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab)
344 #ifdef SS_COMPATIBLE_DISASSEMBLY
345 return originalDisassembly;
347 return csprintf("%-10s (%s)", "nop", originalDisassembly);
351 /// Helper function for decoding nops. Substitute Nop object
352 /// for original inst passed in as arg (and delete latter).
355 makeNop(AlphaStaticInst *inst)
357 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
365 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
371 // integer & FP operate instructions use Rc as dest, so check for
372 // Rc == 31 to detect nops
373 def template OperateNopCheckDecode {{
375 AlphaStaticInst *i = new %(class_name)s(machInst);
383 // Like BasicOperate format, but generates NOP if RC/FC == 31
384 def format BasicOperateWithNopCheck(code, *opt_args) {{
385 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
387 header_output = BasicDeclare.subst(iop)
388 decoder_output = BasicConstructor.subst(iop)
389 decode_block = OperateNopCheckDecode.subst(iop)
390 exec_output = BasicExecute.subst(iop)
394 ////////////////////////////////////////////////////////////////////
396 // Integer operate instructions
401 * Base class for integer immediate instructions.
403 class IntegerImm : public AlphaStaticInst
406 /// Immediate operand value (unsigned 8-bit int).
410 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
411 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
415 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
421 IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab)
423 std::stringstream ss;
425 ccprintf(ss, "%-10s ", mnemonic);
427 // just print the first source reg... if there's
428 // a second one, it's a read-modify-write dest (Rc),
430 if (_numSrcRegs > 0) {
431 printReg(ss, _srcRegIdx[0]);
437 if (_numDestRegs > 0) {
439 printReg(ss, _destRegIdx[0]);
447 def template RegOrImmDecode {{
450 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
451 : (AlphaStaticInst *)new %(class_name)s(machInst);
459 // Primary format for integer operate instructions:
460 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
461 // - Generates NOP if RC == 31.
462 def format IntegerOperate(code, *opt_flags) {{
463 # If the code block contains 'Rb_or_imm', we define two instructions,
464 # one using 'Rb' and one using 'imm', and have the decoder select
466 uses_imm = (code.find('Rb_or_imm') != -1)
469 # base code is reg version:
470 # rewrite by substituting 'Rb' for 'Rb_or_imm'
471 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
472 # generate immediate version by substituting 'imm'
473 # note that imm takes no extenstion, so we extend
474 # the regexp to replace any extension as well
475 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
477 # generate declaration for register version
478 cblk = CodeBlock(code)
479 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
480 header_output = BasicDeclare.subst(iop)
481 decoder_output = BasicConstructor.subst(iop)
482 exec_output = BasicExecute.subst(iop)
485 # append declaration for imm version
486 imm_cblk = CodeBlock(imm_code)
487 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
489 header_output += BasicDeclare.subst(imm_iop)
490 decoder_output += BasicConstructor.subst(imm_iop)
491 exec_output += BasicExecute.subst(imm_iop)
492 # decode checks IMM bit to pick correct version
493 decode_block = RegOrImmDecode.subst(iop)
495 # no imm version: just check for nop
496 decode_block = OperateNopCheckDecode.subst(iop)
500 ////////////////////////////////////////////////////////////////////
502 // Floating-point instructions
504 // Note that many FP-type instructions which do not support all the
505 // various rounding & trapping modes use the simpler format
506 // BasicOperateWithNopCheck.
510 /// Check "FP enabled" machine status bit. Called when executing any FP
511 /// instruction in full-system mode.
512 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
513 /// if not. Non-full-system mode: always returns No_Fault.
515 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
517 Fault fault = No_Fault; // dummy... this ipr access should not fault
518 if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
524 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
533 * Base class for general floating-point instructions. Includes
534 * support for various Alpha rounding and trapping modes. Only FP
535 * instructions that require this support are derived from this
536 * class; the rest derive directly from AlphaStaticInst.
538 class AlphaFP : public AlphaStaticInst
541 /// Alpha FP rounding modes.
543 Chopped = 0, ///< round toward zero
544 Minus_Infinity = 1, ///< round toward minus infinity
545 Normal = 2, ///< round to nearest (default)
546 Dynamic = 3, ///< use FPCR setting (in instruction)
547 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
550 /// Alpha FP trapping modes.
551 /// For instructions that produce integer results, the
552 /// "Underflow Enable" modes really mean "Overflow Enable", and
553 /// the assembly modifier is V rather than U.
555 /// default: nothing enabled
556 Imprecise = 0, ///< no modifier
557 /// underflow/overflow traps enabled, inexact disabled
558 Underflow_Imprecise = 1, ///< /U or /V
559 Underflow_Precise = 5, ///< /SU or /SV
560 /// underflow/overflow and inexact traps enabled
561 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
566 static const int alphaToC99RoundingMode[];
569 /// Map enum RoundingMode values to disassembly suffixes.
570 static const char *roundingModeSuffix[];
571 /// Map enum TrappingMode values to FP disassembly suffixes.
572 static const char *fpTrappingModeSuffix[];
573 /// Map enum TrappingMode values to integer disassembly suffixes.
574 static const char *intTrappingModeSuffix[];
576 /// This instruction's rounding mode.
577 RoundingMode roundingMode;
578 /// This instruction's trapping mode.
579 TrappingMode trappingMode;
582 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
583 : AlphaStaticInst(mnem, _machInst, __opClass),
584 roundingMode((enum RoundingMode)FP_ROUNDMODE),
585 trappingMode((enum TrappingMode)FP_TRAPMODE)
587 if (trappingMode != Imprecise) {
588 warn("precise FP traps unimplemented\n");
593 int getC99RoundingMode(uint64_t fpcr_val);
596 // This differs from the AlphaStaticInst version only in
597 // printing suffixes for non-default rounding & trapping modes.
598 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
604 def template FloatingPointDecode {{
606 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
607 && FP_ROUNDMODE == AlphaFP::Normal);
609 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
610 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
623 AlphaFP::getC99RoundingMode(uint64_t fpcr_val)
625 if (roundingMode == Dynamic) {
626 return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
629 return alphaToC99RoundingMode[roundingMode];
635 AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab)
637 std::string mnem_str(mnemonic);
639 #ifndef SS_COMPATIBLE_DISASSEMBLY
640 std::string suffix("");
641 suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
642 ? fpTrappingModeSuffix[trappingMode]
643 : intTrappingModeSuffix[trappingMode]);
644 suffix += roundingModeSuffix[roundingMode];
647 mnem_str = csprintf("%s/%s", mnemonic, suffix);
651 std::stringstream ss;
652 ccprintf(ss, "%-10s ", mnem_str.c_str());
654 // just print the first two source regs... if there's
655 // a third one, it's a read-modify-write dest (Rc),
657 if (_numSrcRegs > 0) {
658 printReg(ss, _srcRegIdx[0]);
660 if (_numSrcRegs > 1) {
662 printReg(ss, _srcRegIdx[1]);
665 // just print the first dest... if there's a second one,
666 // it's generally implicit
667 if (_numDestRegs > 0) {
670 printReg(ss, _destRegIdx[0]);
677 const int AlphaFP::alphaToC99RoundingMode[] = {
678 FE_TOWARDZERO, // Chopped
679 FE_DOWNWARD, // Minus_Infinity
680 FE_TONEAREST, // Normal
681 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
685 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
686 // mark invalid trapping modes, but don't fail on them, because
687 // you could decode anything on a misspeculated path
688 const char *AlphaFP::fpTrappingModeSuffix[] =
689 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
690 const char *AlphaFP::intTrappingModeSuffix[] =
691 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
694 // General format for floating-point operate instructions:
695 // - Checks trapping and rounding mode flags. Trapping modes
696 // currently unimplemented (will fail).
697 // - Generates NOP if FC == 31.
698 def format FloatingPointOperate(code, *opt_args) {{
699 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
700 decode_block = FloatingPointDecode.subst(iop)
702 fast_iop = InstObjParams(name, Name + 'Fast', 'AlphaFP',
703 CodeBlock(code), opt_args)
704 header_output = BasicDeclare.subst(fast_iop)
705 decoder_output = BasicConstructor.subst(fast_iop)
706 exec_output = BasicExecute.subst(fast_iop)
708 gen_code_prefix = r'''
710 fesetround(getC99RoundingMode(xc->readFpcr()));
713 gen_code_suffix = r'''
715 fesetround(FE_TONEAREST);
719 gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
720 CodeBlock(gen_code_prefix + code + gen_code_suffix), opt_args)
721 header_output += BasicDeclare.subst(gen_iop)
722 decoder_output += BasicConstructor.subst(gen_iop)
723 exec_output += BasicExecute.subst(gen_iop)
727 ////////////////////////////////////////////////////////////////////
729 // Memory-format instructions: LoadAddress, Load, Store
734 * Base class for general Alpha memory-format instructions.
736 class Memory : public AlphaStaticInst
740 /// Memory request flags. See mem_req_base.hh.
741 unsigned memAccessFlags;
742 /// Pointer to EAComp object.
743 const StaticInstPtr<AlphaISA> eaCompPtr;
744 /// Pointer to MemAcc object.
745 const StaticInstPtr<AlphaISA> memAccPtr;
748 Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
749 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
750 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
751 : AlphaStaticInst(mnem, _machInst, __opClass),
752 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
756 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
760 const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
761 const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
765 * Base class for memory-format instructions using a 32-bit
766 * displacement (i.e. most of them).
768 class MemoryDisp32 : public Memory
771 /// Displacement for EA calculation (signed).
775 MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
776 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
777 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
778 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
786 * Base class for a few miscellaneous memory-format insts
787 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
788 * None of these instructions has a destination register either.
790 class MemoryNoDisp : public Memory
794 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
795 StaticInstPtr<AlphaISA> _eaCompPtr,
796 StaticInstPtr<AlphaISA> _memAccPtr)
797 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
801 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
806 * Base class for "fake" effective-address computation
807 * instructions returnded by eaCompInst().
809 class EACompBase : public AlphaStaticInst
813 EACompBase(MachInst machInst)
814 : AlphaStaticInst("(eacomp)", machInst, IntAluOp)
822 * Base class for "fake" memory-access instructions returnded by
825 class MemAccBase : public AlphaStaticInst
829 MemAccBase(MachInst machInst, OpClass __opClass)
830 : AlphaStaticInst("(memacc)", machInst, __opClass)
842 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab)
844 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
845 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
849 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab)
851 return csprintf("%-10s (r%d)", mnemonic, RB);
857 EACompBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
859 panic("attempt to execute eacomp");
863 MemAccBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
865 panic("attempt to execute memacc");
870 def format LoadAddress(code) {{
871 iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
872 header_output = BasicDeclare.subst(iop)
873 decoder_output = BasicConstructor.subst(iop)
874 decode_block = BasicDecode.subst(iop)
875 exec_output = BasicExecute.subst(iop)
879 def template LoadStoreDeclare {{
881 * Static instruction class for "%(mnemonic)s".
883 class %(class_name)s : public %(base_class)s
888 * "Fake" effective address computation class for "%(mnemonic)s".
890 class EAComp : public EACompBase
894 EAComp(MachInst machInst);
898 * "Fake" memory access instruction class for "%(mnemonic)s".
900 class MemAcc : public MemAccBase
904 MemAcc(MachInst machInst);
910 %(class_name)s(MachInst machInst);
916 def template LoadStoreConstructor {{
917 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
918 : EACompBase(machInst)
923 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
924 : MemAccBase(machInst, %(op_class)s)
926 %(memacc_constructor)s;
929 inline %(class_name)s::%(class_name)s(MachInst machInst)
930 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
931 new EAComp(machInst), new MemAcc(machInst))
937 def template LoadStoreExecute {{
938 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
939 Trace::InstRecord *traceData)
942 Fault fault = No_Fault;
949 if (fault == No_Fault) {
954 if (fault == No_Fault) {
958 if (fault == No_Fault) {
962 if (fault == No_Fault) {
971 def template PrefetchExecute {{
972 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
973 Trace::InstRecord *traceData)
976 Fault fault = No_Fault;
983 if (fault == No_Fault) {
984 xc->prefetch(EA, memAccessFlags);
991 // load instructions use Ra as dest, so check for
992 // Ra == 31 to detect nops
993 def template LoadNopCheckDecode {{
995 AlphaStaticInst *i = new %(class_name)s(machInst);
1004 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1005 def template LoadPrefetchCheckDecode {{
1008 return new %(class_name)s(machInst);
1011 return new %(class_name)sPrefetch(machInst);
1018 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1019 base_class = 'MemoryDisp32', flags = [],
1020 decode_template = BasicDecode,
1021 exec_template = LoadStoreExecute):
1022 # Segregate flags into instruction flags (handled by InstObjParams)
1023 # and memory access flags (handled here).
1025 # Would be nice to autogenerate this list, but oh well.
1026 valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1030 if f in valid_mem_flags:
1033 inst_flags.append(f)
1035 ea_cblk = CodeBlock(ea_code)
1036 memacc_cblk = CodeBlock(memacc_code)
1037 postacc_cblk = CodeBlock(postacc_code)
1039 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1040 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1042 iop.ea_constructor = ea_cblk.constructor
1043 iop.ea_code = ea_cblk.code
1044 iop.memacc_constructor = memacc_cblk.constructor
1045 iop.memacc_code = memacc_cblk.code
1046 iop.postacc_code = postacc_cblk.code
1048 mem_flags = string.join(mem_flags, '|')
1050 iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
1052 # (header_output, decoder_output, decode_block, exec_output)
1053 return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
1054 decode_template.subst(iop), exec_template.subst(iop))
1058 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1059 (header_output, decoder_output, decode_block, exec_output) = \
1060 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1061 decode_template = LoadNopCheckDecode)
1065 // Note that the flags passed in apply only to the prefetch version
1066 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1067 # declare the load instruction object and generate the decode block
1068 (header_output, decoder_output, decode_block, exec_output) = \
1069 LoadStoreBase(name, Name, ea_code, memacc_code,
1070 decode_template = LoadPrefetchCheckDecode)
1072 # Declare the prefetch instruction object.
1074 # convert flags from tuple to list to make them mutable
1075 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
1077 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
1078 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1079 flags = pf_flags, exec_template = PrefetchExecute)
1081 header_output += pf_header_output
1082 decoder_output += pf_decoder_output
1083 exec_output += pf_exec_output
1087 def format Store(ea_code, memacc_code, *flags) {{
1088 (header_output, decoder_output, decode_block, exec_output) = \
1089 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags)
1093 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1094 (header_output, decoder_output, decode_block, exec_output) = \
1095 LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1100 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1101 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1102 (header_output, decoder_output, decode_block, exec_output) = \
1103 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1104 base_class = 'MemoryNoDisp')
1108 ////////////////////////////////////////////////////////////////////
1110 // Control transfer instructions
1116 * Base class for instructions whose disassembly is not purely a
1117 * function of the machine instruction (i.e., it depends on the
1118 * PC). This class overrides the disassemble() method to check
1119 * the PC and symbol table values before re-using a cached
1120 * disassembly string. This is necessary for branches and jumps,
1121 * where the disassembly string includes the target address (which
1122 * may depend on the PC and/or symbol table).
1124 class PCDependentDisassembly : public AlphaStaticInst
1127 /// Cached program counter from last disassembly
1129 /// Cached symbol table pointer from last disassembly
1130 const SymbolTable *cachedSymtab;
1133 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1135 : AlphaStaticInst(mnem, _machInst, __opClass),
1136 cachedPC(0), cachedSymtab(0)
1140 const std::string &disassemble(Addr pc, const SymbolTable *symtab);
1144 * Base class for branches (PC-relative control transfers),
1145 * conditional or unconditional.
1147 class Branch : public PCDependentDisassembly
1150 /// Displacement to target address (signed).
1154 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1155 : PCDependentDisassembly(mnem, _machInst, __opClass),
1160 Addr branchTarget(Addr branchPC) const;
1162 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1166 * Base class for jumps (register-indirect control transfers). In
1167 * the Alpha ISA, these are always unconditional.
1169 class Jump : public PCDependentDisassembly
1173 /// Displacement to target address (signed).
1178 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1179 : PCDependentDisassembly(mnem, _machInst, __opClass),
1184 Addr branchTarget(ExecContext *xc) const;
1186 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1192 Branch::branchTarget(Addr branchPC) const
1194 return branchPC + 4 + disp;
1198 Jump::branchTarget(ExecContext *xc) const
1200 Addr NPC = xc->readPC() + 4;
1201 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
1202 return (Rb & ~3) | (NPC & 1);
1206 PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab)
1208 if (!cachedDisassembly ||
1209 pc != cachedPC || symtab != cachedSymtab)
1211 if (cachedDisassembly)
1212 delete cachedDisassembly;
1215 new std::string(generateDisassembly(pc, symtab));
1217 cachedSymtab = symtab;
1220 return *cachedDisassembly;
1224 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab)
1226 std::stringstream ss;
1228 ccprintf(ss, "%-10s ", mnemonic);
1230 // There's only one register arg (RA), but it could be
1231 // either a source (the condition for conditional
1232 // branches) or a destination (the link reg for
1233 // unconditional branches)
1234 if (_numSrcRegs > 0) {
1235 printReg(ss, _srcRegIdx[0]);
1238 else if (_numDestRegs > 0) {
1239 printReg(ss, _destRegIdx[0]);
1243 #ifdef SS_COMPATIBLE_DISASSEMBLY
1244 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1250 Addr target = pc + 4 + disp;
1253 if (symtab && symtab->findSymbol(target, str))
1256 ccprintf(ss, "0x%x", target);
1262 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab)
1264 std::stringstream ss;
1266 ccprintf(ss, "%-10s ", mnemonic);
1268 #ifdef SS_COMPATIBLE_DISASSEMBLY
1269 if (_numDestRegs == 0) {
1275 if (_numDestRegs > 0) {
1276 printReg(ss, _destRegIdx[0]);
1280 ccprintf(ss, "(r%d)", RB);
1286 def template JumpOrBranchDecode {{
1288 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1289 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1292 def format CondBranch(code) {{
1293 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1294 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1295 ('IsDirectControl', 'IsCondControl'))
1296 header_output = BasicDeclare.subst(iop)
1297 decoder_output = BasicConstructor.subst(iop)
1298 decode_block = BasicDecode.subst(iop)
1299 exec_output = BasicExecute.subst(iop)
1303 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1304 # Declare basic control transfer w/o link (i.e. link reg is R31)
1305 nolink_code = 'NPC = %s;\n' % npc_expr
1306 nolink_iop = InstObjParams(name, Name, base_class,
1307 CodeBlock(nolink_code), flags)
1308 header_output = BasicDeclare.subst(nolink_iop)
1309 decoder_output = BasicConstructor.subst(nolink_iop)
1310 exec_output = BasicExecute.subst(nolink_iop)
1312 # Generate declaration of '*AndLink' version, append to decls
1313 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1314 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1315 CodeBlock(link_code), flags)
1316 header_output += BasicDeclare.subst(link_iop)
1317 decoder_output += BasicConstructor.subst(link_iop)
1318 exec_output += BasicExecute.subst(link_iop)
1320 # need to use link_iop for the decode template since it is expecting
1321 # the shorter version of class_name (w/o "AndLink")
1323 return (header_output, decoder_output,
1324 JumpOrBranchDecode.subst(nolink_iop), exec_output)
1327 def format UncondBranch(*flags) {{
1328 flags += ('IsUncondControl', 'IsDirectControl')
1329 (header_output, decoder_output, decode_block, exec_output) = \
1330 UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1333 def format Jump(*flags) {{
1334 flags += ('IsUncondControl', 'IsIndirectControl')
1335 (header_output, decoder_output, decode_block, exec_output) = \
1336 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1340 ////////////////////////////////////////////////////////////////////
1347 * Base class for emulated call_pal calls (used only in
1348 * non-full-system mode).
1350 class EmulatedCallPal : public AlphaStaticInst
1355 EmulatedCallPal(const char *mnem, MachInst _machInst,
1357 : AlphaStaticInst(mnem, _machInst, __opClass)
1361 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1367 EmulatedCallPal::generateDisassembly(Addr pc, const SymbolTable *symtab)
1369 #ifdef SS_COMPATIBLE_DISASSEMBLY
1370 return csprintf("%s %s", "call_pal", mnemonic);
1372 return csprintf("%-10s %s", "call_pal", mnemonic);
1377 def format EmulatedCallPal(code, *flags) {{
1378 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
1379 header_output = BasicDeclare.subst(iop)
1380 decoder_output = BasicConstructor.subst(iop)
1381 decode_block = BasicDecode.subst(iop)
1382 exec_output = BasicExecute.subst(iop)
1387 * Base class for full-system-mode call_pal instructions.
1388 * Probably could turn this into a leaf class and get rid of the
1391 class CallPalBase : public AlphaStaticInst
1394 int palFunc; ///< Function code part of instruction
1395 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1396 bool palValid; ///< is the function code valid?
1397 bool palPriv; ///< is this call privileged?
1400 CallPalBase(const char *mnem, MachInst _machInst,
1403 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1409 CallPalBase::CallPalBase(const char *mnem, MachInst _machInst,
1411 : AlphaStaticInst(mnem, _machInst, __opClass),
1414 // From the 21164 HRM (paraphrased):
1415 // Bit 7 of the function code (mask 0x80) indicates
1416 // whether the call is privileged (bit 7 == 0) or
1417 // unprivileged (bit 7 == 1). The privileged call table
1418 // starts at 0x2000, the unprivielged call table starts at
1419 // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
1421 const int palPrivMask = 0x80;
1422 const int palOffsetMask = 0x3f;
1424 // Pal call is invalid unless all other bits are 0
1425 palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
1426 palPriv = ((machInst & palPrivMask) == 0);
1427 int shortPalFunc = (machInst & palOffsetMask);
1428 // Add 1 to base to set pal-mode bit
1429 palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
1433 CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab)
1435 return csprintf("%-10s %#x", "call_pal", palFunc);
1439 def format CallPal(code, *flags) {{
1440 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
1441 header_output = BasicDeclare.subst(iop)
1442 decoder_output = BasicConstructor.subst(iop)
1443 decode_block = BasicDecode.subst(iop)
1444 exec_output = BasicExecute.subst(iop)
1447 ////////////////////////////////////////////////////////////////////
1454 * Base class for hw_ld and hw_st.
1456 class HwLoadStore : public Memory
1460 /// Displacement for EA calculation (signed).
1464 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
1465 StaticInstPtr<AlphaISA> _eaCompPtr,
1466 StaticInstPtr<AlphaISA> _memAccPtr);
1468 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1475 HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
1477 StaticInstPtr<AlphaISA> _eaCompPtr,
1478 StaticInstPtr<AlphaISA> _memAccPtr)
1479 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
1483 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1484 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1485 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1486 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1490 HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab)
1492 #ifdef SS_COMPATIBLE_DISASSEMBLY
1493 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1495 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1496 const char *lock_str =
1497 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1499 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1500 mnemonic, RA, disp, RB,
1501 HW_LDST_PHYS ? ",PHYS" : "",
1502 HW_LDST_ALT ? ",ALT" : "",
1503 HW_LDST_QUAD ? ",QUAD" : "",
1504 HW_LDST_VPTE ? ",VPTE" : "",
1510 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1511 (header_output, decoder_output, decode_block, exec_output) = \
1512 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1513 flags = flags, base_class = 'HwLoadStore')
1517 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1518 (header_output, decoder_output, decode_block, exec_output) = \
1519 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1520 postacc_code, flags = flags, base_class = 'HwLoadStore')
1526 * Base class for hw_mfpr and hw_mtpr.
1528 class HwMoveIPR : public AlphaStaticInst
1531 /// Index of internal processor register.
1535 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1536 : AlphaStaticInst(mnem, _machInst, __opClass),
1537 ipr_index(HW_IPR_IDX)
1541 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1547 HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab)
1549 if (_numSrcRegs > 0) {
1551 return csprintf("%-10s r%d,IPR(%#x)",
1552 mnemonic, RA, ipr_index);
1556 return csprintf("%-10s IPR(%#x),r%d",
1557 mnemonic, ipr_index, RA);
1562 def format HwMoveIPR(code) {{
1563 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1564 header_output = BasicDeclare.subst(iop)
1565 decoder_output = BasicConstructor.subst(iop)
1566 decode_block = BasicDecode.subst(iop)
1567 exec_output = BasicExecute.subst(iop)
1571 ////////////////////////////////////////////////////////////////////
1573 // Unimplemented instructions
1578 * Static instruction class for unimplemented instructions that
1579 * cause simulator termination. Note that these are recognized
1580 * (legal) instructions that the simulator does not support; the
1581 * 'Unknown' class is used for unrecognized/illegal instructions.
1582 * This is a leaf class.
1584 class FailUnimplemented : public AlphaStaticInst
1588 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1589 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1591 // don't call execute() (which panics) if we're on a
1593 flags[IsNonSpeculative] = true;
1596 %(BasicExecDeclare)s
1598 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1602 * Base class for unimplemented instructions that cause a warning
1603 * to be printed (but do not terminate simulation). This
1604 * implementation is a little screwy in that it will print a
1605 * warning for each instance of a particular unimplemented machine
1606 * instruction, not just for each unimplemented opcode. Should
1607 * probably make the 'warned' flag a static member of the derived
1610 class WarnUnimplemented : public AlphaStaticInst
1613 /// Have we warned on this instruction yet?
1618 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1619 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1621 // don't call execute() (which panics) if we're on a
1623 flags[IsNonSpeculative] = true;
1626 %(BasicExecDeclare)s
1628 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1634 FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
1636 return csprintf("%-10s (unimplemented)", mnemonic);
1640 WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
1642 #ifdef SS_COMPATIBLE_DISASSEMBLY
1643 return csprintf("%-10s", mnemonic);
1645 return csprintf("%-10s (unimplemented)", mnemonic);
1652 FailUnimplemented::execute(%(CPU_exec_context)s *xc,
1653 Trace::InstRecord *traceData)
1655 panic("attempt to execute unimplemented instruction '%s' "
1656 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1657 return Unimplemented_Opcode_Fault;
1661 WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
1662 Trace::InstRecord *traceData)
1665 warn("instruction '%s' unimplemented\n", mnemonic);
1674 def format FailUnimpl() {{
1675 iop = InstObjParams(name, 'FailUnimplemented')
1676 decode_block = BasicDecodeWithMnemonic.subst(iop)
1679 def format WarnUnimpl() {{
1680 iop = InstObjParams(name, 'WarnUnimplemented')
1681 decode_block = BasicDecodeWithMnemonic.subst(iop)
1686 * Static instruction class for unknown (illegal) instructions.
1687 * These cause simulator termination if they are executed in a
1688 * non-speculative mode. This is a leaf class.
1690 class Unknown : public AlphaStaticInst
1694 Unknown(MachInst _machInst)
1695 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1697 // don't call execute() (which panics) if we're on a
1699 flags[IsNonSpeculative] = true;
1702 %(BasicExecDeclare)s
1704 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1708 ////////////////////////////////////////////////////////////////////
1710 // Unknown instructions
1715 Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab)
1717 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1718 "unknown", machInst, OPCODE);
1724 Unknown::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData)
1726 panic("attempt to execute unknown instruction "
1727 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1728 return Unimplemented_Opcode_Fault;
1732 def format Unknown() {{
1733 decode_block = 'return new Unknown(machInst);\n'
1736 ////////////////////////////////////////////////////////////////////
1738 // Utility functions for execute methods
1743 /// Return opa + opb, summing carry into third arg.
1745 addc(uint64_t opa, uint64_t opb, int &carry)
1747 uint64_t res = opa + opb;
1748 if (res < opa || res < opb)
1753 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1754 /// product in res_hi and res_lo.
1756 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1758 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1759 uint64_t opa_hi = opa<63:32>;
1760 uint64_t opa_lo = opa<31:0>;
1761 uint64_t opb_hi = opb<63:32>;
1762 uint64_t opb_lo = opb<31:0>;
1764 res_lo = opa_lo * opb_lo;
1766 // The middle partial products logically belong in bit
1767 // positions 95 to 32. Thus the lower 32 bits of each product
1768 // sum into the upper 32 bits of the low result, while the
1769 // upper 32 sum into the low 32 bits of the upper result.
1770 uint64_t partial1 = opa_hi * opb_lo;
1771 uint64_t partial2 = opa_lo * opb_hi;
1773 uint64_t partial1_lo = partial1<31:0> << 32;
1774 uint64_t partial1_hi = partial1<63:32>;
1775 uint64_t partial2_lo = partial2<31:0> << 32;
1776 uint64_t partial2_hi = partial2<63:32>;
1778 // Add partial1_lo and partial2_lo to res_lo, keeping track
1779 // of any carries out
1781 res_lo = addc(partial1_lo, res_lo, carry_out);
1782 res_lo = addc(partial2_lo, res_lo, carry_out);
1784 // Now calculate the high 64 bits...
1785 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1788 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1789 /// See Table 2-2 of Alpha AHB.
1793 int hibit = old_exp<7:>;
1794 int lobits = old_exp<6:0>;
1797 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1800 return (lobits == 0) ? 0 : (0x380 | lobits);
1804 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1805 /// representation to be stored in an FP reg.
1807 s_to_t(uint32_t s_val)
1809 uint64_t tmp = s_val;
1810 return (tmp<31:> << 63 // sign bit
1811 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1812 | tmp<22:0> << 29); // fraction
1815 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1816 /// S-floating representation to be stored in memory.
1818 t_to_s(uint64_t t_val)
1820 return (t_val<63:62> << 30 // sign bit & hi exp bit
1821 | t_val<58:29>); // rest of exp & fraction
1825 ////////////////////////////////////////////////////////////////////
1827 // The actual decoder specification
1830 decode OPCODE default Unknown::unknown() {
1832 format LoadAddress {
1833 0x08: lda({{ Ra = Rb + disp; }});
1834 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1838 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1839 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1840 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1841 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1842 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1843 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1844 0x20: copy_load({{EA = Ra;}},
1845 {{fault = xc->copySrcTranslate(EA);}},
1846 IsMemRef, IsLoad, IsCopy);
1849 format LoadOrPrefetch {
1850 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1851 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1852 // IsFloating flag on lds gets the prefetch to disassemble
1853 // using f31 instead of r31... funcitonally it's unnecessary
1854 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1855 PF_EXCLUSIVE, IsFloating);
1859 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1860 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1861 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1862 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1863 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1864 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1865 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1866 0x24: copy_store({{EA = Rb;}},
1867 {{fault = xc->copy(EA);}},
1868 IsMemRef, IsStore, IsCopy);
1872 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1874 uint64_t tmp = Mem_write_result;
1876 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1878 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1880 uint64_t tmp = Mem_write_result;
1881 // If the write operation returns 0 or 1, then
1882 // this was a conventional store conditional,
1883 // and the value indicates the success/failure
1884 // of the operation. If another value is
1885 // returned, then this was a Turbolaser
1886 // mailbox access, and we don't update the
1887 // result register at all.
1888 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1892 format IntegerOperate {
1894 0x10: decode INTFUNC { // integer arithmetic operations
1896 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1898 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1899 // signed overflow occurs when operands have same sign
1900 // and sign of result does not match.
1901 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1902 fault = Integer_Overflow_Fault;
1905 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1906 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1908 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1910 uint64_t tmp = Ra + Rb_or_imm;
1911 // signed overflow occurs when operands have same sign
1912 // and sign of result does not match.
1913 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1914 fault = Integer_Overflow_Fault;
1917 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1918 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1920 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1922 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1923 // signed overflow detection is same as for add,
1924 // except we need to look at the *complemented*
1925 // sign bit of the subtrahend (Rb), i.e., if the initial
1926 // signs are the *same* then no overflow can occur
1927 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1928 fault = Integer_Overflow_Fault;
1931 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1932 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1934 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1936 uint64_t tmp = Ra - Rb_or_imm;
1937 // signed overflow detection is same as for add,
1938 // except we need to look at the *complemented*
1939 // sign bit of the subtrahend (Rb), i.e., if the initial
1940 // signs are the *same* then no overflow can occur
1941 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1942 fault = Integer_Overflow_Fault;
1945 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1946 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1948 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1949 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1950 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1951 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1952 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1958 for (int i = 0; i < 8; ++i) {
1959 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1967 0x11: decode INTFUNC { // integer logical operations
1969 0x00: and({{ Rc = Ra & Rb_or_imm; }});
1970 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1971 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1972 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1973 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1974 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1976 // conditional moves
1977 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1978 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1979 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1980 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1981 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
1982 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1983 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1984 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
1986 // For AMASK, RA must be R31.
1988 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1991 // For IMPLVER, RA must be R31 and the B operand
1992 // must be the immediate value 1.
1996 // return EV5 for FULL_SYSTEM and EV6 otherwise
2009 // The mysterious 11.25...
2010 0x25: WarnUnimpl::eleven25();
2014 0x12: decode INTFUNC {
2015 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2016 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2017 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2019 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2020 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2021 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2022 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2025 int bv = Rb_or_imm<2:0>;
2026 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2029 int bv = Rb_or_imm<2:0>;
2030 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2033 int bv = Rb_or_imm<2:0>;
2034 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2037 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2038 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2039 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2040 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2043 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2045 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2047 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2049 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2050 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2051 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2052 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
2055 int bv = Rb_or_imm<2:0>;
2056 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2059 int bv = Rb_or_imm<2:0>;
2060 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2063 int bv = Rb_or_imm<2:0>;
2064 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
2068 uint64_t zapmask = 0;
2069 for (int i = 0; i < 8; ++i) {
2071 zapmask |= (mask(8) << (i * 8));
2076 uint64_t zapmask = 0;
2077 for (int i = 0; i < 8; ++i) {
2079 zapmask |= (mask(8) << (i * 8));
2085 0x13: decode INTFUNC { // integer multiplies
2086 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2087 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
2090 mul128(Ra, Rb_or_imm, hi, lo);
2094 // 32-bit multiply with trap on overflow
2095 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
2096 int64_t Rbx = Rb_or_imm.sl;
2097 int64_t tmp = Rax * Rbx;
2098 // To avoid overflow, all the upper 32 bits must match
2099 // the sign bit of the lower 32. We code this as
2100 // checking the upper 33 bits for all 0s or all 1s.
2101 uint64_t sign_bits = tmp<63:31>;
2102 if (sign_bits != 0 && sign_bits != mask(33))
2103 fault = Integer_Overflow_Fault;
2107 // 64-bit multiply with trap on overflow
2109 mul128(Ra, Rb_or_imm, hi, lo);
2110 // all the upper 64 bits must match the sign bit of
2112 if (!((hi == 0 && lo<63:> == 0) ||
2113 (hi == mask(64) && lo<63:> == 1)))
2114 fault = Integer_Overflow_Fault;
2119 0x1c: decode INTFUNC {
2120 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2121 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2125 if (temp<63:32>) temp >>= 32; else count += 32;
2126 if (temp<31:16>) temp >>= 16; else count += 16;
2127 if (temp<15:8>) temp >>= 8; else count += 8;
2128 if (temp<7:4>) temp >>= 4; else count += 4;
2129 if (temp<3:2>) temp >>= 2; else count += 2;
2130 if (temp<1:1>) temp >>= 1; else count += 1;
2131 if ((temp<0:0>) != 0x1) count += 1;
2138 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
2139 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
2140 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
2141 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
2142 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
2143 if (!(temp<0:0> & ULL(0x1))) count += 1;
2164 format BasicOperateWithNopCheck {
2166 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
2169 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2176 // Conditional branches.
2178 0x39: beq({{ cond = (Ra == 0); }});
2179 0x3d: bne({{ cond = (Ra != 0); }});
2180 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2181 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2182 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2183 0x3a: blt({{ cond = (Ra.sq < 0); }});
2184 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2185 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2187 0x31: fbeq({{ cond = (Fa == 0); }});
2188 0x35: fbne({{ cond = (Fa != 0); }});
2189 0x36: fbge({{ cond = (Fa >= 0); }});
2190 0x37: fbgt({{ cond = (Fa > 0); }});
2191 0x33: fble({{ cond = (Fa <= 0); }});
2192 0x32: fblt({{ cond = (Fa < 0); }});
2195 // unconditional branches
2196 format UncondBranch {
2201 // indirect branches
2202 0x1a: decode JMPFUNC {
2207 3: jsr_coroutine(IsCall, IsReturn);
2211 // IEEE floating point
2212 0x14: decode FP_SHORTFUNC {
2213 // Integer to FP register moves must have RB == 31
2215 31: decode FP_FULLFUNC {
2216 format BasicOperateWithNopCheck {
2217 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
2218 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
2219 0x014: FailUnimpl::itoff(); // VAX-format conversion
2224 // Square root instructions must have FA == 31
2226 31: decode FP_TYPEFUNC {
2227 format FloatingPointOperate {
2228 #ifdef SS_COMPATIBLE_FP
2231 fault = Arithmetic_Fault;
2237 fault = Arithmetic_Fault;
2238 Fc.sf = sqrt(Fb.sf);
2243 fault = Arithmetic_Fault;
2250 // VAX-format sqrtf and sqrtg are not implemented
2251 0xa: FailUnimpl::sqrtfg();
2254 // IEEE floating point
2255 0x16: decode FP_SHORTFUNC_TOP2 {
2256 // The top two bits of the short function code break this space
2257 // into four groups: binary ops, compares, reserved, and conversions.
2258 // See Table 4-12 of AHB.
2259 // Most of these instructions may have various trapping and
2260 // rounding mode flags set; these are decoded in the
2261 // FloatingPointDecode template used by the
2262 // FloatingPointOperate format.
2264 // add/sub/mul/div: just decode on the short function code
2266 0: decode FP_TYPEFUNC {
2267 format FloatingPointOperate {
2268 #ifdef SS_COMPATIBLE_FP
2269 0x00: adds({{ Fc = Fa + Fb; }});
2270 0x01: subs({{ Fc = Fa - Fb; }});
2271 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
2272 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
2274 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2275 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2276 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
2277 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
2280 0x20: addt({{ Fc = Fa + Fb; }});
2281 0x21: subt({{ Fc = Fa - Fb; }});
2282 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
2283 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
2287 // Floating-point compare instructions must have the default
2288 // rounding mode, and may use the default trapping mode or
2289 // /SU. Both trapping modes are treated the same by M5; the
2290 // only difference on the real hardware (as far a I can tell)
2291 // is that without /SU you'd get an imprecise trap if you
2292 // tried to compare a NaN with something else (instead of an
2293 // "unordered" result).
2294 1: decode FP_FULLFUNC {
2295 format BasicOperateWithNopCheck {
2296 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2298 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2300 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2302 0x0a4, 0x5a4: cmptun({{ // unordered
2303 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2308 // The FP-to-integer and integer-to-FP conversion insts
2309 // require that FA be 31.
2311 31: decode FP_TYPEFUNC {
2312 format FloatingPointOperate {
2313 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2315 // The cvtts opcode is overloaded to be cvtst if the trap
2316 // mode is 2 or 6 (which are not valid otherwise)
2317 0x2c: decode FP_FULLFUNC {
2318 format BasicOperateWithNopCheck {
2319 // trap on denorm version "cvtst/s" is
2320 // simulated same as cvtst
2321 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2323 default: cvtts({{ Fc.sf = Fb; }});
2326 // The trapping mode for integer-to-FP conversions
2327 // must be /SUI or nothing; /U and /SU are not
2328 // allowed. The full set of rounding modes are
2329 // supported though.
2330 0x3c: decode FP_TRAPMODE {
2331 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2333 0x3e: decode FP_TRAPMODE {
2334 0,7: cvtqt({{ Fc = Fb.sq; }});
2342 0x17: decode FP_FULLFUNC {
2343 format BasicOperateWithNopCheck {
2345 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2348 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2351 // We treat the precise & imprecise trapping versions of
2352 // cvtql identically.
2353 0x130, 0x530: cvtqlv({{
2354 // To avoid overflow, all the upper 32 bits must match
2355 // the sign bit of the lower 32. We code this as
2356 // checking the upper 33 bits for all 0s or all 1s.
2357 uint64_t sign_bits = Fb.uq<63:31>;
2358 if (sign_bits != 0 && sign_bits != mask(33))
2359 fault = Integer_Overflow_Fault;
2360 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2363 0x020: cpys({{ // copy sign
2364 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2366 0x021: cpysn({{ // copy sign negated
2367 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2369 0x022: cpyse({{ // copy sign and exponent
2370 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2373 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2374 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2375 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2376 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2377 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2378 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2380 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2381 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2385 // miscellaneous mem-format ops
2386 0x18: decode MEMFUNC {
2393 format MiscPrefetch {
2394 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
2395 {{ xc->writeHint(EA, 64, memAccessFlags); }},
2396 IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
2400 format BasicOperate {
2403 /* Rb is a fake dependency so here is a fun way to get
2404 * the parser to understand that.
2406 Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
2413 // All of the barrier instructions below do nothing in
2414 // their execute() methods (hence the empty code blocks).
2415 // All of their functionality is hard-coded in the
2416 // pipeline based on the flags IsSerializing,
2417 // IsMemBarrier, and IsWriteBarrier. In the current
2418 // detailed CPU model, the execute() function only gets
2419 // called at fetch, so there's no way to generate pipeline
2420 // behavior at any other stage. Once we go to an
2421 // exec-in-exec CPU model we should be able to get rid of
2422 // these flags and implement this behavior via the
2423 // execute() methods.
2425 // trapb is just a barrier on integer traps, where excb is
2426 // a barrier on integer and FP traps. "EXCB is thus a
2427 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
2428 // them the same though.
2429 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
2430 0x0400: excb({{ }}, IsSerializing, No_OpClass);
2431 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
2432 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
2436 format BasicOperate {
2438 Ra = xc->readIntrFlag();
2440 }}, IsNonSpeculative);
2442 Ra = xc->readIntrFlag();
2444 }}, IsNonSpeculative);
2455 0x00: CallPal::call_pal({{
2458 && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
2459 // invalid pal function code, or attempt to do privileged
2460 // PAL call in non-kernel mode
2461 fault = Unimplemented_Opcode_Fault;
2464 // check to see if simulator wants to do something special
2465 // on this PAL call (including maybe suppress it)
2466 bool dopal = xc->simPalCheck(palFunc);
2469 AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
2470 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2471 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2474 }}, IsNonSpeculative);
2476 0x00: decode PALFUNC {
2477 format EmulatedCallPal {
2479 SimExit(curTick, "halt instruction encountered");
2480 }}, IsNonSpeculative);
2483 }}, IsNonSpeculative);
2484 // Read uniq reg into ABI return value register (r0)
2485 0x9e: rduniq({{ R0 = Runiq; }});
2486 // Write uniq reg with value from ABI arg register (r16)
2487 0x9f: wruniq({{ Runiq = R16; }});
2493 format HwLoadStore {
2494 0x1b: decode HW_LDST_QUAD {
2495 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2496 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2499 0x1f: decode HW_LDST_COND {
2500 0: decode HW_LDST_QUAD {
2501 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2502 {{ Mem.ul = Ra<31:0>; }}, L);
2503 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2504 {{ Mem.uq = Ra.uq; }}, Q);
2507 1: FailUnimpl::hw_st_cond();
2511 format BasicOperate {
2512 0x1e: hw_rei({{ xc->hwrei(); }});
2514 // M5 special opcodes use the reserved 0x01 opcode space
2515 0x01: decode M5FUNC {
2517 AlphaPseudo::arm(xc->xcBase());
2518 }}, IsNonSpeculative);
2520 AlphaPseudo::quiesce(xc->xcBase());
2521 }}, IsNonSpeculative);
2523 AlphaPseudo::ivlb(xc->xcBase());
2524 }}, No_OpClass, IsNonSpeculative);
2526 AlphaPseudo::ivle(xc->xcBase());
2527 }}, No_OpClass, IsNonSpeculative);
2529 AlphaPseudo::m5exit_old(xc->xcBase());
2530 }}, No_OpClass, IsNonSpeculative);
2532 AlphaPseudo::m5exit(xc->xcBase());
2533 }}, No_OpClass, IsNonSpeculative);
2534 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
2536 AlphaPseudo::resetstats(xc->xcBase());
2537 }}, IsNonSpeculative);
2539 AlphaPseudo::dumpstats(xc->xcBase());
2540 }}, IsNonSpeculative);
2541 0x42: dumpresetstats({{
2542 AlphaPseudo::dumpresetstats(xc->xcBase());
2543 }}, IsNonSpeculative);
2544 0x43: m5checkpoint({{
2545 AlphaPseudo::m5checkpoint(xc->xcBase());
2546 }}, IsNonSpeculative);
2548 AlphaPseudo::readfile(xc->xcBase());
2549 }}, IsNonSpeculative);
2551 AlphaPseudo::debugbreak(xc->xcBase());
2552 }}, IsNonSpeculative);
2553 0x52: m5switchcpu({{
2554 AlphaPseudo::switchcpu(xc->xcBase());
2555 }}, IsNonSpeculative);
2562 // this instruction is only valid in PAL mode
2563 if (!xc->inPalMode()) {
2564 fault = Unimplemented_Opcode_Fault;
2567 Ra = xc->readIpr(ipr_index, fault);
2571 // this instruction is only valid in PAL mode
2572 if (!xc->inPalMode()) {
2573 fault = Unimplemented_Opcode_Fault;
2576 xc->setIpr(ipr_index, Ra);
2577 if (traceData) { traceData->setData(Ra); }