3 ////////////////////////////////////////////////////////////////////
5 // Alpha ISA description file.
7 ////////////////////////////////////////////////////////////////////
10 ////////////////////////////////////////////////////////////////////
12 // Output include file directives.
20 #include "cpu/static_inst.hh"
21 #include "mem/mem_req.hh" // some constructors use MemReq flags
25 #include "base/cprintf.hh"
26 #include "base/loader/symtab.hh"
27 #include "cpu/exec_context.hh" // for Jump::branchTarget()
42 #include "arch/alpha/pseudo_inst.hh"
44 #include "cpu/base_cpu.hh"
45 #include "cpu/exetrace.hh"
46 #include "sim/sim_exit.hh"
49 ////////////////////////////////////////////////////////////////////
51 // Namespace statement. Everything below this line will be in the
52 // AlphaISAInst namespace.
58 ////////////////////////////////////////////////////////////////////
60 // Bitfield definitions.
63 // Universal (format-independent) fields
64 def bitfield OPCODE <31:26>;
65 def bitfield RA <25:21>;
66 def bitfield RB <20:16>;
69 def signed bitfield MEMDISP <15: 0>; // displacement
70 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
72 // Memory-format jumps
73 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
74 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
77 def signed bitfield BRDISP <20: 0>; // displacement
79 // Integer operate format(s>;
80 def bitfield INTIMM <20:13>; // integer immediate (literal)
81 def bitfield IMM <12:12>; // immediate flag
82 def bitfield INTFUNC <11: 5>; // function code
83 def bitfield RC < 4: 0>; // dest reg
85 // Floating-point operate format
86 def bitfield FA <25:21>;
87 def bitfield FB <20:16>;
88 def bitfield FP_FULLFUNC <15: 5>; // complete function code
89 def bitfield FP_TRAPMODE <15:13>; // trapping mode
90 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
91 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
92 def bitfield FP_SRCTYPE <10: 9>; // source reg type
93 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
94 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
95 def bitfield FC < 4: 0>; // dest reg
98 def bitfield PALFUNC <25: 0>; // function code
100 // EV5 PAL instructions:
102 def bitfield HW_LDST_PHYS <15>; // address is physical
103 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
104 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
105 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
106 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
107 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
108 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
109 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
112 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
113 def bitfield HW_REI_MBZ <13: 0>; // must be zero
116 def bitfield HW_IPR_IDX <15:0>; // IPR index
119 def bitfield M5FUNC <7:0>;
122 'sb' : ('signed int', 8),
123 'ub' : ('unsigned int', 8),
124 'sw' : ('signed int', 16),
125 'uw' : ('unsigned int', 16),
126 'sl' : ('signed int', 32),
127 'ul' : ('unsigned int', 32),
128 'sq' : ('signed int', 64),
129 'uq' : ('unsigned int', 64),
130 'sf' : ('float', 32),
135 # Int regs default to unsigned, but code should not count on this.
136 # For clarity, descriptions that depend on unsigned behavior should
137 # explicitly specify '.uq'.
138 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
139 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
140 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
141 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
142 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
143 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
144 'Mem': MemOperandTraits('uq', None,
145 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
146 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
147 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
148 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
149 # The next two are hacks for non-full-system call-pal emulation
150 'R0': IntRegOperandTraits('uq', '0', None, 1),
151 'R16': IntRegOperandTraits('uq', '16', None, 1)
154 ////////////////////////////////////////////////////////////////////
156 // Basic instruction classes/templates/formats etc.
160 // uncomment the following to get SimpleScalar-compatible disassembly
161 // (useful for diffing output traces).
162 // #define SS_COMPATIBLE_DISASSEMBLY
165 * Base class for all Alpha static instructions.
167 class AlphaStaticInst : public StaticInst<AlphaISA>
171 /// Make AlphaISA register dependence tags directly visible in
172 /// this class and derived classes. Maybe these should really
173 /// live here and not in the AlphaISA namespace.
174 enum DependenceTags {
175 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
176 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
177 Uniq_DepTag = AlphaISA::Uniq_DepTag,
178 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
182 AlphaStaticInst(const char *mnem, MachInst _machInst,
184 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
188 /// Print a register name for disassembly given the unique
189 /// dependence tag number (FP or int).
190 void printReg(std::ostream &os, int reg);
192 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
198 AlphaStaticInst::printReg(std::ostream &os, int reg)
200 if (reg < FP_Base_DepTag) {
201 ccprintf(os, "r%d", reg);
204 ccprintf(os, "f%d", reg - FP_Base_DepTag);
209 AlphaStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab)
211 std::stringstream ss;
213 ccprintf(ss, "%-10s ", mnemonic);
215 // just print the first two source regs... if there's
216 // a third one, it's a read-modify-write dest (Rc),
218 if (_numSrcRegs > 0) {
219 printReg(ss, _srcRegIdx[0]);
221 if (_numSrcRegs > 1) {
223 printReg(ss, _srcRegIdx[1]);
226 // just print the first dest... if there's a second one,
227 // it's generally implicit
228 if (_numDestRegs > 0) {
231 printReg(ss, _destRegIdx[0]);
238 // Declarations for execute() methods.
239 def template BasicExecDeclare {{
240 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *);
243 // Basic instruction class declaration template.
244 def template BasicDeclare {{
246 * Static instruction class for "%(mnemonic)s".
248 class %(class_name)s : public %(base_class)s
252 %(class_name)s(MachInst machInst);
258 // Basic instruction class constructor template.
259 def template BasicConstructor {{
260 inline %(class_name)s::%(class_name)s(MachInst machInst)
261 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
267 // Basic instruction class execute method template.
268 def template BasicExecute {{
269 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
270 Trace::InstRecord *traceData)
272 Fault fault = No_Fault;
279 if (fault == No_Fault) {
287 // Basic decode template.
288 def template BasicDecode {{
289 return new %(class_name)s(machInst);
292 // Basic decode template, passing mnemonic in as string arg to constructor.
293 def template BasicDecodeWithMnemonic {{
294 return new %(class_name)s("%(mnemonic)s", machInst);
297 // The most basic instruction format... used only for a few misc. insts
298 def format BasicOperate(code, *flags) {{
299 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
300 header_output = BasicDeclare.subst(iop)
301 decoder_output = BasicConstructor.subst(iop)
302 decode_block = BasicDecode.subst(iop)
303 exec_output = BasicExecute.subst(iop)
308 ////////////////////////////////////////////////////////////////////
315 * Static instruction class for no-ops. This is a leaf class.
317 class Nop : public AlphaStaticInst
319 /// Disassembly of original instruction.
320 const std::string originalDisassembly;
324 Nop(const std::string _originalDisassembly, MachInst _machInst)
325 : AlphaStaticInst("nop", _machInst, No_OpClass),
326 originalDisassembly(_originalDisassembly)
333 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
340 std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab)
342 #ifdef SS_COMPATIBLE_DISASSEMBLY
343 return originalDisassembly;
345 return csprintf("%-10s (%s)", "nop", originalDisassembly);
349 /// Helper function for decoding nops. Substitute Nop object
350 /// for original inst passed in as arg (and delete latter).
353 makeNop(AlphaStaticInst *inst)
355 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
363 Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
369 // integer & FP operate instructions use Rc as dest, so check for
370 // Rc == 31 to detect nops
371 def template OperateNopCheckDecode {{
373 AlphaStaticInst *i = new %(class_name)s(machInst);
381 // Like BasicOperate format, but generates NOP if RC/FC == 31
382 def format BasicOperateWithNopCheck(code, *opt_args) {{
383 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
385 header_output = BasicDeclare.subst(iop)
386 decoder_output = BasicConstructor.subst(iop)
387 decode_block = OperateNopCheckDecode.subst(iop)
388 exec_output = BasicExecute.subst(iop)
392 ////////////////////////////////////////////////////////////////////
394 // Integer operate instructions
399 * Base class for integer immediate instructions.
401 class IntegerImm : public AlphaStaticInst
404 /// Immediate operand value (unsigned 8-bit int).
408 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
409 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
413 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
419 IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab)
421 std::stringstream ss;
423 ccprintf(ss, "%-10s ", mnemonic);
425 // just print the first source reg... if there's
426 // a second one, it's a read-modify-write dest (Rc),
428 if (_numSrcRegs > 0) {
429 printReg(ss, _srcRegIdx[0]);
435 if (_numDestRegs > 0) {
437 printReg(ss, _destRegIdx[0]);
445 def template RegOrImmDecode {{
448 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
449 : (AlphaStaticInst *)new %(class_name)s(machInst);
457 // Primary format for integer operate instructions:
458 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
459 // - Generates NOP if RC == 31.
460 def format IntegerOperate(code, *opt_flags) {{
461 # If the code block contains 'Rb_or_imm', we define two instructions,
462 # one using 'Rb' and one using 'imm', and have the decoder select
464 uses_imm = (code.find('Rb_or_imm') != -1)
467 # base code is reg version:
468 # rewrite by substituting 'Rb' for 'Rb_or_imm'
469 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
470 # generate immediate version by substituting 'imm'
471 # note that imm takes no extenstion, so we extend
472 # the regexp to replace any extension as well
473 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
475 # generate declaration for register version
476 cblk = CodeBlock(code)
477 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
478 header_output = BasicDeclare.subst(iop)
479 decoder_output = BasicConstructor.subst(iop)
480 exec_output = BasicExecute.subst(iop)
483 # append declaration for imm version
484 imm_cblk = CodeBlock(imm_code)
485 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
487 header_output += BasicDeclare.subst(imm_iop)
488 decoder_output += BasicConstructor.subst(imm_iop)
489 exec_output += BasicExecute.subst(imm_iop)
490 # decode checks IMM bit to pick correct version
491 decode_block = RegOrImmDecode.subst(iop)
493 # no imm version: just check for nop
494 decode_block = OperateNopCheckDecode.subst(iop)
498 ////////////////////////////////////////////////////////////////////
500 // Floating-point instructions
502 // Note that many FP-type instructions which do not support all the
503 // various rounding & trapping modes use the simpler format
504 // BasicOperateWithNopCheck.
508 /// Check "FP enabled" machine status bit. Called when executing any FP
509 /// instruction in full-system mode.
510 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
511 /// if not. Non-full-system mode: always returns No_Fault.
513 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
515 Fault fault = No_Fault; // dummy... this ipr access should not fault
516 if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
522 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
531 * Base class for general floating-point instructions. Includes
532 * support for various Alpha rounding and trapping modes. Only FP
533 * instructions that require this support are derived from this
534 * class; the rest derive directly from AlphaStaticInst.
536 class AlphaFP : public AlphaStaticInst
539 /// Alpha FP rounding modes.
541 Chopped = 0, ///< round toward zero
542 Minus_Infinity = 1, ///< round toward minus infinity
543 Normal = 2, ///< round to nearest (default)
544 Dynamic = 3, ///< use FPCR setting (in instruction)
545 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
548 /// Alpha FP trapping modes.
549 /// For instructions that produce integer results, the
550 /// "Underflow Enable" modes really mean "Overflow Enable", and
551 /// the assembly modifier is V rather than U.
553 /// default: nothing enabled
554 Imprecise = 0, ///< no modifier
555 /// underflow/overflow traps enabled, inexact disabled
556 Underflow_Imprecise = 1, ///< /U or /V
557 Underflow_Precise = 5, ///< /SU or /SV
558 /// underflow/overflow and inexact traps enabled
559 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
564 static const int alphaToC99RoundingMode[];
567 /// Map enum RoundingMode values to disassembly suffixes.
568 static const char *roundingModeSuffix[];
569 /// Map enum TrappingMode values to FP disassembly suffixes.
570 static const char *fpTrappingModeSuffix[];
571 /// Map enum TrappingMode values to integer disassembly suffixes.
572 static const char *intTrappingModeSuffix[];
574 /// This instruction's rounding mode.
575 RoundingMode roundingMode;
576 /// This instruction's trapping mode.
577 TrappingMode trappingMode;
580 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
581 : AlphaStaticInst(mnem, _machInst, __opClass),
582 roundingMode((enum RoundingMode)FP_ROUNDMODE),
583 trappingMode((enum TrappingMode)FP_TRAPMODE)
585 if (trappingMode != Imprecise) {
586 warn("precise FP traps unimplemented\n");
591 int getC99RoundingMode(uint64_t fpcr_val);
594 // This differs from the AlphaStaticInst version only in
595 // printing suffixes for non-default rounding & trapping modes.
596 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
602 def template FloatingPointDecode {{
604 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
605 && FP_ROUNDMODE == AlphaFP::Normal);
607 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
608 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
621 AlphaFP::getC99RoundingMode(uint64_t fpcr_val)
623 if (roundingMode == Dynamic) {
624 return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
627 return alphaToC99RoundingMode[roundingMode];
633 AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab)
635 std::string mnem_str(mnemonic);
637 #ifndef SS_COMPATIBLE_DISASSEMBLY
638 std::string suffix("");
639 suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
640 ? fpTrappingModeSuffix[trappingMode]
641 : intTrappingModeSuffix[trappingMode]);
642 suffix += roundingModeSuffix[roundingMode];
645 mnem_str = csprintf("%s/%s", mnemonic, suffix);
649 std::stringstream ss;
650 ccprintf(ss, "%-10s ", mnem_str.c_str());
652 // just print the first two source regs... if there's
653 // a third one, it's a read-modify-write dest (Rc),
655 if (_numSrcRegs > 0) {
656 printReg(ss, _srcRegIdx[0]);
658 if (_numSrcRegs > 1) {
660 printReg(ss, _srcRegIdx[1]);
663 // just print the first dest... if there's a second one,
664 // it's generally implicit
665 if (_numDestRegs > 0) {
668 printReg(ss, _destRegIdx[0]);
675 const int AlphaFP::alphaToC99RoundingMode[] = {
676 FE_TOWARDZERO, // Chopped
677 FE_DOWNWARD, // Minus_Infinity
678 FE_TONEAREST, // Normal
679 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
683 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
684 // mark invalid trapping modes, but don't fail on them, because
685 // you could decode anything on a misspeculated path
686 const char *AlphaFP::fpTrappingModeSuffix[] =
687 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
688 const char *AlphaFP::intTrappingModeSuffix[] =
689 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
692 // General format for floating-point operate instructions:
693 // - Checks trapping and rounding mode flags. Trapping modes
694 // currently unimplemented (will fail).
695 // - Generates NOP if FC == 31.
696 def format FloatingPointOperate(code, *opt_args) {{
697 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)
698 decode_block = FloatingPointDecode.subst(iop)
700 fast_iop = InstObjParams(name, Name + 'Fast', 'AlphaFP',
701 CodeBlock(code), opt_args)
702 header_output = BasicDeclare.subst(fast_iop)
703 decoder_output = BasicConstructor.subst(fast_iop)
704 exec_output = BasicExecute.subst(fast_iop)
706 gen_code_prefix = r'''
708 fesetround(getC99RoundingMode(xc->readFpcr()));
711 gen_code_suffix = r'''
713 fesetround(FE_TONEAREST);
717 gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
718 CodeBlock(gen_code_prefix + code + gen_code_suffix), opt_args)
719 header_output += BasicDeclare.subst(gen_iop)
720 decoder_output += BasicConstructor.subst(gen_iop)
721 exec_output += BasicExecute.subst(gen_iop)
725 ////////////////////////////////////////////////////////////////////
727 // Memory-format instructions: LoadAddress, Load, Store
732 * Base class for general Alpha memory-format instructions.
734 class Memory : public AlphaStaticInst
738 /// Memory request flags. See mem_req_base.hh.
739 unsigned memAccessFlags;
740 /// Pointer to EAComp object.
741 const StaticInstPtr<AlphaISA> eaCompPtr;
742 /// Pointer to MemAcc object.
743 const StaticInstPtr<AlphaISA> memAccPtr;
746 Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
747 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
748 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
749 : AlphaStaticInst(mnem, _machInst, __opClass),
750 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
754 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
758 const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
759 const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
763 * Base class for memory-format instructions using a 32-bit
764 * displacement (i.e. most of them).
766 class MemoryDisp32 : public Memory
769 /// Displacement for EA calculation (signed).
773 MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
774 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
775 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
776 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
784 * Base class for a few miscellaneous memory-format insts
785 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
786 * None of these instructions has a destination register either.
788 class MemoryNoDisp : public Memory
792 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
793 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
794 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
795 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
799 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
806 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab)
808 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
809 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
813 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab)
815 return csprintf("%-10s (r%d)", mnemonic, RB);
819 def format LoadAddress(code) {{
820 iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
821 header_output = BasicDeclare.subst(iop)
822 decoder_output = BasicConstructor.subst(iop)
823 decode_block = BasicDecode.subst(iop)
824 exec_output = BasicExecute.subst(iop)
828 def template LoadStoreDeclare {{
830 * Static instruction class for "%(mnemonic)s".
832 class %(class_name)s : public %(base_class)s
837 * "Fake" effective address computation class for "%(mnemonic)s".
839 class EAComp : public %(base_class)s
843 EAComp(MachInst machInst);
849 * "Fake" memory access instruction class for "%(mnemonic)s".
851 class MemAcc : public %(base_class)s
855 MemAcc(MachInst machInst);
863 %(class_name)s(MachInst machInst);
869 def template LoadStoreConstructor {{
870 /** TODO: change op_class to AddrGenOp or something (requires
871 * creating new member of OpClass enum in op_class.hh, updating
872 * config files, etc.). */
873 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
874 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
879 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
880 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
882 %(memacc_constructor)s;
885 inline %(class_name)s::%(class_name)s(MachInst machInst)
886 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
887 new EAComp(machInst), new MemAcc(machInst))
894 def template EACompExecute {{
896 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
897 Trace::InstRecord *traceData)
900 Fault fault = No_Fault;
907 if (fault == No_Fault) {
916 def template MemAccExecute {{
918 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
919 Trace::InstRecord *traceData)
922 Fault fault = No_Fault;
929 if (fault == No_Fault) {
934 if (fault == No_Fault) {
938 if (fault == No_Fault) {
942 if (fault == No_Fault) {
951 def template LoadStoreExecute {{
952 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
953 Trace::InstRecord *traceData)
956 Fault fault = No_Fault;
963 if (fault == No_Fault) {
968 if (fault == No_Fault) {
972 if (fault == No_Fault) {
976 if (fault == No_Fault) {
985 def template PrefetchExecute {{
986 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
987 Trace::InstRecord *traceData)
990 Fault fault = No_Fault;
997 if (fault == No_Fault) {
998 xc->prefetch(EA, memAccessFlags);
1005 // load instructions use Ra as dest, so check for
1006 // Ra == 31 to detect nops
1007 def template LoadNopCheckDecode {{
1009 AlphaStaticInst *i = new %(class_name)s(machInst);
1018 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1019 def template LoadPrefetchCheckDecode {{
1022 return new %(class_name)s(machInst);
1025 return new %(class_name)sPrefetch(machInst);
1032 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1033 base_class = 'MemoryDisp32', flags = [],
1034 decode_template = BasicDecode,
1035 exec_template = LoadStoreExecute):
1036 # Segregate flags into instruction flags (handled by InstObjParams)
1037 # and memory access flags (handled here).
1039 # Would be nice to autogenerate this list, but oh well.
1040 valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1041 mem_flags = [f for f in flags if f in valid_mem_flags]
1042 inst_flags = [f for f in flags if f not in valid_mem_flags]
1044 # add hook to get effective addresses into execution trace output.
1045 ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
1047 # generate code block objects
1048 ea_cblk = CodeBlock(ea_code)
1049 memacc_cblk = CodeBlock(memacc_code)
1050 postacc_cblk = CodeBlock(postacc_code)
1052 # Some CPU models execute the memory operation as an atomic unit,
1053 # while others want to separate them into an effective address
1054 # computation and a memory access operation. As a result, we need
1055 # to generate three StaticInst objects. Note that the latter two
1056 # are nested inside the larger "atomic" one.
1058 # generate InstObjParams for EAComp object
1059 ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
1061 # generate InstObjParams for MemAcc object
1062 memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
1063 # in the split execution model, the MemAcc portion is responsible
1064 # for the post-access code.
1065 memacc_iop.postacc_code = postacc_cblk.code
1067 # generate InstObjParams for unified execution
1068 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1069 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1071 iop.ea_constructor = ea_cblk.constructor
1072 iop.ea_code = ea_cblk.code
1073 iop.memacc_constructor = memacc_cblk.constructor
1074 iop.memacc_code = memacc_cblk.code
1075 iop.postacc_code = postacc_cblk.code
1078 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
1079 iop.constructor += s
1080 memacc_iop.constructor += s
1082 # (header_output, decoder_output, decode_block, exec_output)
1083 return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
1084 decode_template.subst(iop),
1085 EACompExecute.subst(ea_iop)
1086 + MemAccExecute.subst(memacc_iop)
1087 + exec_template.subst(iop))
1091 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1092 (header_output, decoder_output, decode_block, exec_output) = \
1093 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1094 decode_template = LoadNopCheckDecode)
1098 // Note that the flags passed in apply only to the prefetch version
1099 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1100 # declare the load instruction object and generate the decode block
1101 (header_output, decoder_output, decode_block, exec_output) = \
1102 LoadStoreBase(name, Name, ea_code, memacc_code,
1103 decode_template = LoadPrefetchCheckDecode)
1105 # Declare the prefetch instruction object.
1107 # convert flags from tuple to list to make them mutable
1108 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
1110 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
1111 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1112 flags = pf_flags, exec_template = PrefetchExecute)
1114 header_output += pf_header_output
1115 decoder_output += pf_decoder_output
1116 exec_output += pf_exec_output
1120 def format Store(ea_code, memacc_code, *flags) {{
1121 (header_output, decoder_output, decode_block, exec_output) = \
1122 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags)
1126 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1127 (header_output, decoder_output, decode_block, exec_output) = \
1128 LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1133 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1134 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1135 (header_output, decoder_output, decode_block, exec_output) = \
1136 LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
1137 base_class = 'MemoryNoDisp')
1141 ////////////////////////////////////////////////////////////////////
1143 // Control transfer instructions
1149 * Base class for instructions whose disassembly is not purely a
1150 * function of the machine instruction (i.e., it depends on the
1151 * PC). This class overrides the disassemble() method to check
1152 * the PC and symbol table values before re-using a cached
1153 * disassembly string. This is necessary for branches and jumps,
1154 * where the disassembly string includes the target address (which
1155 * may depend on the PC and/or symbol table).
1157 class PCDependentDisassembly : public AlphaStaticInst
1160 /// Cached program counter from last disassembly
1162 /// Cached symbol table pointer from last disassembly
1163 const SymbolTable *cachedSymtab;
1166 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1168 : AlphaStaticInst(mnem, _machInst, __opClass),
1169 cachedPC(0), cachedSymtab(0)
1173 const std::string &disassemble(Addr pc, const SymbolTable *symtab);
1177 * Base class for branches (PC-relative control transfers),
1178 * conditional or unconditional.
1180 class Branch : public PCDependentDisassembly
1183 /// Displacement to target address (signed).
1187 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1188 : PCDependentDisassembly(mnem, _machInst, __opClass),
1193 Addr branchTarget(Addr branchPC) const;
1195 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1199 * Base class for jumps (register-indirect control transfers). In
1200 * the Alpha ISA, these are always unconditional.
1202 class Jump : public PCDependentDisassembly
1206 /// Displacement to target address (signed).
1211 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1212 : PCDependentDisassembly(mnem, _machInst, __opClass),
1217 Addr branchTarget(ExecContext *xc) const;
1219 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1225 Branch::branchTarget(Addr branchPC) const
1227 return branchPC + 4 + disp;
1231 Jump::branchTarget(ExecContext *xc) const
1233 Addr NPC = xc->readPC() + 4;
1234 uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
1235 return (Rb & ~3) | (NPC & 1);
1239 PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab)
1241 if (!cachedDisassembly ||
1242 pc != cachedPC || symtab != cachedSymtab)
1244 if (cachedDisassembly)
1245 delete cachedDisassembly;
1248 new std::string(generateDisassembly(pc, symtab));
1250 cachedSymtab = symtab;
1253 return *cachedDisassembly;
1257 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab)
1259 std::stringstream ss;
1261 ccprintf(ss, "%-10s ", mnemonic);
1263 // There's only one register arg (RA), but it could be
1264 // either a source (the condition for conditional
1265 // branches) or a destination (the link reg for
1266 // unconditional branches)
1267 if (_numSrcRegs > 0) {
1268 printReg(ss, _srcRegIdx[0]);
1271 else if (_numDestRegs > 0) {
1272 printReg(ss, _destRegIdx[0]);
1276 #ifdef SS_COMPATIBLE_DISASSEMBLY
1277 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1283 Addr target = pc + 4 + disp;
1286 if (symtab && symtab->findSymbol(target, str))
1289 ccprintf(ss, "0x%x", target);
1295 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab)
1297 std::stringstream ss;
1299 ccprintf(ss, "%-10s ", mnemonic);
1301 #ifdef SS_COMPATIBLE_DISASSEMBLY
1302 if (_numDestRegs == 0) {
1308 if (_numDestRegs > 0) {
1309 printReg(ss, _destRegIdx[0]);
1313 ccprintf(ss, "(r%d)", RB);
1319 def template JumpOrBranchDecode {{
1321 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1322 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1325 def format CondBranch(code) {{
1326 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1327 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1328 ('IsDirectControl', 'IsCondControl'))
1329 header_output = BasicDeclare.subst(iop)
1330 decoder_output = BasicConstructor.subst(iop)
1331 decode_block = BasicDecode.subst(iop)
1332 exec_output = BasicExecute.subst(iop)
1336 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1337 # Declare basic control transfer w/o link (i.e. link reg is R31)
1338 nolink_code = 'NPC = %s;\n' % npc_expr
1339 nolink_iop = InstObjParams(name, Name, base_class,
1340 CodeBlock(nolink_code), flags)
1341 header_output = BasicDeclare.subst(nolink_iop)
1342 decoder_output = BasicConstructor.subst(nolink_iop)
1343 exec_output = BasicExecute.subst(nolink_iop)
1345 # Generate declaration of '*AndLink' version, append to decls
1346 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1347 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1348 CodeBlock(link_code), flags)
1349 header_output += BasicDeclare.subst(link_iop)
1350 decoder_output += BasicConstructor.subst(link_iop)
1351 exec_output += BasicExecute.subst(link_iop)
1353 # need to use link_iop for the decode template since it is expecting
1354 # the shorter version of class_name (w/o "AndLink")
1356 return (header_output, decoder_output,
1357 JumpOrBranchDecode.subst(nolink_iop), exec_output)
1360 def format UncondBranch(*flags) {{
1361 flags += ('IsUncondControl', 'IsDirectControl')
1362 (header_output, decoder_output, decode_block, exec_output) = \
1363 UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1366 def format Jump(*flags) {{
1367 flags += ('IsUncondControl', 'IsIndirectControl')
1368 (header_output, decoder_output, decode_block, exec_output) = \
1369 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1373 ////////////////////////////////////////////////////////////////////
1380 * Base class for emulated call_pal calls (used only in
1381 * non-full-system mode).
1383 class EmulatedCallPal : public AlphaStaticInst
1388 EmulatedCallPal(const char *mnem, MachInst _machInst,
1390 : AlphaStaticInst(mnem, _machInst, __opClass)
1394 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1400 EmulatedCallPal::generateDisassembly(Addr pc, const SymbolTable *symtab)
1402 #ifdef SS_COMPATIBLE_DISASSEMBLY
1403 return csprintf("%s %s", "call_pal", mnemonic);
1405 return csprintf("%-10s %s", "call_pal", mnemonic);
1410 def format EmulatedCallPal(code, *flags) {{
1411 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
1412 header_output = BasicDeclare.subst(iop)
1413 decoder_output = BasicConstructor.subst(iop)
1414 decode_block = BasicDecode.subst(iop)
1415 exec_output = BasicExecute.subst(iop)
1420 * Base class for full-system-mode call_pal instructions.
1421 * Probably could turn this into a leaf class and get rid of the
1424 class CallPalBase : public AlphaStaticInst
1427 int palFunc; ///< Function code part of instruction
1428 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1429 bool palValid; ///< is the function code valid?
1430 bool palPriv; ///< is this call privileged?
1433 CallPalBase(const char *mnem, MachInst _machInst,
1436 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1442 CallPalBase::CallPalBase(const char *mnem, MachInst _machInst,
1444 : AlphaStaticInst(mnem, _machInst, __opClass),
1447 // From the 21164 HRM (paraphrased):
1448 // Bit 7 of the function code (mask 0x80) indicates
1449 // whether the call is privileged (bit 7 == 0) or
1450 // unprivileged (bit 7 == 1). The privileged call table
1451 // starts at 0x2000, the unprivielged call table starts at
1452 // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
1454 const int palPrivMask = 0x80;
1455 const int palOffsetMask = 0x3f;
1457 // Pal call is invalid unless all other bits are 0
1458 palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
1459 palPriv = ((machInst & palPrivMask) == 0);
1460 int shortPalFunc = (machInst & palOffsetMask);
1461 // Add 1 to base to set pal-mode bit
1462 palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
1466 CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab)
1468 return csprintf("%-10s %#x", "call_pal", palFunc);
1472 def format CallPal(code, *flags) {{
1473 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
1474 header_output = BasicDeclare.subst(iop)
1475 decoder_output = BasicConstructor.subst(iop)
1476 decode_block = BasicDecode.subst(iop)
1477 exec_output = BasicExecute.subst(iop)
1480 ////////////////////////////////////////////////////////////////////
1487 * Base class for hw_ld and hw_st.
1489 class HwLoadStore : public Memory
1493 /// Displacement for EA calculation (signed).
1497 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
1498 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
1499 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
1501 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1508 HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
1510 StaticInstPtr<AlphaISA> _eaCompPtr,
1511 StaticInstPtr<AlphaISA> _memAccPtr)
1512 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
1516 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1517 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1518 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1519 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1523 HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab)
1525 #ifdef SS_COMPATIBLE_DISASSEMBLY
1526 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1528 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1529 const char *lock_str =
1530 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1532 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1533 mnemonic, RA, disp, RB,
1534 HW_LDST_PHYS ? ",PHYS" : "",
1535 HW_LDST_ALT ? ",ALT" : "",
1536 HW_LDST_QUAD ? ",QUAD" : "",
1537 HW_LDST_VPTE ? ",VPTE" : "",
1543 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1544 (header_output, decoder_output, decode_block, exec_output) = \
1545 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1546 flags = flags, base_class = 'HwLoadStore')
1550 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1551 (header_output, decoder_output, decode_block, exec_output) = \
1552 LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1553 postacc_code, flags = flags, base_class = 'HwLoadStore')
1559 * Base class for hw_mfpr and hw_mtpr.
1561 class HwMoveIPR : public AlphaStaticInst
1564 /// Index of internal processor register.
1568 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1569 : AlphaStaticInst(mnem, _machInst, __opClass),
1570 ipr_index(HW_IPR_IDX)
1574 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1580 HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab)
1582 if (_numSrcRegs > 0) {
1584 return csprintf("%-10s r%d,IPR(%#x)",
1585 mnemonic, RA, ipr_index);
1589 return csprintf("%-10s IPR(%#x),r%d",
1590 mnemonic, ipr_index, RA);
1595 def format HwMoveIPR(code) {{
1596 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1597 header_output = BasicDeclare.subst(iop)
1598 decoder_output = BasicConstructor.subst(iop)
1599 decode_block = BasicDecode.subst(iop)
1600 exec_output = BasicExecute.subst(iop)
1604 ////////////////////////////////////////////////////////////////////
1606 // Unimplemented instructions
1611 * Static instruction class for unimplemented instructions that
1612 * cause simulator termination. Note that these are recognized
1613 * (legal) instructions that the simulator does not support; the
1614 * 'Unknown' class is used for unrecognized/illegal instructions.
1615 * This is a leaf class.
1617 class FailUnimplemented : public AlphaStaticInst
1621 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1622 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1624 // don't call execute() (which panics) if we're on a
1626 flags[IsNonSpeculative] = true;
1629 %(BasicExecDeclare)s
1631 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1635 * Base class for unimplemented instructions that cause a warning
1636 * to be printed (but do not terminate simulation). This
1637 * implementation is a little screwy in that it will print a
1638 * warning for each instance of a particular unimplemented machine
1639 * instruction, not just for each unimplemented opcode. Should
1640 * probably make the 'warned' flag a static member of the derived
1643 class WarnUnimplemented : public AlphaStaticInst
1646 /// Have we warned on this instruction yet?
1651 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1652 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1654 // don't call execute() (which panics) if we're on a
1656 flags[IsNonSpeculative] = true;
1659 %(BasicExecDeclare)s
1661 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1667 FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
1669 return csprintf("%-10s (unimplemented)", mnemonic);
1673 WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
1675 #ifdef SS_COMPATIBLE_DISASSEMBLY
1676 return csprintf("%-10s", mnemonic);
1678 return csprintf("%-10s (unimplemented)", mnemonic);
1685 FailUnimplemented::execute(%(CPU_exec_context)s *xc,
1686 Trace::InstRecord *traceData)
1688 panic("attempt to execute unimplemented instruction '%s' "
1689 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1690 return Unimplemented_Opcode_Fault;
1694 WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
1695 Trace::InstRecord *traceData)
1698 warn("instruction '%s' unimplemented\n", mnemonic);
1707 def format FailUnimpl() {{
1708 iop = InstObjParams(name, 'FailUnimplemented')
1709 decode_block = BasicDecodeWithMnemonic.subst(iop)
1712 def format WarnUnimpl() {{
1713 iop = InstObjParams(name, 'WarnUnimplemented')
1714 decode_block = BasicDecodeWithMnemonic.subst(iop)
1719 * Static instruction class for unknown (illegal) instructions.
1720 * These cause simulator termination if they are executed in a
1721 * non-speculative mode. This is a leaf class.
1723 class Unknown : public AlphaStaticInst
1727 Unknown(MachInst _machInst)
1728 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1730 // don't call execute() (which panics) if we're on a
1732 flags[IsNonSpeculative] = true;
1735 %(BasicExecDeclare)s
1737 std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
1741 ////////////////////////////////////////////////////////////////////
1743 // Unknown instructions
1748 Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab)
1750 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1751 "unknown", machInst, OPCODE);
1757 Unknown::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData)
1759 panic("attempt to execute unknown instruction "
1760 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1761 return Unimplemented_Opcode_Fault;
1765 def format Unknown() {{
1766 decode_block = 'return new Unknown(machInst);\n'
1769 ////////////////////////////////////////////////////////////////////
1771 // Utility functions for execute methods
1776 /// Return opa + opb, summing carry into third arg.
1778 addc(uint64_t opa, uint64_t opb, int &carry)
1780 uint64_t res = opa + opb;
1781 if (res < opa || res < opb)
1786 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1787 /// product in res_hi and res_lo.
1789 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1791 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1792 uint64_t opa_hi = opa<63:32>;
1793 uint64_t opa_lo = opa<31:0>;
1794 uint64_t opb_hi = opb<63:32>;
1795 uint64_t opb_lo = opb<31:0>;
1797 res_lo = opa_lo * opb_lo;
1799 // The middle partial products logically belong in bit
1800 // positions 95 to 32. Thus the lower 32 bits of each product
1801 // sum into the upper 32 bits of the low result, while the
1802 // upper 32 sum into the low 32 bits of the upper result.
1803 uint64_t partial1 = opa_hi * opb_lo;
1804 uint64_t partial2 = opa_lo * opb_hi;
1806 uint64_t partial1_lo = partial1<31:0> << 32;
1807 uint64_t partial1_hi = partial1<63:32>;
1808 uint64_t partial2_lo = partial2<31:0> << 32;
1809 uint64_t partial2_hi = partial2<63:32>;
1811 // Add partial1_lo and partial2_lo to res_lo, keeping track
1812 // of any carries out
1814 res_lo = addc(partial1_lo, res_lo, carry_out);
1815 res_lo = addc(partial2_lo, res_lo, carry_out);
1817 // Now calculate the high 64 bits...
1818 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1821 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1822 /// See Table 2-2 of Alpha AHB.
1826 int hibit = old_exp<7:>;
1827 int lobits = old_exp<6:0>;
1830 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1833 return (lobits == 0) ? 0 : (0x380 | lobits);
1837 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1838 /// representation to be stored in an FP reg.
1840 s_to_t(uint32_t s_val)
1842 uint64_t tmp = s_val;
1843 return (tmp<31:> << 63 // sign bit
1844 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1845 | tmp<22:0> << 29); // fraction
1848 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1849 /// S-floating representation to be stored in memory.
1851 t_to_s(uint64_t t_val)
1853 return (t_val<63:62> << 30 // sign bit & hi exp bit
1854 | t_val<58:29>); // rest of exp & fraction
1858 ////////////////////////////////////////////////////////////////////
1860 // The actual decoder specification
1863 decode OPCODE default Unknown::unknown() {
1865 format LoadAddress {
1866 0x08: lda({{ Ra = Rb + disp; }});
1867 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1871 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1872 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1873 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1874 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1875 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1876 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1877 0x20: copy_load({{EA = Ra;}},
1878 {{fault = xc->copySrcTranslate(EA);}},
1879 IsMemRef, IsLoad, IsCopy);
1882 format LoadOrPrefetch {
1883 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1884 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1885 // IsFloating flag on lds gets the prefetch to disassemble
1886 // using f31 instead of r31... funcitonally it's unnecessary
1887 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1888 PF_EXCLUSIVE, IsFloating);
1892 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1893 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1894 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1895 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1896 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1897 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1898 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1899 0x24: copy_store({{EA = Rb;}},
1900 {{fault = xc->copy(EA);}},
1901 IsMemRef, IsStore, IsCopy);
1905 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1907 uint64_t tmp = Mem_write_result;
1909 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1911 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1913 uint64_t tmp = Mem_write_result;
1914 // If the write operation returns 0 or 1, then
1915 // this was a conventional store conditional,
1916 // and the value indicates the success/failure
1917 // of the operation. If another value is
1918 // returned, then this was a Turbolaser
1919 // mailbox access, and we don't update the
1920 // result register at all.
1921 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1925 format IntegerOperate {
1927 0x10: decode INTFUNC { // integer arithmetic operations
1929 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1931 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1932 // signed overflow occurs when operands have same sign
1933 // and sign of result does not match.
1934 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1935 fault = Integer_Overflow_Fault;
1938 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1939 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1941 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1943 uint64_t tmp = Ra + Rb_or_imm;
1944 // signed overflow occurs when operands have same sign
1945 // and sign of result does not match.
1946 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1947 fault = Integer_Overflow_Fault;
1950 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1951 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1953 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1955 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1956 // signed overflow detection is same as for add,
1957 // except we need to look at the *complemented*
1958 // sign bit of the subtrahend (Rb), i.e., if the initial
1959 // signs are the *same* then no overflow can occur
1960 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1961 fault = Integer_Overflow_Fault;
1964 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1965 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1967 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1969 uint64_t tmp = Ra - Rb_or_imm;
1970 // signed overflow detection is same as for add,
1971 // except we need to look at the *complemented*
1972 // sign bit of the subtrahend (Rb), i.e., if the initial
1973 // signs are the *same* then no overflow can occur
1974 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1975 fault = Integer_Overflow_Fault;
1978 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1979 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1981 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1982 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1983 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1984 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1985 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1991 for (int i = 0; i < 8; ++i) {
1992 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
2000 0x11: decode INTFUNC { // integer logical operations
2002 0x00: and({{ Rc = Ra & Rb_or_imm; }});
2003 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
2004 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
2005 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
2006 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
2007 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
2009 // conditional moves
2010 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
2011 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
2012 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
2013 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
2014 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
2015 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
2016 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
2017 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
2019 // For AMASK, RA must be R31.
2021 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
2024 // For IMPLVER, RA must be R31 and the B operand
2025 // must be the immediate value 1.
2029 // return EV5 for FULL_SYSTEM and EV6 otherwise
2042 // The mysterious 11.25...
2043 0x25: WarnUnimpl::eleven25();
2047 0x12: decode INTFUNC {
2048 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2049 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2050 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2052 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2053 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2054 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2055 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2058 int bv = Rb_or_imm<2:0>;
2059 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2062 int bv = Rb_or_imm<2:0>;
2063 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2066 int bv = Rb_or_imm<2:0>;
2067 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2070 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2071 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2072 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2073 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2076 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2078 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2080 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2082 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2083 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2084 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2085 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
2088 int bv = Rb_or_imm<2:0>;
2089 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2092 int bv = Rb_or_imm<2:0>;
2093 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2096 int bv = Rb_or_imm<2:0>;
2097 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
2101 uint64_t zapmask = 0;
2102 for (int i = 0; i < 8; ++i) {
2104 zapmask |= (mask(8) << (i * 8));
2109 uint64_t zapmask = 0;
2110 for (int i = 0; i < 8; ++i) {
2112 zapmask |= (mask(8) << (i * 8));
2118 0x13: decode INTFUNC { // integer multiplies
2119 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2120 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
2123 mul128(Ra, Rb_or_imm, hi, lo);
2127 // 32-bit multiply with trap on overflow
2128 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
2129 int64_t Rbx = Rb_or_imm.sl;
2130 int64_t tmp = Rax * Rbx;
2131 // To avoid overflow, all the upper 32 bits must match
2132 // the sign bit of the lower 32. We code this as
2133 // checking the upper 33 bits for all 0s or all 1s.
2134 uint64_t sign_bits = tmp<63:31>;
2135 if (sign_bits != 0 && sign_bits != mask(33))
2136 fault = Integer_Overflow_Fault;
2140 // 64-bit multiply with trap on overflow
2142 mul128(Ra, Rb_or_imm, hi, lo);
2143 // all the upper 64 bits must match the sign bit of
2145 if (!((hi == 0 && lo<63:> == 0) ||
2146 (hi == mask(64) && lo<63:> == 1)))
2147 fault = Integer_Overflow_Fault;
2152 0x1c: decode INTFUNC {
2153 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2154 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2158 if (temp<63:32>) temp >>= 32; else count += 32;
2159 if (temp<31:16>) temp >>= 16; else count += 16;
2160 if (temp<15:8>) temp >>= 8; else count += 8;
2161 if (temp<7:4>) temp >>= 4; else count += 4;
2162 if (temp<3:2>) temp >>= 2; else count += 2;
2163 if (temp<1:1>) temp >>= 1; else count += 1;
2164 if ((temp<0:0>) != 0x1) count += 1;
2171 if (!(temp<31:0>)) { temp >>= 32; count += 32; }
2172 if (!(temp<15:0>)) { temp >>= 16; count += 16; }
2173 if (!(temp<7:0>)) { temp >>= 8; count += 8; }
2174 if (!(temp<3:0>)) { temp >>= 4; count += 4; }
2175 if (!(temp<1:0>)) { temp >>= 2; count += 2; }
2176 if (!(temp<0:0> & ULL(0x1))) count += 1;
2197 format BasicOperateWithNopCheck {
2199 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
2202 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2209 // Conditional branches.
2211 0x39: beq({{ cond = (Ra == 0); }});
2212 0x3d: bne({{ cond = (Ra != 0); }});
2213 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2214 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2215 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2216 0x3a: blt({{ cond = (Ra.sq < 0); }});
2217 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2218 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2220 0x31: fbeq({{ cond = (Fa == 0); }});
2221 0x35: fbne({{ cond = (Fa != 0); }});
2222 0x36: fbge({{ cond = (Fa >= 0); }});
2223 0x37: fbgt({{ cond = (Fa > 0); }});
2224 0x33: fble({{ cond = (Fa <= 0); }});
2225 0x32: fblt({{ cond = (Fa < 0); }});
2228 // unconditional branches
2229 format UncondBranch {
2234 // indirect branches
2235 0x1a: decode JMPFUNC {
2240 3: jsr_coroutine(IsCall, IsReturn);
2244 // IEEE floating point
2245 0x14: decode FP_SHORTFUNC {
2246 // Integer to FP register moves must have RB == 31
2248 31: decode FP_FULLFUNC {
2249 format BasicOperateWithNopCheck {
2250 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
2251 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
2252 0x014: FailUnimpl::itoff(); // VAX-format conversion
2257 // Square root instructions must have FA == 31
2259 31: decode FP_TYPEFUNC {
2260 format FloatingPointOperate {
2261 #ifdef SS_COMPATIBLE_FP
2264 fault = Arithmetic_Fault;
2270 fault = Arithmetic_Fault;
2271 Fc.sf = sqrt(Fb.sf);
2276 fault = Arithmetic_Fault;
2283 // VAX-format sqrtf and sqrtg are not implemented
2284 0xa: FailUnimpl::sqrtfg();
2287 // IEEE floating point
2288 0x16: decode FP_SHORTFUNC_TOP2 {
2289 // The top two bits of the short function code break this space
2290 // into four groups: binary ops, compares, reserved, and conversions.
2291 // See Table 4-12 of AHB.
2292 // Most of these instructions may have various trapping and
2293 // rounding mode flags set; these are decoded in the
2294 // FloatingPointDecode template used by the
2295 // FloatingPointOperate format.
2297 // add/sub/mul/div: just decode on the short function code
2299 0: decode FP_TYPEFUNC {
2300 format FloatingPointOperate {
2301 #ifdef SS_COMPATIBLE_FP
2302 0x00: adds({{ Fc = Fa + Fb; }});
2303 0x01: subs({{ Fc = Fa - Fb; }});
2304 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
2305 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
2307 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2308 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2309 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
2310 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
2313 0x20: addt({{ Fc = Fa + Fb; }});
2314 0x21: subt({{ Fc = Fa - Fb; }});
2315 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
2316 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
2320 // Floating-point compare instructions must have the default
2321 // rounding mode, and may use the default trapping mode or
2322 // /SU. Both trapping modes are treated the same by M5; the
2323 // only difference on the real hardware (as far a I can tell)
2324 // is that without /SU you'd get an imprecise trap if you
2325 // tried to compare a NaN with something else (instead of an
2326 // "unordered" result).
2327 1: decode FP_FULLFUNC {
2328 format BasicOperateWithNopCheck {
2329 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2331 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2333 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2335 0x0a4, 0x5a4: cmptun({{ // unordered
2336 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2341 // The FP-to-integer and integer-to-FP conversion insts
2342 // require that FA be 31.
2344 31: decode FP_TYPEFUNC {
2345 format FloatingPointOperate {
2346 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2348 // The cvtts opcode is overloaded to be cvtst if the trap
2349 // mode is 2 or 6 (which are not valid otherwise)
2350 0x2c: decode FP_FULLFUNC {
2351 format BasicOperateWithNopCheck {
2352 // trap on denorm version "cvtst/s" is
2353 // simulated same as cvtst
2354 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2356 default: cvtts({{ Fc.sf = Fb; }});
2359 // The trapping mode for integer-to-FP conversions
2360 // must be /SUI or nothing; /U and /SU are not
2361 // allowed. The full set of rounding modes are
2362 // supported though.
2363 0x3c: decode FP_TRAPMODE {
2364 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2366 0x3e: decode FP_TRAPMODE {
2367 0,7: cvtqt({{ Fc = Fb.sq; }});
2375 0x17: decode FP_FULLFUNC {
2376 format BasicOperateWithNopCheck {
2378 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2381 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2384 // We treat the precise & imprecise trapping versions of
2385 // cvtql identically.
2386 0x130, 0x530: cvtqlv({{
2387 // To avoid overflow, all the upper 32 bits must match
2388 // the sign bit of the lower 32. We code this as
2389 // checking the upper 33 bits for all 0s or all 1s.
2390 uint64_t sign_bits = Fb.uq<63:31>;
2391 if (sign_bits != 0 && sign_bits != mask(33))
2392 fault = Integer_Overflow_Fault;
2393 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2396 0x020: cpys({{ // copy sign
2397 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2399 0x021: cpysn({{ // copy sign negated
2400 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2402 0x022: cpyse({{ // copy sign and exponent
2403 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2406 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2407 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2408 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2409 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2410 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2411 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2413 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2414 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2418 // miscellaneous mem-format ops
2419 0x18: decode MEMFUNC {
2426 format MiscPrefetch {
2427 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
2428 {{ xc->writeHint(EA, 64, memAccessFlags); }},
2429 IsMemRef, IsDataPrefetch, IsStore, MemWriteOp,
2433 format BasicOperate {
2436 /* Rb is a fake dependency so here is a fun way to get
2437 * the parser to understand that.
2439 Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0);
2446 // All of the barrier instructions below do nothing in
2447 // their execute() methods (hence the empty code blocks).
2448 // All of their functionality is hard-coded in the
2449 // pipeline based on the flags IsSerializing,
2450 // IsMemBarrier, and IsWriteBarrier. In the current
2451 // detailed CPU model, the execute() function only gets
2452 // called at fetch, so there's no way to generate pipeline
2453 // behavior at any other stage. Once we go to an
2454 // exec-in-exec CPU model we should be able to get rid of
2455 // these flags and implement this behavior via the
2456 // execute() methods.
2458 // trapb is just a barrier on integer traps, where excb is
2459 // a barrier on integer and FP traps. "EXCB is thus a
2460 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
2461 // them the same though.
2462 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
2463 0x0400: excb({{ }}, IsSerializing, No_OpClass);
2464 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
2465 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
2469 format BasicOperate {
2471 Ra = xc->readIntrFlag();
2473 }}, IsNonSpeculative);
2475 Ra = xc->readIntrFlag();
2477 }}, IsNonSpeculative);
2488 0x00: CallPal::call_pal({{
2491 && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
2492 // invalid pal function code, or attempt to do privileged
2493 // PAL call in non-kernel mode
2494 fault = Unimplemented_Opcode_Fault;
2497 // check to see if simulator wants to do something special
2498 // on this PAL call (including maybe suppress it)
2499 bool dopal = xc->simPalCheck(palFunc);
2502 AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
2503 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2504 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2507 }}, IsNonSpeculative);
2509 0x00: decode PALFUNC {
2510 format EmulatedCallPal {
2512 SimExit(curTick, "halt instruction encountered");
2513 }}, IsNonSpeculative);
2516 }}, IsNonSpeculative);
2517 // Read uniq reg into ABI return value register (r0)
2518 0x9e: rduniq({{ R0 = Runiq; }});
2519 // Write uniq reg with value from ABI arg register (r16)
2520 0x9f: wruniq({{ Runiq = R16; }});
2526 format HwLoadStore {
2527 0x1b: decode HW_LDST_QUAD {
2528 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2529 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2532 0x1f: decode HW_LDST_COND {
2533 0: decode HW_LDST_QUAD {
2534 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2535 {{ Mem.ul = Ra<31:0>; }}, L);
2536 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2537 {{ Mem.uq = Ra.uq; }}, Q);
2540 1: FailUnimpl::hw_st_cond();
2544 format BasicOperate {
2545 0x1e: hw_rei({{ xc->hwrei(); }});
2547 // M5 special opcodes use the reserved 0x01 opcode space
2548 0x01: decode M5FUNC {
2550 AlphaPseudo::arm(xc->xcBase());
2551 }}, IsNonSpeculative);
2553 AlphaPseudo::quiesce(xc->xcBase());
2554 }}, IsNonSpeculative);
2556 AlphaPseudo::ivlb(xc->xcBase());
2557 }}, No_OpClass, IsNonSpeculative);
2559 AlphaPseudo::ivle(xc->xcBase());
2560 }}, No_OpClass, IsNonSpeculative);
2562 AlphaPseudo::m5exit_old(xc->xcBase());
2563 }}, No_OpClass, IsNonSpeculative);
2565 AlphaPseudo::m5exit(xc->xcBase());
2566 }}, No_OpClass, IsNonSpeculative);
2567 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
2569 AlphaPseudo::resetstats(xc->xcBase());
2570 }}, IsNonSpeculative);
2572 AlphaPseudo::dumpstats(xc->xcBase());
2573 }}, IsNonSpeculative);
2574 0x42: dumpresetstats({{
2575 AlphaPseudo::dumpresetstats(xc->xcBase());
2576 }}, IsNonSpeculative);
2577 0x43: m5checkpoint({{
2578 AlphaPseudo::m5checkpoint(xc->xcBase());
2579 }}, IsNonSpeculative);
2581 AlphaPseudo::readfile(xc->xcBase());
2582 }}, IsNonSpeculative);
2584 AlphaPseudo::debugbreak(xc->xcBase());
2585 }}, IsNonSpeculative);
2586 0x52: m5switchcpu({{
2587 AlphaPseudo::switchcpu(xc->xcBase());
2588 }}, IsNonSpeculative);
2595 // this instruction is only valid in PAL mode
2596 if (!xc->inPalMode()) {
2597 fault = Unimplemented_Opcode_Fault;
2600 Ra = xc->readIpr(ipr_index, fault);
2604 // this instruction is only valid in PAL mode
2605 if (!xc->inPalMode()) {
2606 fault = Unimplemented_Opcode_Fault;
2609 xc->setIpr(ipr_index, Ra);
2610 if (traceData) { traceData->setData(Ra); }