3 // Alpha ISA description file.
21 #include "base/cprintf.hh"
22 #include "base/misc.hh"
23 #include "cpu/exec_context.hh"
24 #include "cpu/exetrace.hh"
25 #include "cpu/full_cpu/full_cpu.hh"
26 #include "cpu/full_cpu/op_class.hh"
27 #include "cpu/full_cpu/spec_state.hh"
28 #include "cpu/simple_cpu/simple_cpu.hh"
29 #include "cpu/static_inst.hh"
30 #include "sim/annotation.hh"
31 #include "sim/sim_events.hh"
34 #include "targetarch/ev5.hh"
39 // Universal (format-independent) fields
40 def bitfield OPCODE <31:26>;
41 def bitfield RA <25:21>;
42 def bitfield RB <20:16>;
45 def signed bitfield MEMDISP <15: 0>; // displacement
46 def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
48 // Memory-format jumps
49 def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
50 def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
53 def signed bitfield BRDISP <20: 0>; // displacement
55 // Integer operate format(s>;
56 def bitfield INTIMM <20:13>; // integer immediate (literal)
57 def bitfield IMM <12:12>; // immediate flag
58 def bitfield INTFUNC <11: 5>; // function code
59 def bitfield RC < 4: 0>; // dest reg
61 // Floating-point operate format
62 def bitfield FA <25:21>;
63 def bitfield FB <20:16>;
64 def bitfield FP_FULLFUNC <15: 5>; // complete function code
65 def bitfield FP_TRAPMODE <15:13>; // trapping mode
66 def bitfield FP_ROUNDMODE <12:11>; // rounding mode
67 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
68 def bitfield FP_SRCTYPE <10: 9>; // source reg type
69 def bitfield FP_SHORTFUNC < 8: 5>; // short function code
70 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
71 def bitfield FC < 4: 0>; // dest reg
74 def bitfield PALFUNC <25: 0>; // function code
76 // EV5 PAL instructions:
78 def bitfield HW_LDST_PHYS <15>; // address is physical
79 def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
80 def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
81 def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
82 def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
83 def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
84 def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
85 def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
88 def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
89 def bitfield HW_REI_MBZ <13: 0>; // must be zero
92 def bitfield HW_IPR_IDX <15:0>; // IPR index
95 def bitfield M5FUNC <7:0>;
100 'sb' : ('signed int', 8),
101 'ub' : ('unsigned int', 8),
102 'sw' : ('signed int', 16),
103 'uw' : ('unsigned int', 16),
104 'sl' : ('signed int', 32),
105 'ul' : ('unsigned int', 32),
106 'sq' : ('signed int', 64),
107 'uq' : ('unsigned int', 64),
108 'sf' : ('float', 32),
112 global operandTraitsMap
114 # Int regs default to unsigned, but code should not count on this.
115 # For clarity, descriptions that depend on unsigned behavior should
116 # explicitly specify '.uq'.
117 'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),
118 'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),
119 'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),
120 'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
121 'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
122 'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
123 'Mem': MemOperandTraits('uq', None,
124 ('IsMemRef', 'IsLoad', 'IsStore'), 4),
125 'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
126 'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
127 'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
128 # The next two are hacks for non-full-system call-pal emulation
129 'R0': IntRegOperandTraits('uq', '0', None, 1),
130 'R16': IntRegOperandTraits('uq', '16', None, 1),
133 defineDerivedOperandVars()
137 // just temporary, while comparing with old code for debugging
138 // #define SS_COMPATIBLE_DISASSEMBLY
140 /// Check "FP enabled" machine status bit. Called when executing any FP
141 /// instruction in full-system mode.
142 /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
143 /// if not. Non-full-system mode: always returns No_Fault.
145 inline Fault checkFpEnableFault(ExecContext *xc)
147 Fault fault = No_Fault; // dummy... this ipr access should not fault
148 if (!ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
154 inline Fault checkFpEnableFault(ExecContext *xc)
161 * Base class for all Alpha static instructions.
163 class AlphaStaticInst : public StaticInst<AlphaISA>
167 /// Make AlphaISA register dependence tags directly visible in
168 /// this class and derived classes. Maybe these should really
169 /// live here and not in the AlphaISA namespace.
170 enum DependenceTags {
171 FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
172 Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
173 Uniq_DepTag = AlphaISA::Uniq_DepTag,
174 IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
178 AlphaStaticInst(const char *mnem, MachInst _machInst,
180 : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
184 /// Print a register name for disassembly given the unique
185 /// dependence tag number (FP or int).
186 void printReg(std::ostream &os, int reg)
188 if (reg < FP_Base_DepTag) {
189 ccprintf(os, "r%d", reg);
192 ccprintf(os, "f%d", reg - FP_Base_DepTag);
196 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
198 std::stringstream ss;
200 ccprintf(ss, "%-10s ", mnemonic);
202 // just print the first two source regs... if there's
203 // a third one, it's a read-modify-write dest (Rc),
205 if (_numSrcRegs > 0) {
206 printReg(ss, _srcRegIdx[0]);
208 if (_numSrcRegs > 1) {
210 printReg(ss, _srcRegIdx[1]);
213 // just print the first dest... if there's a second one,
214 // it's generally implicit
215 if (_numDestRegs > 0) {
218 printReg(ss, _destRegIdx[0]);
227 def template BasicDeclare {{
229 * Static instruction class for "%(mnemonic)s".
231 class %(class_name)s : public %(base_class)s
235 %(class_name)s(MachInst machInst)
236 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
241 Fault execute(SimpleCPU *cpu, ExecContext *xc,
242 Trace::InstRecord *traceData)
244 SimpleCPU *memAccessObj __attribute__((unused)) = cpu;
245 Fault fault = No_Fault;
252 if (fault == No_Fault) {
259 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
260 Trace::InstRecord *traceData)
262 DynInst *memAccessObj __attribute__((unused)) = dynInst;
263 Fault fault = No_Fault;
270 if (fault == No_Fault) {
279 def template BasicDecode {{
280 return new %(class_name)s(machInst);
283 def template BasicDecodeWithMnemonic {{
284 return new %(class_name)s("%(mnemonic)s", machInst);
287 // The most basic instruction format... used only for a few misc. insts
288 def format BasicOperate(code, *flags) {{
289 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)
290 return iop.subst('BasicDeclare', 'BasicDecode')
295 ////////////////////////////////////////////////////////////////////
299 * Static instruction class for no-ops. This is a leaf class.
301 class Nop : public AlphaStaticInst
303 /// Disassembly of original instruction.
304 const std::string originalDisassembly;
308 Nop(const std::string _originalDisassembly, MachInst _machInst)
309 : AlphaStaticInst("nop", _machInst, No_OpClass),
310 originalDisassembly(_originalDisassembly)
317 Fault execute(SimpleCPU *cpu, ExecContext *xc,
318 Trace::InstRecord *traceData)
323 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
324 Trace::InstRecord *traceData)
329 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
331 #ifdef SS_COMPATIBLE_DISASSEMBLY
332 return originalDisassembly;
334 return csprintf("%-10s (%s)", "nop", originalDisassembly);
339 /// Helper function for decoding nops. Substitute Nop object
340 /// for original inst passed in as arg (and delete latter).
343 makeNop(AlphaStaticInst *inst)
345 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
352 return ('', 'return new Nop("%s", machInst);\n' % name)
356 // integer & FP operate instructions use Rc as dest, so check for
357 // Rc == 31 to detect nops
358 def template OperateNopCheckDecode {{
360 AlphaStaticInst *i = new %(class_name)s(machInst);
368 // Like BasicOperate format, but generates NOP if RC/FC == 31
369 def format BasicOperateWithNopCheck(code, *opt_args) {{
370 iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
372 return iop.subst('BasicDeclare', 'OperateNopCheckDecode')
376 ////////////////////////////////////////////////////////////////////
378 // Integer operate instructions
383 * Base class for integer immediate instructions.
385 class IntegerImm : public AlphaStaticInst
388 /// Immediate operand value (unsigned 8-bit int).
392 IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
393 : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
397 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
399 std::stringstream ss;
401 ccprintf(ss, "%-10s ", mnemonic);
403 // just print the first source reg... if there's
404 // a second one, it's a read-modify-write dest (Rc),
406 if (_numSrcRegs > 0) {
407 printReg(ss, _srcRegIdx[0]);
413 if (_numDestRegs > 0) {
415 printReg(ss, _destRegIdx[0]);
423 def template RegOrImmDecode {{
426 (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
427 : (AlphaStaticInst *)new %(class_name)s(machInst);
435 // Primary format for integer operate instructions:
436 // - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
437 // - Generates NOP if RC == 31.
438 def format IntegerOperate(code, *opt_flags) {{
439 # If the code block contains 'Rb_or_imm', we define two instructions,
440 # one using 'Rb' and one using 'imm', and have the decoder select
442 uses_imm = (code.find('Rb_or_imm') != -1)
445 # base code is reg version:
446 # rewrite by substituting 'Rb' for 'Rb_or_imm'
447 code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
448 # generate immediate version by substituting 'imm'
449 # note that imm takes no extenstion, so we extend
450 # the regexp to replace any extension as well
451 imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
453 # generate declaration for register version
454 cblk = CodeBlock(code)
455 iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)
456 decls = iop.subst('BasicDeclare')
459 # append declaration for imm version
460 imm_cblk = CodeBlock(imm_code)
461 imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,
463 decls += imm_iop.subst('BasicDeclare')
464 # decode checks IMM bit to pick correct version
465 decode = iop.subst('RegOrImmDecode')
467 # no imm version: just check for nop
468 decode = iop.subst('OperateNopCheckDecode')
470 return (decls, decode)
474 ////////////////////////////////////////////////////////////////////
476 // Floating-point instructions
478 // Note that many FP-type instructions which do not support all the
479 // various rounding & trapping modes use the simpler format
480 // BasicOperateWithNopCheck.
485 * Base class for general floating-point instructions. Includes
486 * support for various Alpha rounding and trapping modes. Only FP
487 * instructions that require this support are derived from this
488 * class; the rest derive directly from AlphaStaticInst.
490 class AlphaFP : public AlphaStaticInst
493 /// Alpha FP rounding modes.
495 Chopped = 0, ///< round toward zero
496 Minus_Infinity = 1, ///< round toward minus infinity
497 Normal = 2, ///< round to nearest (default)
498 Dynamic = 3, ///< use FPCR setting (in instruction)
499 Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
502 /// Alpha FP trapping modes.
503 /// For instructions that produce integer results, the
504 /// "Underflow Enable" modes really mean "Overflow Enable", and
505 /// the assembly modifier is V rather than U.
507 /// default: nothing enabled
508 Imprecise = 0, ///< no modifier
509 /// underflow/overflow traps enabled, inexact disabled
510 Underflow_Imprecise = 1, ///< /U or /V
511 Underflow_Precise = 5, ///< /SU or /SV
512 /// underflow/overflow and inexact traps enabled
513 Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
518 static const int alphaToC99RoundingMode[];
521 /// Map enum RoundingMode values to disassembly suffixes.
522 static const char *roundingModeSuffix[];
523 /// Map enum TrappingMode values to FP disassembly suffixes.
524 static const char *fpTrappingModeSuffix[];
525 /// Map enum TrappingMode values to integer disassembly suffixes.
526 static const char *intTrappingModeSuffix[];
528 /// This instruction's rounding mode.
529 RoundingMode roundingMode;
530 /// This instruction's trapping mode.
531 TrappingMode trappingMode;
534 AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
535 : AlphaStaticInst(mnem, _machInst, __opClass),
536 roundingMode((enum RoundingMode)FP_ROUNDMODE),
537 trappingMode((enum TrappingMode)FP_TRAPMODE)
539 if (trappingMode != Imprecise) {
540 warn("Warning: precise FP traps unimplemented\n");
546 getC99RoundingMode(ExecContext *xc)
548 if (roundingMode == Dynamic) {
549 return alphaToC99RoundingMode[bits(xc->readFpcr(), 59, 58)];
552 return alphaToC99RoundingMode[roundingMode];
557 // This differs from the AlphaStaticInst version only in
558 // printing suffixes for non-default rounding & trapping modes.
559 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
561 std::string mnem_str(mnemonic);
563 mnem_str += ((_destRegIdx[0] >= FP_Base_DepTag)
564 ? fpTrappingModeSuffix[trappingMode]
565 : intTrappingModeSuffix[trappingMode]);
566 mnem_str += roundingModeSuffix[roundingMode];
568 std::stringstream ss;
570 ccprintf(ss, "%-10s ", mnem_str.c_str());
572 // just print the first two source regs... if there's
573 // a third one, it's a read-modify-write dest (Rc),
575 if (_numSrcRegs > 0) {
576 printReg(ss, _srcRegIdx[0]);
578 if (_numSrcRegs > 1) {
580 printReg(ss, _srcRegIdx[1]);
583 // just print the first dest... if there's a second one,
584 // it's generally implicit
585 if (_numDestRegs > 0) {
588 printReg(ss, _destRegIdx[0]);
596 const int AlphaFP::alphaToC99RoundingMode[] = {
597 FE_TOWARDZERO, // Chopped
598 FE_DOWNWARD, // Minus_Infinity
599 FE_TONEAREST, // Normal
600 FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
604 const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
605 // mark invalid trapping modes, but don't fail on them, because
606 // you could decode anything on a misspeculated path
607 const char *AlphaFP::fpTrappingModeSuffix[] =
608 { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
609 const char *AlphaFP::intTrappingModeSuffix[] =
610 { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
614 def template FloatingPointDeclare {{
616 * "Fast" static instruction class for "%(mnemonic)s" (imprecise
617 * trapping mode, normal rounding mode).
619 class %(class_name)sFast : public %(base_class)s
623 %(class_name)sFast(MachInst machInst)
624 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
629 Fault execute(SimpleCPU *cpu, ExecContext *xc,
630 Trace::InstRecord *traceData)
632 Fault fault = No_Fault;
639 if (fault == No_Fault) {
646 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
647 Trace::InstRecord *traceData)
649 Fault fault = No_Fault;
656 if (fault == No_Fault) {
665 * General static instruction class for "%(mnemonic)s". Supports
666 * all the various rounding and trapping modes.
668 class %(class_name)sGeneral : public %(base_class)s
672 %(class_name)sGeneral(MachInst machInst)
673 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
678 Fault execute(SimpleCPU *cpu, ExecContext *xc,
679 Trace::InstRecord *traceData)
681 Fault fault = No_Fault;
688 fesetround(getC99RoundingMode(xc));
694 fesetround(FE_TONEAREST);
697 if (fault == No_Fault) {
704 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
705 Trace::InstRecord *traceData)
707 Fault fault = No_Fault;
714 fesetround(getC99RoundingMode(xc));
720 fesetround(FE_TONEAREST);
723 if (fault == No_Fault) {
732 def template FloatingPointDecode {{
734 bool fast = (FP_TRAPMODE == AlphaFP::Imprecise
735 && FP_ROUNDMODE == AlphaFP::Normal);
737 fast ? (AlphaStaticInst *)new %(class_name)sFast(machInst) :
738 (AlphaStaticInst *)new %(class_name)sGeneral(machInst);
749 // General format for floating-point operate instructions:
750 // - Checks trapping and rounding mode flags. Trapping modes
751 // currently unimplemented (will fail).
752 // - Generates NOP if FC == 31.
753 def format FloatingPointOperate(code, *opt_args) {{
754 iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code),
756 return iop.subst('FloatingPointDeclare', 'FloatingPointDecode')
760 ////////////////////////////////////////////////////////////////////
762 // Memory-format instructions: LoadAddress, Load, Store
767 * Base class for general Alpha memory-format instructions.
769 class Memory : public AlphaStaticInst
773 /// Displacement for EA calculation (signed).
775 /// Memory request flags. See mem_req_base.hh.
776 unsigned memAccessFlags;
779 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
780 : AlphaStaticInst(mnem, _machInst, __opClass),
781 disp(MEMDISP), memAccessFlags(0)
785 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
787 return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
788 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
793 * Base class for a few miscellaneous memory-format insts
794 * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
795 * None of these instructions has a destination register either.
797 class MemoryNoDisp : public AlphaStaticInst
800 /// Memory request flags. See mem_req_base.hh.
801 unsigned memAccessFlags;
804 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass)
805 : AlphaStaticInst(mnem, _machInst, __opClass),
810 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
812 return csprintf("%-10s (r%d)", mnemonic, RB);
817 * Base class for "fake" effective-address computation
818 * instructions returnded by eaCompInst().
820 class EACompBase : public AlphaStaticInst
824 EACompBase(MachInst machInst)
825 : AlphaStaticInst("(eacomp)", machInst, IntALU)
829 Fault execute(SimpleCPU *cpu, ExecContext *xc,
830 Trace::InstRecord *traceData)
831 { panic("attempt to execute eacomp"); }
833 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
834 Trace::InstRecord *traceData)
835 { panic("attempt to execute eacomp"); }
839 * Base class for "fake" memory-access instructions returnded by
842 class MemAccBase : public AlphaStaticInst
846 MemAccBase(MachInst machInst, OpClass __opClass)
847 : AlphaStaticInst("(memacc)", machInst, __opClass)
851 Fault execute(SimpleCPU *cpu, ExecContext *xc,
852 Trace::InstRecord *traceData)
853 { panic("attempt to execute memacc"); }
855 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
856 Trace::InstRecord *traceData)
857 { panic("attempt to execute memacc"); }
863 def format LoadAddress(code) {{
864 iop = InstObjParams(name, Name, 'Memory', CodeBlock(code))
865 return iop.subst('BasicDeclare', 'BasicDecode')
869 def template LoadStoreDeclare {{
871 * Static instruction class for "%(mnemonic)s".
873 class %(class_name)s : public %(base_class)s
878 * "Fake" effective address computation class for "%(mnemonic)s".
880 class EAComp : public EACompBase
884 EAComp(MachInst machInst)
885 : EACompBase(machInst)
892 * "Fake" memory access instruction class for "%(mnemonic)s".
894 class MemAcc : public MemAccBase
898 MemAcc(MachInst machInst)
899 : MemAccBase(machInst, %(op_class)s)
901 %(memacc_constructor)s;
905 /// Pointer to EAComp object.
906 StaticInstPtr<AlphaISA> eaCompPtr;
907 /// Pointer to MemAcc object.
908 StaticInstPtr<AlphaISA> memAccPtr;
912 StaticInstPtr<AlphaISA> eaCompInst() { return eaCompPtr; }
913 StaticInstPtr<AlphaISA> memAccInst() { return memAccPtr; }
916 %(class_name)s(MachInst machInst)
917 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
918 eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst))
923 Fault execute(SimpleCPU *cpu, ExecContext *xc,
924 Trace::InstRecord *traceData)
926 SimpleCPU *memAccessObj = cpu;
928 Fault fault = No_Fault;
932 %(simple_nonmem_rd)s;
935 if (fault == No_Fault) {
940 if (fault == No_Fault) {
944 if (fault == No_Fault) {
948 if (fault == No_Fault) {
949 %(simple_nonmem_wb)s;
955 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
956 Trace::InstRecord *traceData)
958 DynInst *memAccessObj = dynInst;
960 Fault fault = No_Fault;
967 if (fault == No_Fault) {
972 if (fault == No_Fault) {
976 if (fault == No_Fault) {
980 if (fault == No_Fault) {
990 def template PrefetchDeclare {{
992 * Static instruction class for "%(mnemonic)s".
994 class %(class_name)s : public %(base_class)s
998 %(class_name)s(MachInst machInst)
999 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
1004 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1005 Trace::InstRecord *traceData)
1008 Fault fault = No_Fault;
1010 %(fp_enable_check)s;
1012 %(simple_nonmem_rd)s;
1015 if (fault == No_Fault) {
1016 cpu->prefetch(EA, memAccessFlags);
1022 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1023 Trace::InstRecord *traceData)
1026 Fault fault = No_Fault;
1028 %(fp_enable_check)s;
1033 if (fault == No_Fault) {
1034 dynInst->prefetch(EA, memAccessFlags);
1043 // load instructions use Ra as dest, so check for
1044 // Ra == 31 to detect nops
1045 def template LoadNopCheckDecode {{
1047 AlphaStaticInst *i = new %(class_name)s(machInst);
1056 // for some load instructions, Ra == 31 indicates a prefetch (not a nop)
1057 def template LoadPrefetchCheckDecode {{
1060 return new %(class_name)s(machInst);
1063 return new %(class_name)sPrefetch(machInst);
1070 global LoadStoreBase
1071 def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
1072 base_class = 'Memory', flags = [],
1073 declare_template = 'LoadStoreDeclare',
1074 decode_template = 'BasicDecode'):
1075 # Segregate flags into instruction flags (handled by InstObjParams)
1076 # and memory access flags (handled here).
1078 # Would be nice to autogenerate this list, but oh well.
1079 valid_mem_flags = ['LOCKED', 'EVICT_NEXT', 'PF_EXCLUSIVE']
1083 if f in valid_mem_flags:
1086 inst_flags.append(f)
1088 ea_cblk = CodeBlock(ea_code)
1089 memacc_cblk = CodeBlock(memacc_code)
1090 postacc_cblk = CodeBlock(postacc_code)
1092 cblk = CodeBlock(ea_code + memacc_code + postacc_code)
1093 iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
1095 iop.ea_constructor = ea_cblk.constructor
1096 iop.ea_code = ea_cblk.code
1097 iop.memacc_constructor = memacc_cblk.constructor
1098 iop.memacc_code = memacc_cblk.code
1099 iop.postacc_code = postacc_cblk.code
1101 mem_flags = string.join(mem_flags, '|')
1103 iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
1105 return iop.subst(declare_template, decode_template)
1109 def format LoadOrNop(ea_code, memacc_code, *flags) {{
1110 return LoadStoreBase(name, Name, ea_code, memacc_code,
1112 decode_template = 'LoadNopCheckDecode')
1116 // Note that the flags passed in apply only to the prefetch version
1117 def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
1118 # declare the load instruction object and generate the decode block
1120 LoadStoreBase(name, Name, ea_code, memacc_code,
1121 decode_template = 'LoadPrefetchCheckDecode')
1123 # Declare the prefetch instruction object.
1125 # convert flags from tuple to list to make them mutable
1126 pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'RdPort']
1128 (pfdecls, pfdecode) = \
1129 LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
1131 declare_template = 'PrefetchDeclare')
1133 return (decls + pfdecls, decode)
1137 def format Store(ea_code, memacc_code, *flags) {{
1138 return LoadStoreBase(name, Name, ea_code, memacc_code,
1143 def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
1144 return LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
1149 // Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
1150 def format MiscPrefetch(ea_code, memacc_code, *flags) {{
1151 return LoadStoreBase(name, Name, ea_code, memacc_code,
1152 flags = flags, base_class = 'MemoryNoDisp')
1156 ////////////////////////////////////////////////////////////////////
1162 * Base class for instructions whose disassembly is not purely a
1163 * function of the machine instruction (i.e., it depends on the
1164 * PC). This class overrides the disassemble() method to check
1165 * the PC and symbol table values before re-using a cached
1166 * disassembly string. This is necessary for branches and jumps,
1167 * where the disassembly string includes the target address (which
1168 * may depend on the PC and/or symbol table).
1170 class PCDependentDisassembly : public AlphaStaticInst
1173 /// Cached program counter from last disassembly
1175 /// Cached symbol table pointer from last disassembly
1176 const SymbolTable *cachedSymtab;
1179 PCDependentDisassembly(const char *mnem, MachInst _machInst,
1181 : AlphaStaticInst(mnem, _machInst, __opClass),
1182 cachedPC(0), cachedSymtab(0)
1186 const std::string &disassemble(Addr pc, const SymbolTable *symtab)
1188 if (!cachedDisassembly ||
1189 pc != cachedPC || symtab != cachedSymtab)
1191 if (cachedDisassembly)
1192 delete cachedDisassembly;
1195 new std::string(generateDisassembly(pc, symtab));
1197 cachedSymtab = symtab;
1200 return *cachedDisassembly;
1205 * Base class for branches (PC-relative control transfers),
1206 * conditional or unconditional.
1208 class Branch : public PCDependentDisassembly
1211 /// Displacement to target address (signed).
1215 Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
1216 : PCDependentDisassembly(mnem, _machInst, __opClass),
1221 Addr branchTarget(Addr branchPC)
1223 return branchPC + 4 + disp;
1226 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1228 std::stringstream ss;
1230 ccprintf(ss, "%-10s ", mnemonic);
1232 // There's only one register arg (RA), but it could be
1233 // either a source (the condition for conditional
1234 // branches) or a destination (the link reg for
1235 // unconditional branches)
1236 if (_numSrcRegs > 0) {
1237 printReg(ss, _srcRegIdx[0]);
1240 else if (_numDestRegs > 0) {
1241 printReg(ss, _destRegIdx[0]);
1245 #ifdef SS_COMPATIBLE_DISASSEMBLY
1246 if (_numSrcRegs == 0 && _numDestRegs == 0) {
1252 Addr target = pc + 4 + disp;
1255 if (symtab && symtab->findSymbol(target, str))
1258 ccprintf(ss, "0x%x", target);
1265 * Base class for jumps (register-indirect control transfers). In
1266 * the Alpha ISA, these are always unconditional.
1268 class Jump : public PCDependentDisassembly
1272 /// Displacement to target address (signed).
1277 Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
1278 : PCDependentDisassembly(mnem, _machInst, __opClass),
1283 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1285 std::stringstream ss;
1287 ccprintf(ss, "%-10s ", mnemonic);
1289 #ifdef SS_COMPATIBLE_DISASSEMBLY
1290 if (_numDestRegs == 0) {
1296 if (_numDestRegs > 0) {
1297 printReg(ss, _destRegIdx[0]);
1301 ccprintf(ss, "(r%d)", RB);
1308 def template JumpOrBranchDecode {{
1310 ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
1311 : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
1314 def format CondBranch(code) {{
1315 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
1316 iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
1317 ('IsDirectControl', 'IsCondControl'))
1318 return iop.subst('BasicDeclare', 'BasicDecode')
1322 global UncondCtrlBase
1323 def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
1324 # Declare basic control transfer w/o link (i.e. link reg is R31)
1325 nolink_code = 'NPC = %s;\n' % npc_expr
1326 nolink_iop = InstObjParams(name, Name, base_class,
1327 CodeBlock(nolink_code), flags)
1328 decls = nolink_iop.subst('BasicDeclare')
1330 # Generate declaration of '*AndLink' version, append to decls
1331 link_code = 'Ra = NPC & ~3;\n' + nolink_code
1332 link_iop = InstObjParams(name, Name + 'AndLink', base_class,
1333 CodeBlock(link_code), flags)
1334 decls += link_iop.subst('BasicDeclare')
1336 # need to use link_iop for the decode template since it is expecting
1337 # the shorter version of class_name (w/o "AndLink")
1338 return (decls, nolink_iop.subst('JumpOrBranchDecode'))
1341 def format UncondBranch(*flags) {{
1342 flags += ('IsUncondControl', 'IsDirectControl')
1343 return UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
1346 def format Jump(*flags) {{
1347 flags += ('IsUncondControl', 'IsIndirectControl')
1348 return UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
1354 * Base class for emulated call_pal calls (used only in
1355 * non-full-system mode).
1357 class EmulatedCallPal : public AlphaStaticInst
1362 EmulatedCallPal(const char *mnem, MachInst _machInst,
1364 : AlphaStaticInst(mnem, _machInst, __opClass)
1368 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1370 #ifdef SS_COMPATIBLE_DISASSEMBLY
1371 return csprintf("%s %s", "call_pal", mnemonic);
1373 return csprintf("%-10s %s", "call_pal", mnemonic);
1379 def format EmulatedCallPal(code) {{
1380 iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code))
1381 return iop.subst('BasicDeclare', 'BasicDecode')
1386 * Base class for full-system-mode call_pal instructions.
1387 * Probably could turn this into a leaf class and get rid of the
1390 class CallPalBase : public AlphaStaticInst
1393 int palFunc; ///< Function code part of instruction
1394 int palOffset; ///< Target PC, offset from IPR_PAL_BASE
1397 CallPalBase(const char *mnem, MachInst _machInst,
1399 : AlphaStaticInst(mnem, _machInst, __opClass),
1402 int palPriv = ((machInst & 0x80) != 0);
1403 int shortPalFunc = (machInst & 0x3f);
1404 palOffset = 0x2001 + (palPriv << 12) + (shortPalFunc << 6);
1407 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1409 return csprintf("%-10s %#x", "call_pal", palFunc);
1415 def format CallPal(code) {{
1416 iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code))
1417 return iop.subst('BasicDeclare', 'BasicDecode')
1425 * Base class for hw_ld and hw_st.
1427 class HwLoadStore : public AlphaStaticInst
1431 /// Displacement for EA calculation (signed).
1433 /// Memory request flags. See mem_req_base.hh.
1434 unsigned memAccessFlags;
1437 HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass)
1438 : AlphaStaticInst(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
1441 if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
1442 if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
1443 if (HW_LDST_VPTE) memAccessFlags |= VPTE;
1444 if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
1447 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1449 #ifdef SS_COMPATIBLE_DISASSEMBLY
1450 return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
1452 // HW_LDST_LOCK and HW_LDST_COND are the same bit.
1453 const char *lock_str =
1454 (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
1456 return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
1457 mnemonic, RA, disp, RB,
1458 HW_LDST_PHYS ? ",PHYS" : "",
1459 HW_LDST_ALT ? ",ALT" : "",
1460 HW_LDST_QUAD ? ",QUAD" : "",
1461 HW_LDST_VPTE ? ",VPTE" : "",
1469 def format HwLoadStore(ea_code, memacc_code, class_ext, *flags) {{
1470 return LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
1472 base_class = 'HwLoadStore')
1476 def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, *flags) {{
1477 return LoadStoreBase(name, Name + class_ext,
1478 ea_code, memacc_code, postacc_code,
1480 base_class = 'HwLoadStore')
1486 * Base class for hw_mfpr and hw_mtpr.
1488 class HwMoveIPR : public AlphaStaticInst
1491 /// Index of internal processor register.
1495 HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
1496 : AlphaStaticInst(mnem, _machInst, __opClass),
1497 ipr_index(HW_IPR_IDX)
1501 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1503 if (_numSrcRegs > 0) {
1505 return csprintf("%-10s r%d,IPR(%#x)",
1506 mnemonic, RA, ipr_index);
1510 return csprintf("%-10s IPR(%#x),r%d",
1511 mnemonic, ipr_index, RA);
1517 def format HwMoveIPR(code) {{
1518 iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
1519 return iop.subst('BasicDeclare', 'BasicDecode')
1524 * Static instruction class for unimplemented instructions that
1525 * cause simulator termination. Note that these are recognized
1526 * (legal) instructions that the simulator does not support; the
1527 * 'Unknown' class is used for unrecognized/illegal instructions.
1528 * This is a leaf class.
1530 class FailUnimplemented : public AlphaStaticInst
1534 FailUnimplemented(const char *_mnemonic, MachInst _machInst)
1535 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
1539 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1540 Trace::InstRecord *traceData)
1542 panic("attempt to execute unimplemented instruction '%s' "
1543 "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
1544 return Unimplemented_Opcode_Fault;
1547 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1548 Trace::InstRecord *traceData)
1550 // don't panic if this is a misspeculated instruction
1552 panic("attempt to execute unimplemented instruction '%s' "
1553 "(inst 0x%08x, opcode 0x%x)",
1554 mnemonic, machInst, OPCODE);
1555 return Unimplemented_Opcode_Fault;
1558 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1560 return csprintf("%-10s (unimplemented)", mnemonic);
1565 * Base class for unimplemented instructions that cause a warning
1566 * to be printed (but do not terminate simulation). This
1567 * implementation is a little screwy in that it will print a
1568 * warning for each instance of a particular unimplemented machine
1569 * instruction, not just for each unimplemented opcode. Should
1570 * probably make the 'warned' flag a static member of the derived
1573 class WarnUnimplemented : public AlphaStaticInst
1576 /// Have we warned on this instruction yet?
1581 WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
1582 : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
1586 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1587 Trace::InstRecord *traceData)
1590 warn("Warning: instruction '%s' unimplemented\n", mnemonic);
1597 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1598 Trace::InstRecord *traceData)
1600 if (!xc->spec_mode && !warned) {
1601 warn("Warning: instruction '%s' unimplemented\n", mnemonic);
1608 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1610 #ifdef SS_COMPATIBLE_DISASSEMBLY
1611 return csprintf("%-10s", mnemonic);
1613 return csprintf("%-10s (unimplemented)", mnemonic);
1619 def template WarnUnimplDeclare {{
1621 * Static instruction class for "%(mnemonic)s".
1623 class %(class_name)s : public %(base_class)s
1627 %(class_name)s(MachInst machInst)
1628 : %(base_class)s("%(mnemonic)s", machInst)
1635 def format FailUnimpl() {{
1636 iop = InstObjParams(name, 'FailUnimplemented')
1637 return ('', iop.subst('BasicDecodeWithMnemonic'))
1640 def format WarnUnimpl() {{
1641 iop = InstObjParams(name, Name, 'WarnUnimplemented')
1642 return iop.subst('WarnUnimplDeclare', 'BasicDecode')
1647 * Static instruction class for unknown (illegal) instructions.
1648 * These cause simulator termination if they are executed in a
1649 * non-speculative mode. This is a leaf class.
1651 class Unknown : public AlphaStaticInst
1655 Unknown(MachInst _machInst)
1656 : AlphaStaticInst("unknown", _machInst, No_OpClass)
1660 Fault execute(SimpleCPU *cpu, ExecContext *xc,
1661 Trace::InstRecord *traceData)
1663 panic("attempt to execute unknown instruction "
1664 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1665 return Unimplemented_Opcode_Fault;
1668 Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
1669 Trace::InstRecord *traceData)
1671 // don't panic if this is a misspeculated instruction
1673 panic("attempt to execute unknown instruction "
1674 "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
1675 return Unimplemented_Opcode_Fault;
1678 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
1680 return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
1681 "unknown", machInst, OPCODE);
1686 def format Unknown() {{
1687 return ('', 'return new Unknown(machInst);\n')
1692 /// Return opa + opb, summing carry into third arg.
1694 addc(uint64_t opa, uint64_t opb, int &carry)
1696 uint64_t res = opa + opb;
1697 if (res < opa || res < opb)
1702 /// Multiply two 64-bit values (opa * opb), returning the 128-bit
1703 /// product in res_hi and res_lo.
1705 mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
1707 // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
1708 uint64_t opa_hi = opa<63:32>;
1709 uint64_t opa_lo = opa<31:0>;
1710 uint64_t opb_hi = opb<63:32>;
1711 uint64_t opb_lo = opb<31:0>;
1713 res_lo = opa_lo * opb_lo;
1715 // The middle partial products logically belong in bit
1716 // positions 95 to 32. Thus the lower 32 bits of each product
1717 // sum into the upper 32 bits of the low result, while the
1718 // upper 32 sum into the low 32 bits of the upper result.
1719 uint64_t partial1 = opa_hi * opb_lo;
1720 uint64_t partial2 = opa_lo * opb_hi;
1722 uint64_t partial1_lo = partial1<31:0> << 32;
1723 uint64_t partial1_hi = partial1<63:32>;
1724 uint64_t partial2_lo = partial2<31:0> << 32;
1725 uint64_t partial2_hi = partial2<63:32>;
1727 // Add partial1_lo and partial2_lo to res_lo, keeping track
1728 // of any carries out
1730 res_lo = addc(partial1_lo, res_lo, carry_out);
1731 res_lo = addc(partial2_lo, res_lo, carry_out);
1733 // Now calculate the high 64 bits...
1734 res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
1737 /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
1738 /// See Table 2-2 of Alpha AHB.
1742 int hibit = old_exp<7:>;
1743 int lobits = old_exp<6:0>;
1746 return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
1749 return (lobits == 0) ? 0 : (0x380 | lobits);
1753 /// Convert a 32-bit S-floating value to the equivalent 64-bit
1754 /// representation to be stored in an FP reg.
1756 s_to_t(uint32_t s_val)
1758 uint64_t tmp = s_val;
1759 return (tmp<31:> << 63 // sign bit
1760 | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
1761 | tmp<22:0> << 29); // fraction
1764 /// Convert a 64-bit T-floating value to the equivalent 32-bit
1765 /// S-floating representation to be stored in memory.
1767 t_to_s(uint64_t t_val)
1769 return (t_val<63:62> << 30 // sign bit & hi exp bit
1770 | t_val<58:29>); // rest of exp & fraction
1774 decode OPCODE default Unknown::unknown() {
1776 format LoadAddress {
1777 0x08: lda({{ Ra = Rb + disp; }});
1778 0x09: ldah({{ Ra = Rb + (disp << 16); }});
1782 0x0a: ldbu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.ub; }});
1783 0x0c: ldwu({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uw; }});
1784 0x0b: ldq_u({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }});
1785 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
1786 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
1787 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
1790 format LoadOrPrefetch {
1791 0x28: ldl({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }});
1792 0x29: ldq({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, EVICT_NEXT);
1793 0x22: lds({{ EA = Rb + disp; }}, {{ Fa.uq = s_to_t(Mem.ul); }},
1798 0x0e: stb({{ EA = Rb + disp; }}, {{ Mem.ub = Ra<7:0>; }});
1799 0x0d: stw({{ EA = Rb + disp; }}, {{ Mem.uw = Ra<15:0>; }});
1800 0x2c: stl({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }});
1801 0x2d: stq({{ EA = Rb + disp; }}, {{ Mem.uq = Ra.uq; }});
1802 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
1803 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
1804 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
1808 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
1810 uint64_t tmp = Mem_write_result;
1812 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1814 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
1816 uint64_t tmp = Mem_write_result;
1817 // If the write operation returns 0 or 1, then
1818 // this was a conventional store conditional,
1819 // and the value indicates the success/failure
1820 // of the operation. If another value is
1821 // returned, then this was a Turbolaser
1822 // mailbox access, and we don't update the
1823 // result register at all.
1824 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1828 format IntegerOperate {
1830 0x10: decode INTFUNC { // integer arithmetic operations
1832 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1834 uint32_t tmp = Ra.sl + Rb_or_imm.sl;
1835 // signed overflow occurs when operands have same sign
1836 // and sign of result does not match.
1837 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1838 fault = Integer_Overflow_Fault;
1841 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1842 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1844 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1846 uint64_t tmp = Ra + Rb_or_imm;
1847 // signed overflow occurs when operands have same sign
1848 // and sign of result does not match.
1849 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1850 fault = Integer_Overflow_Fault;
1853 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1854 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1856 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1858 uint32_t tmp = Ra.sl - Rb_or_imm.sl;
1859 // signed overflow detection is same as for add,
1860 // except we need to look at the *complemented*
1861 // sign bit of the subtrahend (Rb), i.e., if the initial
1862 // signs are the *same* then no overflow can occur
1863 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1864 fault = Integer_Overflow_Fault;
1867 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1868 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1870 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1872 uint64_t tmp = Ra - Rb_or_imm;
1873 // signed overflow detection is same as for add,
1874 // except we need to look at the *complemented*
1875 // sign bit of the subtrahend (Rb), i.e., if the initial
1876 // signs are the *same* then no overflow can occur
1877 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1878 fault = Integer_Overflow_Fault;
1881 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1882 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1884 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1885 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1886 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }});
1887 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1888 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }});
1894 for (int i = 0; i < 8; ++i) {
1895 tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1903 0x11: decode INTFUNC { // integer logical operations
1905 0x00: and({{ Rc = Ra & Rb_or_imm; }});
1906 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1907 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1908 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1909 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1910 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1912 // conditional moves
1913 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1914 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1915 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1916 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1917 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }});
1918 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1919 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1920 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }});
1922 // For AMASK, RA must be R31.
1924 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1927 // For IMPLVER, RA must be R31 and the B operand
1928 // must be the immediate value 1.
1932 // return EV5 for FULL_SYSTEM and EV6 otherwise
1945 // The mysterious 11.25...
1946 0x25: WarnUnimpl::eleven25();
1950 0x12: decode INTFUNC {
1951 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
1952 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
1953 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
1955 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
1956 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
1957 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
1958 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
1961 int bv = Rb_or_imm<2:0>;
1962 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
1965 int bv = Rb_or_imm<2:0>;
1966 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
1969 int bv = Rb_or_imm<2:0>;
1970 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
1973 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
1974 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
1975 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
1976 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
1979 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
1981 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
1983 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
1985 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
1986 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
1987 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
1988 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
1991 int bv = Rb_or_imm<2:0>;
1992 Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
1995 int bv = Rb_or_imm<2:0>;
1996 Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
1999 int bv = Rb_or_imm<2:0>;
2000 Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0;
2004 uint64_t zapmask = 0;
2005 for (int i = 0; i < 8; ++i) {
2007 zapmask |= (mask(8) << (i * 8));
2012 uint64_t zapmask = 0;
2013 for (int i = 0; i < 8; ++i) {
2015 zapmask |= (mask(8) << (i * 8));
2021 0x13: decode INTFUNC { // integer multiplies
2022 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMULT);
2023 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMULT);
2026 mul128(Ra, Rb_or_imm, hi, lo);
2030 // 32-bit multiply with trap on overflow
2031 int64_t Rax = Ra.sl; // sign extended version of Ra.sl
2032 int64_t Rbx = Rb_or_imm.sl;
2033 int64_t tmp = Rax * Rbx;
2034 // To avoid overflow, all the upper 32 bits must match
2035 // the sign bit of the lower 32. We code this as
2036 // checking the upper 33 bits for all 0s or all 1s.
2037 uint64_t sign_bits = tmp<63:31>;
2038 if (sign_bits != 0 && sign_bits != mask(33))
2039 fault = Integer_Overflow_Fault;
2043 // 64-bit multiply with trap on overflow
2045 mul128(Ra, Rb_or_imm, hi, lo);
2046 // all the upper 64 bits must match the sign bit of
2048 if (!((hi == 0 && lo<63:> == 0) ||
2049 (hi == mask(64) && lo<63:> == 1)))
2050 fault = Integer_Overflow_Fault;
2055 0x1c: decode INTFUNC {
2056 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
2057 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
2078 format BasicOperateWithNopCheck {
2080 31: ftoit({{ Rc = Fa.uq; }}, FloatCVT);
2083 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
2090 // Conditional branches.
2092 0x39: beq({{ cond = (Ra == 0); }});
2093 0x3d: bne({{ cond = (Ra != 0); }});
2094 0x3e: bge({{ cond = (Ra.sq >= 0); }});
2095 0x3f: bgt({{ cond = (Ra.sq > 0); }});
2096 0x3b: ble({{ cond = (Ra.sq <= 0); }});
2097 0x3a: blt({{ cond = (Ra.sq < 0); }});
2098 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
2099 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
2101 0x31: fbeq({{ cond = (Fa == 0); }});
2102 0x35: fbne({{ cond = (Fa != 0); }});
2103 0x36: fbge({{ cond = (Fa >= 0); }});
2104 0x37: fbgt({{ cond = (Fa > 0); }});
2105 0x33: fble({{ cond = (Fa <= 0); }});
2106 0x32: fblt({{ cond = (Fa < 0); }});
2109 // unconditional branches
2110 format UncondBranch {
2115 // indirect branches
2116 0x1a: decode JMPFUNC {
2121 3: jsr_coroutine(IsCall, IsReturn);
2125 // IEEE floating point
2126 0x14: decode FP_SHORTFUNC {
2127 // Integer to FP register moves must have RB == 31
2129 31: decode FP_FULLFUNC {
2130 format BasicOperateWithNopCheck {
2131 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCVT);
2132 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCVT);
2133 0x014: FailUnimpl::itoff(); // VAX-format conversion
2138 // Square root instructions must have FA == 31
2140 31: decode FP_TYPEFUNC {
2141 format FloatingPointOperate {
2142 #ifdef SS_COMPATIBLE_FP
2145 fault = Arithmetic_Fault;
2151 fault = Arithmetic_Fault;
2152 Fc.sf = sqrt(Fb.sf);
2157 fault = Arithmetic_Fault;
2164 // VAX-format sqrtf and sqrtg are not implemented
2165 0xa: FailUnimpl::sqrtfg();
2168 // IEEE floating point
2169 0x16: decode FP_SHORTFUNC_TOP2 {
2170 // The top two bits of the short function code break this space
2171 // into four groups: binary ops, compares, reserved, and conversions.
2172 // See Table 4-12 of AHB.
2173 // Most of these instructions may have various trapping and
2174 // rounding mode flags set; these are decoded in the
2175 // FloatingPointDecode template used by the
2176 // FloatingPointOperate format.
2178 // add/sub/mul/div: just decode on the short function code
2180 0: decode FP_TYPEFUNC {
2181 format FloatingPointOperate {
2182 #ifdef SS_COMPATIBLE_FP
2183 0x00: adds({{ Fc = Fa + Fb; }});
2184 0x01: subs({{ Fc = Fa - Fb; }});
2185 0x02: muls({{ Fc = Fa * Fb; }}, FloatMULT);
2186 0x03: divs({{ Fc = Fa / Fb; }}, FloatDIV);
2188 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
2189 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
2190 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMULT);
2191 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDIV);
2194 0x20: addt({{ Fc = Fa + Fb; }});
2195 0x21: subt({{ Fc = Fa - Fb; }});
2196 0x22: mult({{ Fc = Fa * Fb; }}, FloatMULT);
2197 0x23: divt({{ Fc = Fa / Fb; }}, FloatDIV);
2201 // Floating-point compare instructions must have the default
2202 // rounding mode, and may use the default trapping mode or
2203 // /SU. Both trapping modes are treated the same by M5; the
2204 // only difference on the real hardware (as far a I can tell)
2205 // is that without /SU you'd get an imprecise trap if you
2206 // tried to compare a NaN with something else (instead of an
2207 // "unordered" result).
2208 1: decode FP_FULLFUNC {
2209 format BasicOperateWithNopCheck {
2210 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
2212 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
2214 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
2216 0x0a4, 0x5a4: cmptun({{ // unordered
2217 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
2222 // The FP-to-integer and integer-to-FP conversion insts
2223 // require that FA be 31.
2225 31: decode FP_TYPEFUNC {
2226 format FloatingPointOperate {
2227 0x2f: cvttq({{ Fc.sq = (int64_t)rint(Fb); }});
2229 // The cvtts opcode is overloaded to be cvtst if the trap
2230 // mode is 2 or 6 (which are not valid otherwise)
2231 0x2c: decode FP_FULLFUNC {
2232 format BasicOperateWithNopCheck {
2233 // trap on denorm version "cvtst/s" is
2234 // simulated same as cvtst
2235 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
2237 default: cvtts({{ Fc.sf = Fb; }});
2240 // The trapping mode for integer-to-FP conversions
2241 // must be /SUI or nothing; /U and /SU are not
2242 // allowed. The full set of rounding modes are
2243 // supported though.
2244 0x3c: decode FP_TRAPMODE {
2245 0,7: cvtqs({{ Fc.sf = Fb.sq; }});
2247 0x3e: decode FP_TRAPMODE {
2248 0,7: cvtqt({{ Fc = Fb.sq; }});
2256 0x17: decode FP_FULLFUNC {
2257 format BasicOperateWithNopCheck {
2259 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
2262 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2265 // We treat the precise & imprecise trapping versions of
2266 // cvtql identically.
2267 0x130, 0x530: cvtqlv({{
2268 // To avoid overflow, all the upper 32 bits must match
2269 // the sign bit of the lower 32. We code this as
2270 // checking the upper 33 bits for all 0s or all 1s.
2271 uint64_t sign_bits = Fb.uq<63:31>;
2272 if (sign_bits != 0 && sign_bits != mask(33))
2273 fault = Integer_Overflow_Fault;
2274 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
2277 0x020: cpys({{ // copy sign
2278 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
2280 0x021: cpysn({{ // copy sign negated
2281 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
2283 0x022: cpyse({{ // copy sign and exponent
2284 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
2287 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
2288 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
2289 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
2290 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
2291 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
2292 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
2294 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
2295 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
2299 // miscellaneous mem-format ops
2300 0x18: decode MEMFUNC {
2311 format MiscPrefetch {
2312 0xf800: wh64({{ EA = Rb; }},
2313 {{ memAccessObj->writeHint(EA, 64); }},
2314 IsMemRef, IsStore, WrPort);
2317 format BasicOperate {
2318 0xc000: rpcc({{ Ra = curTick; }});
2322 format BasicOperate {
2324 Ra = xc->regs.intrflag;
2325 xc->regs.intrflag = 0;
2328 Ra = xc->regs.intrflag;
2329 xc->regs.intrflag = 1;
2341 0x00: CallPal::call_pal({{
2342 // check to see if simulator wants to do something special
2343 // on this PAL call (including maybe suppress it)
2344 bool dopal = xc->simPalCheck(palFunc);
2346 Annotate::Callpal(xc, palFunc);
2349 if (!xc->misspeculating()) {
2350 AlphaISA::swap_palshadow(&xc->regs, true);
2352 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
2353 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
2357 0x00: decode PALFUNC {
2358 format EmulatedCallPal {
2360 if (!xc->misspeculating())
2361 SimExit("halt instruction encountered");
2363 0x83: callsys({{ xc->syscall(); }});
2364 // Read uniq reg into ABI return value register (r0)
2365 0x9e: rduniq({{ R0 = Runiq; }});
2366 // Write uniq reg with value from ABI arg register (r16)
2367 0x9f: wruniq({{ Runiq = R16; }});
2373 format HwLoadStore {
2374 0x1b: decode HW_LDST_QUAD {
2375 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
2376 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
2379 0x1f: decode HW_LDST_COND {
2380 0: decode HW_LDST_QUAD {
2381 0: hw_st({{ EA = (Rb + disp) & ~3; }},
2382 {{ Mem.ul = Ra<31:0>; }}, L);
2383 1: hw_st({{ EA = (Rb + disp) & ~7; }},
2384 {{ Mem.uq = Ra.uq; }}, Q);
2387 1: FailUnimpl::hw_st_cond();
2391 format BasicOperate {
2392 0x1e: hw_rei({{ xc->hwrei(); }});
2394 // M5 special opcodes use the reserved 0x01 opcode space
2395 0x01: decode M5FUNC {
2397 if (!xc->misspeculating()) {
2399 xc->kernelStats.arm();
2403 if (!xc->misspeculating()) {
2404 Annotate::QUIESCE(xc);
2405 xc->setStatus(ExecContext::Suspended);
2406 xc->kernelStats.quiesce();
2410 if (!xc->misspeculating()) {
2411 Annotate::BeginInterval(xc);
2412 xc->kernelStats.ivlb();
2416 if (!xc->misspeculating())
2417 Annotate::EndInterval(xc);
2420 if (!xc->misspeculating())
2421 SimExit("m5_exit instruction encountered");
2423 0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
2425 if (!xc->misspeculating())
2426 Statistics::reset();
2433 // this instruction is only valid in PAL mode
2434 if (!PC_PAL(xc->regs.pc)) {
2435 fault = Unimplemented_Opcode_Fault;
2438 Ra = xc->readIpr(ipr_index, fault);
2442 // this instruction is only valid in PAL mode
2443 if (!PC_PAL(xc->regs.pc)) {
2444 fault = Unimplemented_Opcode_Fault;
2447 xc->setIpr(ipr_index, Ra);
2448 if (traceData) { traceData->setData(Ra); }