arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  31
  32 namespace LittleEndianGuest {}
  33 using namespace LittleEndianGuest;
  34
  35 //#include "arch/alpha/faults.hh"
  36 #include "base/misc.hh"
  37 #include "config/full_system.hh"
  38 #include "sim/host.hh"
  39 #include "sim/faults.hh"
  40
  41 class ExecContext;
  42 class FastCPU;
  43 class FullCPU;
  44 class Checkpoint;
  45
  46 #define TARGET_ALPHA
  47
  48 class StaticInst;
  49 class StaticInstPtr;
  50
  51 namespace EV5 {
  52 int DTB_ASN_ASN(uint64_t reg);
  53 int ITB_ASN_ASN(uint64_t reg);
  54 }
  55
  56 namespace AlphaISA
  57 {
  58
  59     typedef uint32_t MachInst;
  60 //    typedef uint64_t Addr;
  61     typedef uint8_t  RegIndex;
  62
  63     enum {
  64         MemoryEnd = 0xffffffffffffffffULL,
  65
  66         NumIntRegs = 32,
  67         NumFloatRegs = 32,
  68         // @todo: Figure out what this number really should be.
  69         NumMiscRegs = 32,
  70
  71         MaxRegsOfAnyType = 32,
  72         // Static instruction parameters
  73         MaxInstSrcRegs = 3,
  74         MaxInstDestRegs = 2,
  75
  76         // semantically meaningful register indices
  77         ZeroReg = 31,   // architecturally meaningful
  78         // the rest of these depend on the ABI
  79         StackPointerReg = 30,
  80         GlobalPointerReg = 29,
  81         ProcedureValueReg = 27,
  82         ReturnAddressReg = 26,
  83         ReturnValueReg = 0,
  84         FramePointerReg = 15,
  85         ArgumentReg0 = 16,
  86         ArgumentReg1 = 17,
  87         ArgumentReg2 = 18,
  88         ArgumentReg3 = 19,
  89         ArgumentReg4 = 20,
  90         ArgumentReg5 = 21,
  91
  92         LogVMPageSize = 13,     // 8K bytes
  93         VMPageSize = (1 << LogVMPageSize),
  94
  95         BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
  96
  97         WordBytes = 4,
  98         HalfwordBytes = 2,
  99         ByteBytes = 1,
 100         DepNA = 0,
 101     };
 102
 103     // These enumerate all the registers for dependence tracking.
 104     enum DependenceTags {
 105         // 0..31 are the integer regs 0..31
 106         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
 107         FP_Base_DepTag = 32,
 108         Ctrl_Base_DepTag = 64,
 109         Fpcr_DepTag = 64,               // floating point control register
 110         Uniq_DepTag = 65,
 111         Lock_Flag_DepTag = 66,
 112         Lock_Addr_DepTag = 67,
 113         IPR_Base_DepTag = 68
 114     };
 115
 116     typedef uint64_t IntReg;
 117     typedef IntReg IntRegFile[NumIntRegs];
 118
 119     // floating point register file entry type
 120     typedef union {
 121         uint64_t q;
 122         double d;
 123     } FloatReg;
 124
 125     typedef union {
 126         uint64_t q[NumFloatRegs];       // integer qword view
 127         double d[NumFloatRegs];         // double-precision floating point view
 128     } FloatRegFile;
 129
 130 extern const Addr PageShift;
 131 extern const Addr PageBytes;
 132 extern const Addr PageMask;
 133 extern const Addr PageOffset;
 134
 135 #if FULL_SYSTEM
 136
 137     typedef uint64_t InternalProcReg;
 138
 139 #include "arch/alpha/isa_fullsys_traits.hh"
 140
 141 #else
 142     enum {
 143         NumInternalProcRegs = 0
 144     };
 145 #endif
 146
 147     // control register file contents
 148     typedef uint64_t MiscReg;
 149     class MiscRegFile {
 150       protected:
 151         uint64_t        fpcr;           // floating point condition codes
 152         uint64_t        uniq;           // process-unique register
 153         bool            lock_flag;      // lock flag for LL/SC
 154         Addr            lock_addr;      // lock address for LL/SC
 155
 156       public:
 157         MiscReg readReg(int misc_reg);
 158
 159         MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
 160
 161         Fault setReg(int misc_reg, const MiscReg &val);
 162
 163         Fault setRegWithEffect(int misc_reg, const MiscReg &val,
 164                                ExecContext *xc);
 165
 166 #if FULL_SYSTEM
 167         void clearIprs();
 168
 169       protected:
 170         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 171
 172       private:
 173         MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
 174
 175         Fault setIpr(int idx, uint64_t val, ExecContext *xc);
 176 #endif
 177         friend class RegFile;
 178     };
 179
 180     enum {
 181         TotalNumRegs =
 182         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
 183     };
 184
 185     enum {
 186         TotalDataRegs = NumIntRegs + NumFloatRegs
 187     };
 188
 189     typedef union {
 190         IntReg  intreg;
 191         FloatReg   fpreg;
 192         MiscReg ctrlreg;
 193     } AnyReg;
 194
 195     struct RegFile {
 196         IntRegFile intRegFile;          // (signed) integer register file
 197         FloatRegFile floatRegFile;      // floating point register file
 198         MiscRegFile miscRegs;           // control register file
 199         Addr pc;                        // program counter
 200         Addr npc;                       // next-cycle program counter
 201 #if FULL_SYSTEM
 202         IntReg palregs[NumIntRegs];     // PAL shadow registers
 203         int intrflag;                   // interrupt flag
 204         bool pal_shadow;                // using pal_shadow registers
 205         inline int instAsid()
 206         { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
 207         inline int dataAsid()
 208         { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
 209 #endif // FULL_SYSTEM
 210
 211         void serialize(std::ostream &os);
 212         void unserialize(Checkpoint *cp, const std::string &section);
 213     };
 214
 215     StaticInstPtr decodeInst(MachInst);
 216
 217     // return a no-op instruction... used for instruction fetch faults
 218     extern const MachInst NoopMachInst;
 219
 220     enum annotes {
 221         ANNOTE_NONE = 0,
 222         // An impossible number for instruction annotations
 223         ITOUCH_ANNOTE = 0xffffffff,
 224     };
 225
 226     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
 227         panic("register classification not implemented");
 228         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
 229     }
 230
 231     static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
 232         panic("register classification not implemented");
 233         return (reg >= 9 && reg <= 15);
 234     }
 235
 236     static inline bool isCallerSaveFloatRegister(unsigned int reg) {
 237         panic("register classification not implemented");
 238         return false;
 239     }
 240
 241     static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
 242         panic("register classification not implemented");
 243         return false;
 244     }
 245
 246     static inline Addr alignAddress(const Addr &addr,
 247                                          unsigned int nbytes) {
 248         return (addr & ~(nbytes - 1));
 249     }
 250
 251     // Instruction address compression hooks
 252     static inline Addr realPCToFetchPC(const Addr &addr) {
 253         return addr;
 254     }
 255
 256     static inline Addr fetchPCToRealPC(const Addr &addr) {
 257         return addr;
 258     }
 259
 260     // the size of "fetched" instructions (not necessarily the size
 261     // of real instructions for PISA)
 262     static inline size_t fetchInstSize() {
 263         return sizeof(MachInst);
 264     }
 265
 266     static inline MachInst makeRegisterCopy(int dest, int src) {
 267         panic("makeRegisterCopy not implemented");
 268         return 0;
 269     }
 270
 271     // Machine operations
 272
 273     void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 274                                int regnum);
 275
 276     void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 277                                   int regnum);
 278
 279 #if 0
 280     static void serializeSpecialRegs(const Serializable::Proxy &proxy,
 281                                      const RegFile &regs);
 282
 283     static void unserializeSpecialRegs(const IniFile *db,
 284                                        const std::string &category,
 285                                        ConfigNode *node,
 286                                        RegFile &regs);
 287 #endif
 288
 289     /**
 290      * Function to insure ISA semantics about 0 registers.
 291      * @param xc The execution context.
 292      */
 293     template <class XC>
 294     void zeroRegisters(XC *xc);
 295
 296
 297 //typedef AlphaISA TheISA;
 298
 299 //typedef TheISA::MachInst MachInst;
 300 //typedef TheISA::Addr Addr;
 301 //typedef TheISA::RegIndex RegIndex;
 302 //typedef TheISA::IntReg IntReg;
 303 //typedef TheISA::IntRegFile IntRegFile;
 304 //typedef TheISA::FloatReg FloatReg;
 305 //typedef TheISA::FloatRegFile FloatRegFile;
 306 //typedef TheISA::MiscReg MiscReg;
 307 //typedef TheISA::MiscRegFile MiscRegFile;
 308 //typedef TheISA::AnyReg AnyReg;
 309 //typedef TheISA::RegFile RegFile;
 310
 311 //const int NumIntRegs   = TheISA::NumIntRegs;
 312 //const int NumFloatRegs = TheISA::NumFloatRegs;
 313 //const int NumMiscRegs  = TheISA::NumMiscRegs;
 314 //const int TotalNumRegs = TheISA::TotalNumRegs;
 315 //const int VMPageSize   = TheISA::VMPageSize;
 316 //const int LogVMPageSize   = TheISA::LogVMPageSize;
 317 //const int ZeroReg = TheISA::ZeroReg;
 318 //const int StackPointerReg = TheISA::StackPointerReg;
 319 //const int GlobalPointerReg = TheISA::GlobalPointerReg;
 320 //const int ReturnAddressReg = TheISA::ReturnAddressReg;
 321 //const int ReturnValueReg = TheISA::ReturnValueReg;
 322 //const int ArgumentReg0 = TheISA::ArgumentReg0;
 323 //const int ArgumentReg1 = TheISA::ArgumentReg1;
 324 //const int ArgumentReg2 = TheISA::ArgumentReg2;
 325 //const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
 326 const Addr MaxAddr = (Addr)-1;
 327 };
 328
 329 #if !FULL_SYSTEM
 330 class SyscallReturn {
 331         public:
 332            template <class T>
 333            SyscallReturn(T v, bool s)
 334            {
 335                retval = (uint64_t)v;
 336                success = s;
 337            }
 338
 339            template <class T>
 340            SyscallReturn(T v)
 341            {
 342                success = (v >= 0);
 343                retval = (uint64_t)v;
 344            }
 345
 346            ~SyscallReturn() {}
 347
 348            SyscallReturn& operator=(const SyscallReturn& s) {
 349                retval = s.retval;
 350                success = s.success;
 351                return *this;
 352            }
 353
 354            bool successful() { return success; }
 355            uint64_t value() { return retval; }
 356
 357
 358        private:
 359            uint64_t retval;
 360            bool success;
 361 };
 362
 363 #endif
 364
 365
 366 #if FULL_SYSTEM
 367 //typedef TheISA::InternalProcReg InternalProcReg;
 368 //const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 369 //const int NumInterruptLevels = TheISA::NumInterruptLevels;
 370
 371 #include "arch/alpha/ev5.hh"
 372 #endif
 373
 374 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__