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29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
32 #include "arch/alpha/faults.hh"
33 #include "base/misc.hh"
34 #include "sim/host.hh"
42 template <class ISA> class StaticInst;
43 template <class ISA> class StaticInstPtr;
46 int DTB_ASN_ASN(uint64_t reg);
47 int ITB_ASN_ASN(uint64_t reg);
54 typedef uint32_t MachInst;
55 typedef uint64_t Addr;
56 typedef uint8_t RegIndex;
59 MemoryEnd = 0xffffffffffffffffULL,
65 MaxRegsOfAnyType = 32,
66 // Static instruction parameters
70 // semantically meaningful register indices
71 ZeroReg = 31, // architecturally meaningful
72 // the rest of these depend on the ABI
74 GlobalPointerReg = 29,
75 ReturnAddressReg = 26,
84 LogVMPageSize = 13, // 8K bytes
85 VMPageSize = (1 << LogVMPageSize),
87 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
95 // These enumerate all the registers for dependence tracking.
97 // 0..31 are the integer regs 0..31
98 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
100 Ctrl_Base_DepTag = 64,
101 Fpcr_DepTag = 64, // floating point control register
106 typedef uint64_t IntReg;
107 typedef IntReg IntRegFile[NumIntRegs];
109 // floating point register file entry type
116 uint64_t q[NumFloatRegs]; // integer qword view
117 double d[NumFloatRegs]; // double-precision floating point view
120 // control register file contents
121 typedef uint64_t MiscReg;
123 uint64_t fpcr; // floating point condition codes
124 uint64_t uniq; // process-unique register
125 bool lock_flag; // lock flag for LL/SC
126 Addr lock_addr; // lock address for LL/SC
129 static const Addr PageShift = 13;
130 static const Addr PageBytes = ULL(1) << PageShift;
131 static const Addr PageMask = ~(PageBytes - 1);
132 static const Addr PageOffset = PageBytes - 1;
136 typedef uint64_t InternalProcReg;
138 #include "arch/alpha/isa_fullsys_traits.hh"
142 NumInternalProcRegs = 0
148 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
152 TotalDataRegs = NumIntRegs + NumFloatRegs
162 IntRegFile intRegFile; // (signed) integer register file
163 FloatRegFile floatRegFile; // floating point register file
164 MiscRegFile miscRegs; // control register file
165 Addr pc; // program counter
166 Addr npc; // next-cycle program counter
168 IntReg palregs[NumIntRegs]; // PAL shadow registers
169 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
170 int intrflag; // interrupt flag
171 bool pal_shadow; // using pal_shadow registers
172 inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
173 inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
174 #endif // FULL_SYSTEM
176 void serialize(std::ostream &os);
177 void unserialize(Checkpoint *cp, const std::string §ion);
180 static StaticInstPtr<AlphaISA> decodeInst(MachInst);
182 // return a no-op instruction... used for instruction fetch faults
183 static const MachInst NoopMachInst;
187 // An impossible number for instruction annotations
188 ITOUCH_ANNOTE = 0xffffffff,
191 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
192 panic("register classification not implemented");
193 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
196 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
197 panic("register classification not implemented");
198 return (reg >= 9 && reg <= 15);
201 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
202 panic("register classification not implemented");
206 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
207 panic("register classification not implemented");
211 static inline Addr alignAddress(const Addr &addr,
212 unsigned int nbytes) {
213 return (addr & ~(nbytes - 1));
216 // Instruction address compression hooks
217 static inline Addr realPCToFetchPC(const Addr &addr) {
221 static inline Addr fetchPCToRealPC(const Addr &addr) {
225 // the size of "fetched" instructions (not necessarily the size
226 // of real instructions for PISA)
227 static inline size_t fetchInstSize() {
228 return sizeof(MachInst);
231 static inline MachInst makeRegisterCopy(int dest, int src) {
232 panic("makeRegisterCopy not implemented");
236 // Machine operations
238 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
241 static void restoreMachineReg(RegFile ®s, const AnyReg ®,
245 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
246 const RegFile ®s);
248 static void unserializeSpecialRegs(const IniFile *db,
249 const std::string &category,
255 * Function to insure ISA semantics about 0 registers.
256 * @param xc The execution context.
259 static void zeroRegisters(XC *xc);
263 typedef AlphaISA TheISA;
265 typedef TheISA::MachInst MachInst;
266 typedef TheISA::Addr Addr;
267 typedef TheISA::RegIndex RegIndex;
268 typedef TheISA::IntReg IntReg;
269 typedef TheISA::IntRegFile IntRegFile;
270 typedef TheISA::FloatReg FloatReg;
271 typedef TheISA::FloatRegFile FloatRegFile;
272 typedef TheISA::MiscReg MiscReg;
273 typedef TheISA::MiscRegFile MiscRegFile;
274 typedef TheISA::AnyReg AnyReg;
275 typedef TheISA::RegFile RegFile;
277 const int NumIntRegs = TheISA::NumIntRegs;
278 const int NumFloatRegs = TheISA::NumFloatRegs;
279 const int NumMiscRegs = TheISA::NumMiscRegs;
280 const int TotalNumRegs = TheISA::TotalNumRegs;
281 const int VMPageSize = TheISA::VMPageSize;
282 const int LogVMPageSize = TheISA::LogVMPageSize;
283 const int ZeroReg = TheISA::ZeroReg;
284 const int StackPointerReg = TheISA::StackPointerReg;
285 const int GlobalPointerReg = TheISA::GlobalPointerReg;
286 const int ReturnAddressReg = TheISA::ReturnAddressReg;
287 const int ReturnValueReg = TheISA::ReturnValueReg;
288 const int ArgumentReg0 = TheISA::ArgumentReg0;
289 const int ArgumentReg1 = TheISA::ArgumentReg1;
290 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
291 const int MaxAddr = (Addr)-1;
294 class SyscallReturn {
297 SyscallReturn(T v, bool s)
299 retval = (uint64_t)v;
307 retval = (uint64_t)v;
312 SyscallReturn& operator=(const SyscallReturn& s) {
318 bool successful() { return success; }
319 uint64_t value() { return retval; }
331 typedef TheISA::InternalProcReg InternalProcReg;
332 const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
333 const int NumInterruptLevels = TheISA::NumInterruptLevels;
335 #include "arch/alpha/ev5.hh"
338 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__