arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  31
  32 #include "arch/alpha/faults.hh"
  33 #include "base/misc.hh"
  34 #include "sim/host.hh"
  35
  36 class FastCPU;
  37 class FullCPU;
  38 class Checkpoint;
  39
  40 #define TARGET_ALPHA
  41
  42 template <class ISA> class StaticInst;
  43 template <class ISA> class StaticInstPtr;
  44
  45 namespace EV5 {
  46 int DTB_ASN_ASN(uint64_t reg);
  47 int ITB_ASN_ASN(uint64_t reg);
  48 }
  49
  50 class AlphaISA
  51 {
  52   public:
  53
  54     typedef uint32_t MachInst;
  55     typedef uint64_t Addr;
  56     typedef uint8_t  RegIndex;
  57
  58     enum {
  59         MemoryEnd = 0xffffffffffffffffULL,
  60
  61         NumIntRegs = 32,
  62         NumFloatRegs = 32,
  63         NumMiscRegs = 32,
  64
  65         MaxRegsOfAnyType = 32,
  66         // Static instruction parameters
  67         MaxInstSrcRegs = 3,
  68         MaxInstDestRegs = 2,
  69
  70         // semantically meaningful register indices
  71         ZeroReg = 31,   // architecturally meaningful
  72         // the rest of these depend on the ABI
  73         StackPointerReg = 30,
  74         GlobalPointerReg = 29,
  75         ReturnAddressReg = 26,
  76         ReturnValueReg = 0,
  77         ArgumentReg0 = 16,
  78         ArgumentReg1 = 17,
  79         ArgumentReg2 = 18,
  80         ArgumentReg3 = 19,
  81         ArgumentReg4 = 20,
  82         ArgumentReg5 = 21,
  83
  84         LogVMPageSize = 13,     // 8K bytes
  85         VMPageSize = (1 << LogVMPageSize),
  86
  87         BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
  88
  89         WordBytes = 4,
  90         HalfwordBytes = 2,
  91         ByteBytes = 1,
  92         DepNA = 0,
  93     };
  94
  95     // These enumerate all the registers for dependence tracking.
  96     enum DependenceTags {
  97         // 0..31 are the integer regs 0..31
  98         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
  99         FP_Base_DepTag = 32,
 100         Ctrl_Base_DepTag = 64,
 101         Fpcr_DepTag = 64,               // floating point control register
 102         Uniq_DepTag = 65,
 103         IPR_Base_DepTag = 66
 104     };
 105
 106     typedef uint64_t IntReg;
 107     typedef IntReg IntRegFile[NumIntRegs];
 108
 109     // floating point register file entry type
 110     typedef union {
 111         uint64_t q;
 112         double d;
 113     } FloatReg;
 114
 115     typedef union {
 116         uint64_t q[NumFloatRegs];       // integer qword view
 117         double d[NumFloatRegs];         // double-precision floating point view
 118     } FloatRegFile;
 119
 120     // control register file contents
 121     typedef uint64_t MiscReg;
 122     typedef struct {
 123         uint64_t        fpcr;           // floating point condition codes
 124         uint64_t        uniq;           // process-unique register
 125         bool            lock_flag;      // lock flag for LL/SC
 126         Addr            lock_addr;      // lock address for LL/SC
 127     } MiscRegFile;
 128
 129 static const Addr PageShift = 13;
 130 static const Addr PageBytes = ULL(1) << PageShift;
 131 static const Addr PageMask = ~(PageBytes - 1);
 132 static const Addr PageOffset = PageBytes - 1;
 133
 134 #ifdef FULL_SYSTEM
 135
 136     typedef uint64_t InternalProcReg;
 137
 138 #include "arch/alpha/isa_fullsys_traits.hh"
 139
 140 #else
 141     enum {
 142         NumInternalProcRegs = 0
 143     };
 144 #endif
 145
 146     enum {
 147         TotalNumRegs =
 148         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
 149     };
 150
 151     enum {
 152         TotalDataRegs = NumIntRegs + NumFloatRegs
 153     };
 154
 155     typedef union {
 156         IntReg  intreg;
 157         FloatReg   fpreg;
 158         MiscReg ctrlreg;
 159     } AnyReg;
 160
 161     struct RegFile {
 162         IntRegFile intRegFile;          // (signed) integer register file
 163         FloatRegFile floatRegFile;      // floating point register file
 164         MiscRegFile miscRegs;           // control register file
 165         Addr pc;                        // program counter
 166         Addr npc;                       // next-cycle program counter
 167 #ifdef FULL_SYSTEM
 168         IntReg palregs[NumIntRegs];     // PAL shadow registers
 169         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
 170         int intrflag;                   // interrupt flag
 171         bool pal_shadow;                // using pal_shadow registers
 172         inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
 173         inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
 174 #endif // FULL_SYSTEM
 175
 176         void serialize(std::ostream &os);
 177         void unserialize(Checkpoint *cp, const std::string &section);
 178     };
 179
 180     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
 181
 182     // return a no-op instruction... used for instruction fetch faults
 183     static const MachInst NoopMachInst;
 184
 185     enum annotes {
 186         ANNOTE_NONE = 0,
 187         // An impossible number for instruction annotations
 188         ITOUCH_ANNOTE = 0xffffffff,
 189     };
 190
 191     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
 192         panic("register classification not implemented");
 193         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
 194     }
 195
 196     static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
 197         panic("register classification not implemented");
 198         return (reg >= 9 && reg <= 15);
 199     }
 200
 201     static inline bool isCallerSaveFloatRegister(unsigned int reg) {
 202         panic("register classification not implemented");
 203         return false;
 204     }
 205
 206     static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
 207         panic("register classification not implemented");
 208         return false;
 209     }
 210
 211     static inline Addr alignAddress(const Addr &addr,
 212                                          unsigned int nbytes) {
 213         return (addr & ~(nbytes - 1));
 214     }
 215
 216     // Instruction address compression hooks
 217     static inline Addr realPCToFetchPC(const Addr &addr) {
 218         return addr;
 219     }
 220
 221     static inline Addr fetchPCToRealPC(const Addr &addr) {
 222         return addr;
 223     }
 224
 225     // the size of "fetched" instructions (not necessarily the size
 226     // of real instructions for PISA)
 227     static inline size_t fetchInstSize() {
 228         return sizeof(MachInst);
 229     }
 230
 231     static inline MachInst makeRegisterCopy(int dest, int src) {
 232         panic("makeRegisterCopy not implemented");
 233         return 0;
 234     }
 235
 236     // Machine operations
 237
 238     static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 239                                int regnum);
 240
 241     static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 242                                   int regnum);
 243
 244 #if 0
 245     static void serializeSpecialRegs(const Serializable::Proxy &proxy,
 246                                      const RegFile &regs);
 247
 248     static void unserializeSpecialRegs(const IniFile *db,
 249                                        const std::string &category,
 250                                        ConfigNode *node,
 251                                        RegFile &regs);
 252 #endif
 253
 254     /**
 255      * Function to insure ISA semantics about 0 registers.
 256      * @param xc The execution context.
 257      */
 258     template <class XC>
 259     static void zeroRegisters(XC *xc);
 260 };
 261
 262
 263 typedef AlphaISA TheISA;
 264
 265 typedef TheISA::MachInst MachInst;
 266 typedef TheISA::Addr Addr;
 267 typedef TheISA::RegIndex RegIndex;
 268 typedef TheISA::IntReg IntReg;
 269 typedef TheISA::IntRegFile IntRegFile;
 270 typedef TheISA::FloatReg FloatReg;
 271 typedef TheISA::FloatRegFile FloatRegFile;
 272 typedef TheISA::MiscReg MiscReg;
 273 typedef TheISA::MiscRegFile MiscRegFile;
 274 typedef TheISA::AnyReg AnyReg;
 275 typedef TheISA::RegFile RegFile;
 276
 277 const int NumIntRegs   = TheISA::NumIntRegs;
 278 const int NumFloatRegs = TheISA::NumFloatRegs;
 279 const int NumMiscRegs  = TheISA::NumMiscRegs;
 280 const int TotalNumRegs = TheISA::TotalNumRegs;
 281 const int VMPageSize   = TheISA::VMPageSize;
 282 const int LogVMPageSize   = TheISA::LogVMPageSize;
 283 const int ZeroReg = TheISA::ZeroReg;
 284 const int StackPointerReg = TheISA::StackPointerReg;
 285 const int GlobalPointerReg = TheISA::GlobalPointerReg;
 286 const int ReturnAddressReg = TheISA::ReturnAddressReg;
 287 const int ReturnValueReg = TheISA::ReturnValueReg;
 288 const int ArgumentReg0 = TheISA::ArgumentReg0;
 289 const int ArgumentReg1 = TheISA::ArgumentReg1;
 290 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
 291 const int MaxAddr = (Addr)-1;
 292
 293 #ifndef FULL_SYSTEM
 294 class SyscallReturn {
 295         public:
 296            template <class T>
 297            SyscallReturn(T v, bool s)
 298            {
 299                retval = (uint64_t)v;
 300                success = s;
 301            }
 302
 303            template <class T>
 304            SyscallReturn(T v)
 305            {
 306                success = (v >= 0);
 307                retval = (uint64_t)v;
 308            }
 309
 310            ~SyscallReturn() {}
 311
 312            SyscallReturn& operator=(const SyscallReturn& s) {
 313                retval = s.retval;
 314                success = s.success;
 315                return *this;
 316            }
 317
 318            bool successful() { return success; }
 319            uint64_t value() { return retval; }
 320
 321
 322        private:
 323            uint64_t retval;
 324            bool success;
 325 };
 326
 327 #endif
 328
 329
 330 #ifdef FULL_SYSTEM
 331 typedef TheISA::InternalProcReg InternalProcReg;
 332 const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 333 const int NumInterruptLevels = TheISA::NumInterruptLevels;
 334
 335 #include "arch/alpha/ev5.hh"
 336 #endif
 337
 338 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__