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29 #ifndef __ISA_TRAITS_HH__
30 #define __ISA_TRAITS_HH__
32 #include "arch/alpha/faults.hh"
33 #include "base/misc.hh"
34 #include "sim/host.hh"
42 template <class ISA> class StaticInst;
43 template <class ISA> class StaticInstPtr;
49 typedef uint32_t MachInst;
50 typedef uint64_t Addr;
51 typedef uint8_t RegIndex;
54 MemoryEnd = 0xffffffffffffffffULL,
60 MaxRegsOfAnyType = 32,
61 // Static instruction parameters
65 // semantically meaningful register indices
66 ZeroReg = 31, // architecturally meaningful
67 // the rest of these depend on the ABI
69 GlobalPointerReg = 29,
70 ReturnAddressReg = 26,
79 LogVMPageSize = 13, // 8K bytes
80 VMPageSize = (1 << LogVMPageSize),
82 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
90 // These enumerate all the registers for dependence tracking.
92 // 0..31 are the integer regs 0..31
93 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
95 Ctrl_Base_DepTag = 64,
96 Fpcr_DepTag = 64, // floating point control register
101 typedef uint64_t IntReg;
102 typedef IntReg IntRegFile[NumIntRegs];
104 // floating point register file entry type
111 uint64_t q[NumFloatRegs]; // integer qword view
112 double d[NumFloatRegs]; // double-precision floating point view
115 // control register file contents
116 typedef uint64_t MiscReg;
118 uint64_t fpcr; // floating point condition codes
119 uint64_t uniq; // process-unique register
120 bool lock_flag; // lock flag for LL/SC
121 Addr lock_addr; // lock address for LL/SC
124 static const Addr PageShift = 13;
125 static const Addr PageBytes = ULL(1) << PageShift;
126 static const Addr PageMask = ~(PageBytes - 1);
127 static const Addr PageOffset = PageBytes - 1;
131 typedef uint64_t InternalProcReg;
133 #include "arch/alpha/isa_fullsys_traits.hh"
137 NumInternalProcRegs = 0
143 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
153 IntRegFile intRegFile; // (signed) integer register file
154 FloatRegFile floatRegFile; // floating point register file
155 MiscRegFile miscRegs; // control register file
156 Addr pc; // program counter
157 Addr npc; // next-cycle program counter
159 IntReg palregs[NumIntRegs]; // PAL shadow registers
160 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
161 int intrflag; // interrupt flag
162 bool pal_shadow; // using pal_shadow registers
163 #endif // FULL_SYSTEM
165 void serialize(std::ostream &os);
166 void unserialize(Checkpoint *cp, const std::string §ion);
169 static StaticInstPtr<AlphaISA> decodeInst(MachInst);
173 // An impossible number for instruction annotations
174 ITOUCH_ANNOTE = 0xffffffff,
177 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
178 panic("register classification not implemented");
179 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
182 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
183 panic("register classification not implemented");
184 return (reg >= 9 && reg <= 15);
187 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
188 panic("register classification not implemented");
192 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
193 panic("register classification not implemented");
197 static inline Addr alignAddress(const Addr &addr,
198 unsigned int nbytes) {
199 return (addr & ~(nbytes - 1));
202 // Instruction address compression hooks
203 static inline Addr realPCToFetchPC(const Addr &addr) {
207 static inline Addr fetchPCToRealPC(const Addr &addr) {
211 // the size of "fetched" instructions (not necessarily the size
212 // of real instructions for PISA)
213 static inline size_t fetchInstSize() {
214 return sizeof(MachInst);
217 static inline MachInst makeRegisterCopy(int dest, int src) {
218 panic("makeRegisterCopy not implemented");
222 // Machine operations
224 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
227 static void restoreMachineReg(RegFile ®s, const AnyReg ®,
231 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
232 const RegFile ®s);
234 static void unserializeSpecialRegs(const IniFile *db,
235 const std::string &category,
241 * Function to insure ISA semantics about 0 registers.
242 * @param xc The execution context.
245 static void zeroRegisters(XC *xc);
249 typedef AlphaISA TheISA;
251 typedef TheISA::MachInst MachInst;
252 typedef TheISA::Addr Addr;
253 typedef TheISA::RegIndex RegIndex;
254 typedef TheISA::IntReg IntReg;
255 typedef TheISA::IntRegFile IntRegFile;
256 typedef TheISA::FloatReg FloatReg;
257 typedef TheISA::FloatRegFile FloatRegFile;
258 typedef TheISA::MiscReg MiscReg;
259 typedef TheISA::MiscRegFile MiscRegFile;
260 typedef TheISA::AnyReg AnyReg;
261 typedef TheISA::RegFile RegFile;
263 const int NumIntRegs = TheISA::NumIntRegs;
264 const int NumFloatRegs = TheISA::NumFloatRegs;
265 const int NumMiscRegs = TheISA::NumMiscRegs;
266 const int TotalNumRegs = TheISA::TotalNumRegs;
267 const int VMPageSize = TheISA::VMPageSize;
268 const int LogVMPageSize = TheISA::LogVMPageSize;
269 const int ZeroReg = TheISA::ZeroReg;
270 const int StackPointerReg = TheISA::StackPointerReg;
271 const int GlobalPointerReg = TheISA::GlobalPointerReg;
272 const int ReturnAddressReg = TheISA::ReturnAddressReg;
273 const int ReturnValueReg = TheISA::ReturnValueReg;
274 const int ArgumentReg0 = TheISA::ArgumentReg0;
275 const int ArgumentReg1 = TheISA::ArgumentReg1;
276 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
277 const int MaxAddr = (Addr)-1;
280 typedef TheISA::InternalProcReg InternalProcReg;
281 const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
282 const int NumInterruptLevels = TheISA::NumInterruptLevels;
284 // more stuff that should be imported here, but I'm too tired to do it
286 #include "arch/alpha/ev5.hh"
289 #endif // __ALPHA_ISA_H__