arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  31
  32 namespace LittleEndianGuest {}
  33 using namespace LittleEndianGuest;
  34
  35 //#include "arch/alpha/faults.hh"
  36 #include "base/misc.hh"
  37 #include "config/full_system.hh"
  38 #include "sim/host.hh"
  39 #include "sim/faults.hh"
  40
  41 class FastCPU;
  42 class FullCPU;
  43 class Checkpoint;
  44
  45 #define TARGET_ALPHA
  46
  47 template <class ISA> class StaticInst;
  48 template <class ISA> class StaticInstPtr;
  49
  50 namespace EV5 {
  51 int DTB_ASN_ASN(uint64_t reg);
  52 int ITB_ASN_ASN(uint64_t reg);
  53 }
  54
  55 class AlphaISA
  56 {
  57   public:
  58
  59     typedef uint32_t MachInst;
  60     typedef uint64_t Addr;
  61     typedef uint8_t  RegIndex;
  62
  63     enum {
  64         MemoryEnd = 0xffffffffffffffffULL,
  65
  66         NumIntRegs = 32,
  67         NumFloatRegs = 32,
  68         NumMiscRegs = 32,
  69
  70         MaxRegsOfAnyType = 32,
  71         // Static instruction parameters
  72         MaxInstSrcRegs = 3,
  73         MaxInstDestRegs = 2,
  74
  75         // semantically meaningful register indices
  76         ZeroReg = 31,   // architecturally meaningful
  77         // the rest of these depend on the ABI
  78         StackPointerReg = 30,
  79         GlobalPointerReg = 29,
  80         ProcedureValueReg = 27,
  81         ReturnAddressReg = 26,
  82         ReturnValueReg = 0,
  83         FramePointerReg = 15,
  84         ArgumentReg0 = 16,
  85         ArgumentReg1 = 17,
  86         ArgumentReg2 = 18,
  87         ArgumentReg3 = 19,
  88         ArgumentReg4 = 20,
  89         ArgumentReg5 = 21,
  90
  91         LogVMPageSize = 13,     // 8K bytes
  92         VMPageSize = (1 << LogVMPageSize),
  93
  94         BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
  95
  96         WordBytes = 4,
  97         HalfwordBytes = 2,
  98         ByteBytes = 1,
  99         DepNA = 0,
 100     };
 101
 102     // These enumerate all the registers for dependence tracking.
 103     enum DependenceTags {
 104         // 0..31 are the integer regs 0..31
 105         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
 106         FP_Base_DepTag = 32,
 107         Ctrl_Base_DepTag = 64,
 108         Fpcr_DepTag = 64,               // floating point control register
 109         Uniq_DepTag = 65,
 110         IPR_Base_DepTag = 66
 111     };
 112
 113     typedef uint64_t IntReg;
 114     typedef IntReg IntRegFile[NumIntRegs];
 115
 116     // floating point register file entry type
 117     typedef union {
 118         uint64_t q;
 119         double d;
 120     } FloatReg;
 121
 122     typedef union {
 123         uint64_t q[NumFloatRegs];       // integer qword view
 124         double d[NumFloatRegs];         // double-precision floating point view
 125     } FloatRegFile;
 126
 127     // control register file contents
 128     typedef uint64_t MiscReg;
 129     typedef struct {
 130         uint64_t        fpcr;           // floating point condition codes
 131         uint64_t        uniq;           // process-unique register
 132         bool            lock_flag;      // lock flag for LL/SC
 133         Addr            lock_addr;      // lock address for LL/SC
 134     } MiscRegFile;
 135
 136 static const Addr PageShift = 13;
 137 static const Addr PageBytes = ULL(1) << PageShift;
 138 static const Addr PageMask = ~(PageBytes - 1);
 139 static const Addr PageOffset = PageBytes - 1;
 140
 141 #if FULL_SYSTEM
 142
 143     typedef uint64_t InternalProcReg;
 144
 145 #include "arch/alpha/isa_fullsys_traits.hh"
 146
 147 #else
 148     enum {
 149         NumInternalProcRegs = 0
 150     };
 151 #endif
 152
 153     enum {
 154         TotalNumRegs =
 155         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
 156     };
 157
 158     enum {
 159         TotalDataRegs = NumIntRegs + NumFloatRegs
 160     };
 161
 162     typedef union {
 163         IntReg  intreg;
 164         FloatReg   fpreg;
 165         MiscReg ctrlreg;
 166     } AnyReg;
 167
 168     struct RegFile {
 169         IntRegFile intRegFile;          // (signed) integer register file
 170         FloatRegFile floatRegFile;      // floating point register file
 171         MiscRegFile miscRegs;           // control register file
 172         Addr pc;                        // program counter
 173         Addr npc;                       // next-cycle program counter
 174 #if FULL_SYSTEM
 175         IntReg palregs[NumIntRegs];     // PAL shadow registers
 176         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
 177         int intrflag;                   // interrupt flag
 178         bool pal_shadow;                // using pal_shadow registers
 179         inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
 180         inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
 181 #endif // FULL_SYSTEM
 182
 183         void serialize(std::ostream &os);
 184         void unserialize(Checkpoint *cp, const std::string &section);
 185     };
 186
 187     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
 188
 189     // return a no-op instruction... used for instruction fetch faults
 190     static const MachInst NoopMachInst;
 191
 192     enum annotes {
 193         ANNOTE_NONE = 0,
 194         // An impossible number for instruction annotations
 195         ITOUCH_ANNOTE = 0xffffffff,
 196     };
 197
 198     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
 199         panic("register classification not implemented");
 200         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
 201     }
 202
 203     static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
 204         panic("register classification not implemented");
 205         return (reg >= 9 && reg <= 15);
 206     }
 207
 208     static inline bool isCallerSaveFloatRegister(unsigned int reg) {
 209         panic("register classification not implemented");
 210         return false;
 211     }
 212
 213     static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
 214         panic("register classification not implemented");
 215         return false;
 216     }
 217
 218     static inline Addr alignAddress(const Addr &addr,
 219                                          unsigned int nbytes) {
 220         return (addr & ~(nbytes - 1));
 221     }
 222
 223     // Instruction address compression hooks
 224     static inline Addr realPCToFetchPC(const Addr &addr) {
 225         return addr;
 226     }
 227
 228     static inline Addr fetchPCToRealPC(const Addr &addr) {
 229         return addr;
 230     }
 231
 232     // the size of "fetched" instructions (not necessarily the size
 233     // of real instructions for PISA)
 234     static inline size_t fetchInstSize() {
 235         return sizeof(MachInst);
 236     }
 237
 238     static inline MachInst makeRegisterCopy(int dest, int src) {
 239         panic("makeRegisterCopy not implemented");
 240         return 0;
 241     }
 242
 243     // Machine operations
 244
 245     static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 246                                int regnum);
 247
 248     static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 249                                   int regnum);
 250
 251 #if 0
 252     static void serializeSpecialRegs(const Serializable::Proxy &proxy,
 253                                      const RegFile &regs);
 254
 255     static void unserializeSpecialRegs(const IniFile *db,
 256                                        const std::string &category,
 257                                        ConfigNode *node,
 258                                        RegFile &regs);
 259 #endif
 260
 261     /**
 262      * Function to insure ISA semantics about 0 registers.
 263      * @param xc The execution context.
 264      */
 265     template <class XC>
 266     static void zeroRegisters(XC *xc);
 267 };
 268
 269
 270 typedef AlphaISA TheISA;
 271
 272 typedef TheISA::MachInst MachInst;
 273 typedef TheISA::Addr Addr;
 274 typedef TheISA::RegIndex RegIndex;
 275 typedef TheISA::IntReg IntReg;
 276 typedef TheISA::IntRegFile IntRegFile;
 277 typedef TheISA::FloatReg FloatReg;
 278 typedef TheISA::FloatRegFile FloatRegFile;
 279 typedef TheISA::MiscReg MiscReg;
 280 typedef TheISA::MiscRegFile MiscRegFile;
 281 typedef TheISA::AnyReg AnyReg;
 282 typedef TheISA::RegFile RegFile;
 283
 284 const int NumIntRegs   = TheISA::NumIntRegs;
 285 const int NumFloatRegs = TheISA::NumFloatRegs;
 286 const int NumMiscRegs  = TheISA::NumMiscRegs;
 287 const int TotalNumRegs = TheISA::TotalNumRegs;
 288 const int VMPageSize   = TheISA::VMPageSize;
 289 const int LogVMPageSize   = TheISA::LogVMPageSize;
 290 const int ZeroReg = TheISA::ZeroReg;
 291 const int StackPointerReg = TheISA::StackPointerReg;
 292 const int GlobalPointerReg = TheISA::GlobalPointerReg;
 293 const int ReturnAddressReg = TheISA::ReturnAddressReg;
 294 const int ReturnValueReg = TheISA::ReturnValueReg;
 295 const int ArgumentReg0 = TheISA::ArgumentReg0;
 296 const int ArgumentReg1 = TheISA::ArgumentReg1;
 297 const int ArgumentReg2 = TheISA::ArgumentReg2;
 298 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
 299 const int MaxAddr = (Addr)-1;
 300
 301 #if !FULL_SYSTEM
 302 class SyscallReturn {
 303         public:
 304            template <class T>
 305            SyscallReturn(T v, bool s)
 306            {
 307                retval = (uint64_t)v;
 308                success = s;
 309            }
 310
 311            template <class T>
 312            SyscallReturn(T v)
 313            {
 314                success = (v >= 0);
 315                retval = (uint64_t)v;
 316            }
 317
 318            ~SyscallReturn() {}
 319
 320            SyscallReturn& operator=(const SyscallReturn& s) {
 321                retval = s.retval;
 322                success = s.success;
 323                return *this;
 324            }
 325
 326            bool successful() { return success; }
 327            uint64_t value() { return retval; }
 328
 329
 330        private:
 331            uint64_t retval;
 332            bool success;
 333 };
 334
 335 #endif
 336
 337
 338 #if FULL_SYSTEM
 339 typedef TheISA::InternalProcReg InternalProcReg;
 340 const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 341 const int NumInterruptLevels = TheISA::NumInterruptLevels;
 342
 343 #include "arch/alpha/ev5.hh"
 344 #endif
 345
 346 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__