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29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
32 namespace LittleEndianGuest {}
33 using namespace LittleEndianGuest;
35 //#include "arch/alpha/faults.hh"
36 #include "base/misc.hh"
37 #include "config/full_system.hh"
38 #include "sim/host.hh"
39 #include "sim/faults.hh"
52 int DTB_ASN_ASN(uint64_t reg);
53 int ITB_ASN_ASN(uint64_t reg);
59 typedef uint32_t MachInst;
60 typedef uint8_t RegIndex;
63 MemoryEnd = 0xffffffffffffffffULL,
67 // @todo: Figure out what this number really should be.
70 MaxRegsOfAnyType = 32,
71 // Static instruction parameters
75 // semantically meaningful register indices
76 ZeroReg = 31, // architecturally meaningful
77 // the rest of these depend on the ABI
79 GlobalPointerReg = 29,
80 ProcedureValueReg = 27,
81 ReturnAddressReg = 26,
91 LogVMPageSize = 13, // 8K bytes
92 VMPageSize = (1 << LogVMPageSize),
94 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
102 // These enumerate all the registers for dependence tracking.
103 enum DependenceTags {
104 // 0..31 are the integer regs 0..31
105 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
107 Ctrl_Base_DepTag = 64,
108 Fpcr_DepTag = 64, // floating point control register
110 Lock_Flag_DepTag = 66,
111 Lock_Addr_DepTag = 67,
115 typedef uint64_t IntReg;
116 typedef IntReg IntRegFile[NumIntRegs];
118 // floating point register file entry type
125 uint64_t q[NumFloatRegs]; // integer qword view
126 double d[NumFloatRegs]; // double-precision floating point view
129 extern const Addr PageShift;
130 extern const Addr PageBytes;
131 extern const Addr PageMask;
132 extern const Addr PageOffset;
136 typedef uint64_t InternalProcReg;
138 #include "arch/alpha/isa_fullsys_traits.hh"
142 NumInternalProcRegs = 0
146 // control register file contents
147 typedef uint64_t MiscReg;
150 uint64_t fpcr; // floating point condition codes
151 uint64_t uniq; // process-unique register
152 bool lock_flag; // lock flag for LL/SC
153 Addr lock_addr; // lock address for LL/SC
156 MiscReg readReg(int misc_reg);
158 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
160 Fault setReg(int misc_reg, const MiscReg &val);
162 Fault setRegWithEffect(int misc_reg, const MiscReg &val,
169 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
172 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
174 Fault setIpr(int idx, uint64_t val, ExecContext *xc);
176 friend class RegFile;
181 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
185 TotalDataRegs = NumIntRegs + NumFloatRegs
195 IntRegFile intRegFile; // (signed) integer register file
196 FloatRegFile floatRegFile; // floating point register file
197 MiscRegFile miscRegs; // control register file
198 Addr pc; // program counter
199 Addr npc; // next-cycle program counter
201 IntReg palregs[NumIntRegs]; // PAL shadow registers
202 int intrflag; // interrupt flag
203 bool pal_shadow; // using pal_shadow registers
204 inline int instAsid()
205 { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
206 inline int dataAsid()
207 { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
208 #endif // FULL_SYSTEM
210 void serialize(std::ostream &os);
211 void unserialize(Checkpoint *cp, const std::string §ion);
214 StaticInstPtr decodeInst(MachInst);
216 // return a no-op instruction... used for instruction fetch faults
217 extern const MachInst NoopMachInst;
221 // An impossible number for instruction annotations
222 ITOUCH_ANNOTE = 0xffffffff,
225 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
226 panic("register classification not implemented");
227 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
230 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
231 panic("register classification not implemented");
232 return (reg >= 9 && reg <= 15);
235 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
236 panic("register classification not implemented");
240 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
241 panic("register classification not implemented");
245 static inline Addr alignAddress(const Addr &addr,
246 unsigned int nbytes) {
247 return (addr & ~(nbytes - 1));
250 // Instruction address compression hooks
251 static inline Addr realPCToFetchPC(const Addr &addr) {
255 static inline Addr fetchPCToRealPC(const Addr &addr) {
259 // the size of "fetched" instructions (not necessarily the size
260 // of real instructions for PISA)
261 static inline size_t fetchInstSize() {
262 return sizeof(MachInst);
265 static inline MachInst makeRegisterCopy(int dest, int src) {
266 panic("makeRegisterCopy not implemented");
270 // Machine operations
272 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
275 void restoreMachineReg(RegFile ®s, const AnyReg ®,
279 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
280 const RegFile ®s);
282 static void unserializeSpecialRegs(const IniFile *db,
283 const std::string &category,
289 * Function to insure ISA semantics about 0 registers.
290 * @param xc The execution context.
293 void zeroRegisters(XC *xc);
296 //typedef AlphaISA TheISA;
298 //typedef TheISA::MachInst MachInst;
299 //typedef TheISA::Addr Addr;
300 //typedef TheISA::RegIndex RegIndex;
301 //typedef TheISA::IntReg IntReg;
302 //typedef TheISA::IntRegFile IntRegFile;
303 //typedef TheISA::FloatReg FloatReg;
304 //typedef TheISA::FloatRegFile FloatRegFile;
305 //typedef TheISA::MiscReg MiscReg;
306 //typedef TheISA::MiscRegFile MiscRegFile;
307 //typedef TheISA::AnyReg AnyReg;
308 //typedef TheISA::RegFile RegFile;
310 //const int NumIntRegs = TheISA::NumIntRegs;
311 //const int NumFloatRegs = TheISA::NumFloatRegs;
312 //const int NumMiscRegs = TheISA::NumMiscRegs;
313 //const int TotalNumRegs = TheISA::TotalNumRegs;
314 //const int VMPageSize = TheISA::VMPageSize;
315 //const int LogVMPageSize = TheISA::LogVMPageSize;
316 //const int ZeroReg = TheISA::ZeroReg;
317 //const int StackPointerReg = TheISA::StackPointerReg;
318 //const int GlobalPointerReg = TheISA::GlobalPointerReg;
319 //const int ReturnAddressReg = TheISA::ReturnAddressReg;
320 //const int ReturnValueReg = TheISA::ReturnValueReg;
321 //const int ArgumentReg0 = TheISA::ArgumentReg0;
322 //const int ArgumentReg1 = TheISA::ArgumentReg1;
323 //const int ArgumentReg2 = TheISA::ArgumentReg2;
324 //const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
325 const Addr MaxAddr = (Addr)-1;
329 class SyscallReturn {
332 SyscallReturn(T v, bool s)
334 retval = (uint64_t)v;
342 retval = (uint64_t)v;
347 SyscallReturn& operator=(const SyscallReturn& s) {
353 bool successful() { return success; }
354 uint64_t value() { return retval; }
366 //typedef TheISA::InternalProcReg InternalProcReg;
367 //const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
368 //const int NumInterruptLevels = TheISA::NumInterruptLevels;
370 #include "arch/alpha/ev5.hh"
373 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__