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29 #ifndef __ISA_TRAITS_HH__
30 #define __ISA_TRAITS_HH__
32 #include "sim/host.hh"
33 #include "targetarch/faults.hh"
34 #include "base/misc.hh"
41 template <class ISA> class StaticInst;
42 template <class ISA> class StaticInstPtr;
48 typedef uint32_t MachInst;
49 typedef uint64_t Addr;
50 typedef uint8_t RegIndex;
53 MemoryEnd = 0xffffffffffffffffULL,
59 MaxRegsOfAnyType = 32,
60 // Static instruction parameters
64 // semantically meaningful register indices
65 ZeroReg = 31, // architecturally meaningful
66 // the rest of these depend on the ABI
68 GlobalPointerReg = 29,
69 ReturnAddressReg = 26,
78 LogVMPageSize = 13, // 8K bytes
79 VMPageSize = (1 << LogVMPageSize),
81 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
89 // These enumerate all the registers for dependence tracking.
91 // 0..31 are the integer regs 0..31
92 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
94 Ctrl_Base_DepTag = 64,
95 Fpcr_DepTag = 64, // floating point control register
100 typedef uint64_t IntReg;
101 typedef IntReg IntRegFile[NumIntRegs];
103 // floating point register file entry type
110 uint64_t q[NumFloatRegs]; // integer qword view
111 double d[NumFloatRegs]; // double-precision floating point view
114 // control register file contents
115 typedef uint64_t MiscReg;
117 uint64_t fpcr; // floating point condition codes
118 uint64_t uniq; // process-unique register
119 bool lock_flag; // lock flag for LL/SC
120 Addr lock_addr; // lock address for LL/SC
125 typedef uint64_t InternalProcReg;
127 #include "targetarch/isa_fullsys_traits.hh"
131 NumInternalProcRegs = 0
137 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
147 IntRegFile intRegFile; // (signed) integer register file
148 FloatRegFile floatRegFile; // floating point register file
149 MiscRegFile miscRegs; // control register file
150 Addr pc; // program counter
151 Addr npc; // next-cycle program counter
153 IntReg palregs[NumIntRegs]; // PAL shadow registers
154 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
155 int intrlock; // interrupt register lock flag
156 int intrflag; // interrupt flag
157 bool pal_shadow; // using pal_shadow registers
158 #endif // FULL_SYSTEM
159 // Are these architectural, or just for convenience?
160 uint8_t opcode, ra; // current instruction details (for intr's)
163 static StaticInstPtr<AlphaISA> decodeInst(MachInst);
167 // An impossible number for instruction annotations
168 ITOUCH_ANNOTE = 0xffffffff,
171 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
172 panic("register classification not implemented");
173 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
176 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
177 panic("register classification not implemented");
178 return (reg >= 9 && reg <= 15);
181 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
182 panic("register classification not implemented");
186 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
187 panic("register classification not implemented");
191 static inline Addr alignAddress(const Addr &addr,
192 unsigned int nbytes) {
193 return (addr & ~(nbytes - 1));
196 // Instruction address compression hooks
197 static inline Addr realPCToFetchPC(const Addr &addr) {
201 static inline Addr fetchPCToRealPC(const Addr &addr) {
205 // the size of "fetched" instructions (not necessarily the size
206 // of real instructions for PISA)
207 static inline size_t fetchInstSize() {
208 return sizeof(MachInst);
211 static inline MachInst makeRegisterCopy(int dest, int src) {
212 panic("makeRegisterCopy not implemented");
216 // Machine operations
218 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
221 static void restoreMachineReg(RegFile ®s, const AnyReg ®,
225 static void serializeSpecialRegs(const Serializeable::Proxy &proxy,
226 const RegFile ®s);
228 static void unserializeSpecialRegs(IniFile &db,
229 const std::string &category,
236 typedef AlphaISA TheISA;
238 typedef TheISA::MachInst MachInst;
239 typedef TheISA::Addr Addr;
240 typedef TheISA::RegIndex RegIndex;
241 typedef TheISA::IntReg IntReg;
242 typedef TheISA::IntRegFile IntRegFile;
243 typedef TheISA::FloatReg FloatReg;
244 typedef TheISA::FloatRegFile FloatRegFile;
245 typedef TheISA::MiscReg MiscReg;
246 typedef TheISA::MiscRegFile MiscRegFile;
247 typedef TheISA::AnyReg AnyReg;
248 typedef TheISA::RegFile RegFile;
250 const int NumIntRegs = TheISA::NumIntRegs;
251 const int NumFloatRegs = TheISA::NumFloatRegs;
252 const int NumMiscRegs = TheISA::NumMiscRegs;
253 const int TotalNumRegs = TheISA::TotalNumRegs;
254 const int VMPageSize = TheISA::VMPageSize;
255 const int LogVMPageSize = TheISA::LogVMPageSize;
256 const int ZeroReg = TheISA::ZeroReg;
257 const int StackPointerReg = TheISA::StackPointerReg;
258 const int GlobalPointerReg = TheISA::GlobalPointerReg;
259 const int ReturnAddressReg = TheISA::ReturnAddressReg;
260 const int ReturnValueReg = TheISA::ReturnValueReg;
261 const int ArgumentReg0 = TheISA::ArgumentReg0;
262 const int ArgumentReg1 = TheISA::ArgumentReg1;
263 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
266 typedef TheISA::InternalProcReg InternalProcReg;
267 const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
268 const int NumInterruptLevels = TheISA::NumInterruptLevels;
270 // more stuff that should be imported here, but I'm too tired to do it
272 #include "targetarch/ev5.hh"
275 #endif // __ALPHA_ISA_H__