arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ISA_TRAITS_HH__
  30 #define __ISA_TRAITS_HH__
  31
  32 #include "sim/host.hh"
  33 #include "targetarch/faults.hh"
  34 #include "base/misc.hh"
  35
  36 class FastCPU;
  37 class FullCPU;
  38 class Checkpoint;
  39
  40 #define TARGET_ALPHA
  41
  42 template <class ISA> class StaticInst;
  43 template <class ISA> class StaticInstPtr;
  44
  45 class AlphaISA
  46 {
  47   public:
  48
  49     typedef uint32_t MachInst;
  50     typedef uint64_t Addr;
  51     typedef uint8_t  RegIndex;
  52
  53     enum {
  54         MemoryEnd = 0xffffffffffffffffULL,
  55
  56         NumIntRegs = 32,
  57         NumFloatRegs = 32,
  58         NumMiscRegs = 32,
  59
  60         MaxRegsOfAnyType = 32,
  61         // Static instruction parameters
  62         MaxInstSrcRegs = 3,
  63         MaxInstDestRegs = 2,
  64
  65         // semantically meaningful register indices
  66         ZeroReg = 31,   // architecturally meaningful
  67         // the rest of these depend on the ABI
  68         StackPointerReg = 30,
  69         GlobalPointerReg = 29,
  70         ReturnAddressReg = 26,
  71         ReturnValueReg = 0,
  72         ArgumentReg0 = 16,
  73         ArgumentReg1 = 17,
  74         ArgumentReg2 = 18,
  75         ArgumentReg3 = 19,
  76         ArgumentReg4 = 20,
  77         ArgumentReg5 = 21,
  78
  79         LogVMPageSize = 13,     // 8K bytes
  80         VMPageSize = (1 << LogVMPageSize),
  81
  82         BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
  83
  84         WordBytes = 4,
  85         HalfwordBytes = 2,
  86         ByteBytes = 1,
  87         DepNA = 0,
  88     };
  89
  90     // These enumerate all the registers for dependence tracking.
  91     enum DependenceTags {
  92         // 0..31 are the integer regs 0..31
  93         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
  94         FP_Base_DepTag = 32,
  95         Ctrl_Base_DepTag = 64,
  96         Fpcr_DepTag = 64,               // floating point control register
  97         Uniq_DepTag = 65,
  98         IPR_Base_DepTag = 66
  99     };
 100
 101     typedef uint64_t IntReg;
 102     typedef IntReg IntRegFile[NumIntRegs];
 103
 104     // floating point register file entry type
 105     typedef union {
 106         uint64_t q;
 107         double d;
 108     } FloatReg;
 109
 110     typedef union {
 111         uint64_t q[NumFloatRegs];       // integer qword view
 112         double d[NumFloatRegs];         // double-precision floating point view
 113     } FloatRegFile;
 114
 115     // control register file contents
 116     typedef uint64_t MiscReg;
 117     typedef struct {
 118         uint64_t        fpcr;           // floating point condition codes
 119         uint64_t        uniq;           // process-unique register
 120         bool            lock_flag;      // lock flag for LL/SC
 121         Addr            lock_addr;      // lock address for LL/SC
 122     } MiscRegFile;
 123
 124 #ifdef FULL_SYSTEM
 125
 126     typedef uint64_t InternalProcReg;
 127
 128 #include "targetarch/isa_fullsys_traits.hh"
 129
 130 #else
 131     enum {
 132         NumInternalProcRegs = 0
 133     };
 134 #endif
 135
 136     enum {
 137         TotalNumRegs =
 138         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
 139     };
 140
 141     typedef union {
 142         IntReg  intreg;
 143         FloatReg   fpreg;
 144         MiscReg ctrlreg;
 145     } AnyReg;
 146
 147     struct RegFile {
 148         IntRegFile intRegFile;          // (signed) integer register file
 149         FloatRegFile floatRegFile;      // floating point register file
 150         MiscRegFile miscRegs;           // control register file
 151         Addr pc;                        // program counter
 152         Addr npc;                       // next-cycle program counter
 153 #ifdef FULL_SYSTEM
 154         IntReg palregs[NumIntRegs];     // PAL shadow registers
 155         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
 156         int intrlock;                   // interrupt register lock flag
 157         int intrflag;                   // interrupt flag
 158         bool pal_shadow;                // using pal_shadow registers
 159 #endif // FULL_SYSTEM
 160
 161         void serialize(std::ostream &os);
 162         void unserialize(Checkpoint *cp, const std::string &section);
 163     };
 164
 165     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
 166
 167     enum annotes {
 168         ANNOTE_NONE = 0,
 169         // An impossible number for instruction annotations
 170         ITOUCH_ANNOTE = 0xffffffff,
 171     };
 172
 173     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
 174         panic("register classification not implemented");
 175         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
 176     }
 177
 178     static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
 179         panic("register classification not implemented");
 180         return (reg >= 9 && reg <= 15);
 181     }
 182
 183     static inline bool isCallerSaveFloatRegister(unsigned int reg) {
 184         panic("register classification not implemented");
 185         return false;
 186     }
 187
 188     static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
 189         panic("register classification not implemented");
 190         return false;
 191     }
 192
 193     static inline Addr alignAddress(const Addr &addr,
 194                                          unsigned int nbytes) {
 195         return (addr & ~(nbytes - 1));
 196     }
 197
 198     // Instruction address compression hooks
 199     static inline Addr realPCToFetchPC(const Addr &addr) {
 200         return addr;
 201     }
 202
 203     static inline Addr fetchPCToRealPC(const Addr &addr) {
 204         return addr;
 205     }
 206
 207     // the size of "fetched" instructions (not necessarily the size
 208     // of real instructions for PISA)
 209     static inline size_t fetchInstSize() {
 210         return sizeof(MachInst);
 211     }
 212
 213     static inline MachInst makeRegisterCopy(int dest, int src) {
 214         panic("makeRegisterCopy not implemented");
 215         return 0;
 216     }
 217
 218     // Machine operations
 219
 220     static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 221                                int regnum);
 222
 223     static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 224                                   int regnum);
 225
 226 #if 0
 227     static void serializeSpecialRegs(const Serializable::Proxy &proxy,
 228                                      const RegFile &regs);
 229
 230     static void unserializeSpecialRegs(const IniFile *db,
 231                                        const std::string &category,
 232                                        ConfigNode *node,
 233                                        RegFile &regs);
 234 #endif
 235
 236     /**
 237      * Function to insure ISA semantics about 0 registers.
 238      * @param xc The execution context.
 239      */
 240     template <class XC>
 241     static void zeroRegisters(XC *xc);
 242 };
 243
 244
 245 typedef AlphaISA TheISA;
 246
 247 typedef TheISA::MachInst MachInst;
 248 typedef TheISA::Addr Addr;
 249 typedef TheISA::RegIndex RegIndex;
 250 typedef TheISA::IntReg IntReg;
 251 typedef TheISA::IntRegFile IntRegFile;
 252 typedef TheISA::FloatReg FloatReg;
 253 typedef TheISA::FloatRegFile FloatRegFile;
 254 typedef TheISA::MiscReg MiscReg;
 255 typedef TheISA::MiscRegFile MiscRegFile;
 256 typedef TheISA::AnyReg AnyReg;
 257 typedef TheISA::RegFile RegFile;
 258
 259 const int NumIntRegs   = TheISA::NumIntRegs;
 260 const int NumFloatRegs = TheISA::NumFloatRegs;
 261 const int NumMiscRegs  = TheISA::NumMiscRegs;
 262 const int TotalNumRegs = TheISA::TotalNumRegs;
 263 const int VMPageSize   = TheISA::VMPageSize;
 264 const int LogVMPageSize   = TheISA::LogVMPageSize;
 265 const int ZeroReg = TheISA::ZeroReg;
 266 const int StackPointerReg = TheISA::StackPointerReg;
 267 const int GlobalPointerReg = TheISA::GlobalPointerReg;
 268 const int ReturnAddressReg = TheISA::ReturnAddressReg;
 269 const int ReturnValueReg = TheISA::ReturnValueReg;
 270 const int ArgumentReg0 = TheISA::ArgumentReg0;
 271 const int ArgumentReg1 = TheISA::ArgumentReg1;
 272 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
 273 const int MaxAddr = (Addr)-1;
 274
 275 #ifdef FULL_SYSTEM
 276 typedef TheISA::InternalProcReg InternalProcReg;
 277 const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 278 const int NumInterruptLevels = TheISA::NumInterruptLevels;
 279
 280 // more stuff that should be imported here, but I'm too tired to do it
 281 // right now...
 282 #include "targetarch/ev5.hh"
 283 #endif
 284
 285 #endif // __ALPHA_ISA_H__