arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  31
  32 #include "arch/alpha/faults.hh"
  33 #include "base/misc.hh"
  34 #include "config/full_system.hh"
  35 #include "sim/host.hh"
  36
  37 class FastCPU;
  38 class FullCPU;
  39 class Checkpoint;
  40
  41 #define TARGET_ALPHA
  42
  43 template <class ISA> class StaticInst;
  44 template <class ISA> class StaticInstPtr;
  45
  46 namespace EV5 {
  47 int DTB_ASN_ASN(uint64_t reg);
  48 int ITB_ASN_ASN(uint64_t reg);
  49 }
  50
  51 class AlphaISA
  52 {
  53   public:
  54
  55     typedef uint32_t MachInst;
  56     typedef uint64_t Addr;
  57     typedef uint8_t  RegIndex;
  58
  59     enum {
  60         MemoryEnd = 0xffffffffffffffffULL,
  61
  62         NumIntRegs = 32,
  63         NumFloatRegs = 32,
  64         NumMiscRegs = 32,
  65
  66         MaxRegsOfAnyType = 32,
  67         // Static instruction parameters
  68         MaxInstSrcRegs = 3,
  69         MaxInstDestRegs = 2,
  70
  71         // semantically meaningful register indices
  72         ZeroReg = 31,   // architecturally meaningful
  73         // the rest of these depend on the ABI
  74         StackPointerReg = 30,
  75         GlobalPointerReg = 29,
  76         ProcedureValueReg = 27,
  77         ReturnAddressReg = 26,
  78         ReturnValueReg = 0,
  79         FramePointerReg = 15,
  80         ArgumentReg0 = 16,
  81         ArgumentReg1 = 17,
  82         ArgumentReg2 = 18,
  83         ArgumentReg3 = 19,
  84         ArgumentReg4 = 20,
  85         ArgumentReg5 = 21,
  86
  87         LogVMPageSize = 13,     // 8K bytes
  88         VMPageSize = (1 << LogVMPageSize),
  89
  90         BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
  91
  92         WordBytes = 4,
  93         HalfwordBytes = 2,
  94         ByteBytes = 1,
  95         DepNA = 0,
  96     };
  97
  98     // These enumerate all the registers for dependence tracking.
  99     enum DependenceTags {
 100         // 0..31 are the integer regs 0..31
 101         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
 102         FP_Base_DepTag = 32,
 103         Ctrl_Base_DepTag = 64,
 104         Fpcr_DepTag = 64,               // floating point control register
 105         Uniq_DepTag = 65,
 106         IPR_Base_DepTag = 66
 107     };
 108
 109     typedef uint64_t IntReg;
 110     typedef IntReg IntRegFile[NumIntRegs];
 111
 112     // floating point register file entry type
 113     typedef union {
 114         uint64_t q;
 115         double d;
 116     } FloatReg;
 117
 118     typedef union {
 119         uint64_t q[NumFloatRegs];       // integer qword view
 120         double d[NumFloatRegs];         // double-precision floating point view
 121     } FloatRegFile;
 122
 123     // control register file contents
 124     typedef uint64_t MiscReg;
 125     typedef struct {
 126         uint64_t        fpcr;           // floating point condition codes
 127         uint64_t        uniq;           // process-unique register
 128         bool            lock_flag;      // lock flag for LL/SC
 129         Addr            lock_addr;      // lock address for LL/SC
 130     } MiscRegFile;
 131
 132 static const Addr PageShift = 13;
 133 static const Addr PageBytes = ULL(1) << PageShift;
 134 static const Addr PageMask = ~(PageBytes - 1);
 135 static const Addr PageOffset = PageBytes - 1;
 136
 137 #if FULL_SYSTEM
 138
 139     typedef uint64_t InternalProcReg;
 140
 141 #include "arch/alpha/isa_fullsys_traits.hh"
 142
 143 #else
 144     enum {
 145         NumInternalProcRegs = 0
 146     };
 147 #endif
 148
 149     enum {
 150         TotalNumRegs =
 151         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
 152     };
 153
 154     enum {
 155         TotalDataRegs = NumIntRegs + NumFloatRegs
 156     };
 157
 158     typedef union {
 159         IntReg  intreg;
 160         FloatReg   fpreg;
 161         MiscReg ctrlreg;
 162     } AnyReg;
 163
 164     struct RegFile {
 165         IntRegFile intRegFile;          // (signed) integer register file
 166         FloatRegFile floatRegFile;      // floating point register file
 167         MiscRegFile miscRegs;           // control register file
 168         Addr pc;                        // program counter
 169         Addr npc;                       // next-cycle program counter
 170 #if FULL_SYSTEM
 171         IntReg palregs[NumIntRegs];     // PAL shadow registers
 172         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
 173         int intrflag;                   // interrupt flag
 174         bool pal_shadow;                // using pal_shadow registers
 175         inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
 176         inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
 177 #endif // FULL_SYSTEM
 178
 179         void serialize(std::ostream &os);
 180         void unserialize(Checkpoint *cp, const std::string &section);
 181     };
 182
 183     static StaticInstPtr<AlphaISA> decodeInst(MachInst);
 184
 185     // return a no-op instruction... used for instruction fetch faults
 186     static const MachInst NoopMachInst;
 187
 188     enum annotes {
 189         ANNOTE_NONE = 0,
 190         // An impossible number for instruction annotations
 191         ITOUCH_ANNOTE = 0xffffffff,
 192     };
 193
 194     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
 195         panic("register classification not implemented");
 196         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
 197     }
 198
 199     static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
 200         panic("register classification not implemented");
 201         return (reg >= 9 && reg <= 15);
 202     }
 203
 204     static inline bool isCallerSaveFloatRegister(unsigned int reg) {
 205         panic("register classification not implemented");
 206         return false;
 207     }
 208
 209     static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
 210         panic("register classification not implemented");
 211         return false;
 212     }
 213
 214     static inline Addr alignAddress(const Addr &addr,
 215                                          unsigned int nbytes) {
 216         return (addr & ~(nbytes - 1));
 217     }
 218
 219     // Instruction address compression hooks
 220     static inline Addr realPCToFetchPC(const Addr &addr) {
 221         return addr;
 222     }
 223
 224     static inline Addr fetchPCToRealPC(const Addr &addr) {
 225         return addr;
 226     }
 227
 228     // the size of "fetched" instructions (not necessarily the size
 229     // of real instructions for PISA)
 230     static inline size_t fetchInstSize() {
 231         return sizeof(MachInst);
 232     }
 233
 234     static inline MachInst makeRegisterCopy(int dest, int src) {
 235         panic("makeRegisterCopy not implemented");
 236         return 0;
 237     }
 238
 239     // Machine operations
 240
 241     static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 242                                int regnum);
 243
 244     static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 245                                   int regnum);
 246
 247 #if 0
 248     static void serializeSpecialRegs(const Serializable::Proxy &proxy,
 249                                      const RegFile &regs);
 250
 251     static void unserializeSpecialRegs(const IniFile *db,
 252                                        const std::string &category,
 253                                        ConfigNode *node,
 254                                        RegFile &regs);
 255 #endif
 256
 257     /**
 258      * Function to insure ISA semantics about 0 registers.
 259      * @param xc The execution context.
 260      */
 261     template <class XC>
 262     static void zeroRegisters(XC *xc);
 263 };
 264
 265
 266 typedef AlphaISA TheISA;
 267
 268 typedef TheISA::MachInst MachInst;
 269 typedef TheISA::Addr Addr;
 270 typedef TheISA::RegIndex RegIndex;
 271 typedef TheISA::IntReg IntReg;
 272 typedef TheISA::IntRegFile IntRegFile;
 273 typedef TheISA::FloatReg FloatReg;
 274 typedef TheISA::FloatRegFile FloatRegFile;
 275 typedef TheISA::MiscReg MiscReg;
 276 typedef TheISA::MiscRegFile MiscRegFile;
 277 typedef TheISA::AnyReg AnyReg;
 278 typedef TheISA::RegFile RegFile;
 279
 280 const int NumIntRegs   = TheISA::NumIntRegs;
 281 const int NumFloatRegs = TheISA::NumFloatRegs;
 282 const int NumMiscRegs  = TheISA::NumMiscRegs;
 283 const int TotalNumRegs = TheISA::TotalNumRegs;
 284 const int VMPageSize   = TheISA::VMPageSize;
 285 const int LogVMPageSize   = TheISA::LogVMPageSize;
 286 const int ZeroReg = TheISA::ZeroReg;
 287 const int StackPointerReg = TheISA::StackPointerReg;
 288 const int GlobalPointerReg = TheISA::GlobalPointerReg;
 289 const int ReturnAddressReg = TheISA::ReturnAddressReg;
 290 const int ReturnValueReg = TheISA::ReturnValueReg;
 291 const int ArgumentReg0 = TheISA::ArgumentReg0;
 292 const int ArgumentReg1 = TheISA::ArgumentReg1;
 293 const int ArgumentReg2 = TheISA::ArgumentReg2;
 294 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
 295 const int MaxAddr = (Addr)-1;
 296
 297 #if !FULL_SYSTEM
 298 class SyscallReturn {
 299         public:
 300            template <class T>
 301            SyscallReturn(T v, bool s)
 302            {
 303                retval = (uint64_t)v;
 304                success = s;
 305            }
 306
 307            template <class T>
 308            SyscallReturn(T v)
 309            {
 310                success = (v >= 0);
 311                retval = (uint64_t)v;
 312            }
 313
 314            ~SyscallReturn() {}
 315
 316            SyscallReturn& operator=(const SyscallReturn& s) {
 317                retval = s.retval;
 318                success = s.success;
 319                return *this;
 320            }
 321
 322            bool successful() { return success; }
 323            uint64_t value() { return retval; }
 324
 325
 326        private:
 327            uint64_t retval;
 328            bool success;
 329 };
 330
 331 #endif
 332
 333
 334 #if FULL_SYSTEM
 335 typedef TheISA::InternalProcReg InternalProcReg;
 336 const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 337 const int NumInterruptLevels = TheISA::NumInterruptLevels;
 338
 339 #include "arch/alpha/ev5.hh"
 340 #endif
 341
 342 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__