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29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
32 namespace LittleEndianGuest {}
33 using namespace LittleEndianGuest;
35 #include "arch/alpha/faults.hh"
36 #include "base/misc.hh"
37 #include "config/full_system.hh"
38 #include "sim/host.hh"
46 template <class ISA> class StaticInst;
47 template <class ISA> class StaticInstPtr;
50 int DTB_ASN_ASN(uint64_t reg);
51 int ITB_ASN_ASN(uint64_t reg);
58 typedef uint32_t MachInst;
59 typedef uint64_t Addr;
60 typedef uint8_t RegIndex;
63 MemoryEnd = 0xffffffffffffffffULL,
69 MaxRegsOfAnyType = 32,
70 // Static instruction parameters
74 // semantically meaningful register indices
75 ZeroReg = 31, // architecturally meaningful
76 // the rest of these depend on the ABI
78 GlobalPointerReg = 29,
79 ProcedureValueReg = 27,
80 ReturnAddressReg = 26,
90 LogVMPageSize = 13, // 8K bytes
91 VMPageSize = (1 << LogVMPageSize),
93 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
101 // These enumerate all the registers for dependence tracking.
102 enum DependenceTags {
103 // 0..31 are the integer regs 0..31
104 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
106 Ctrl_Base_DepTag = 64,
107 Fpcr_DepTag = 64, // floating point control register
112 typedef uint64_t IntReg;
113 typedef IntReg IntRegFile[NumIntRegs];
115 // floating point register file entry type
122 uint64_t q[NumFloatRegs]; // integer qword view
123 double d[NumFloatRegs]; // double-precision floating point view
126 // control register file contents
127 typedef uint64_t MiscReg;
129 uint64_t fpcr; // floating point condition codes
130 uint64_t uniq; // process-unique register
131 bool lock_flag; // lock flag for LL/SC
132 Addr lock_addr; // lock address for LL/SC
135 static const Addr PageShift = 13;
136 static const Addr PageBytes = ULL(1) << PageShift;
137 static const Addr PageMask = ~(PageBytes - 1);
138 static const Addr PageOffset = PageBytes - 1;
142 typedef uint64_t InternalProcReg;
144 #include "arch/alpha/isa_fullsys_traits.hh"
148 NumInternalProcRegs = 0
154 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
158 TotalDataRegs = NumIntRegs + NumFloatRegs
168 IntRegFile intRegFile; // (signed) integer register file
169 FloatRegFile floatRegFile; // floating point register file
170 MiscRegFile miscRegs; // control register file
171 Addr pc; // program counter
172 Addr npc; // next-cycle program counter
174 IntReg palregs[NumIntRegs]; // PAL shadow registers
175 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
176 int intrflag; // interrupt flag
177 bool pal_shadow; // using pal_shadow registers
178 inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
179 inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
180 #endif // FULL_SYSTEM
182 void serialize(std::ostream &os);
183 void unserialize(Checkpoint *cp, const std::string §ion);
186 static StaticInstPtr<AlphaISA> decodeInst(MachInst);
188 // return a no-op instruction... used for instruction fetch faults
189 static const MachInst NoopMachInst;
193 // An impossible number for instruction annotations
194 ITOUCH_ANNOTE = 0xffffffff,
197 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
198 panic("register classification not implemented");
199 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
202 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
203 panic("register classification not implemented");
204 return (reg >= 9 && reg <= 15);
207 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
208 panic("register classification not implemented");
212 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
213 panic("register classification not implemented");
217 static inline Addr alignAddress(const Addr &addr,
218 unsigned int nbytes) {
219 return (addr & ~(nbytes - 1));
222 // Instruction address compression hooks
223 static inline Addr realPCToFetchPC(const Addr &addr) {
227 static inline Addr fetchPCToRealPC(const Addr &addr) {
231 // the size of "fetched" instructions (not necessarily the size
232 // of real instructions for PISA)
233 static inline size_t fetchInstSize() {
234 return sizeof(MachInst);
237 static inline MachInst makeRegisterCopy(int dest, int src) {
238 panic("makeRegisterCopy not implemented");
242 // Machine operations
244 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
247 static void restoreMachineReg(RegFile ®s, const AnyReg ®,
251 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
252 const RegFile ®s);
254 static void unserializeSpecialRegs(const IniFile *db,
255 const std::string &category,
261 * Function to insure ISA semantics about 0 registers.
262 * @param xc The execution context.
265 static void zeroRegisters(XC *xc);
269 typedef AlphaISA TheISA;
271 typedef TheISA::MachInst MachInst;
272 typedef TheISA::Addr Addr;
273 typedef TheISA::RegIndex RegIndex;
274 typedef TheISA::IntReg IntReg;
275 typedef TheISA::IntRegFile IntRegFile;
276 typedef TheISA::FloatReg FloatReg;
277 typedef TheISA::FloatRegFile FloatRegFile;
278 typedef TheISA::MiscReg MiscReg;
279 typedef TheISA::MiscRegFile MiscRegFile;
280 typedef TheISA::AnyReg AnyReg;
281 typedef TheISA::RegFile RegFile;
283 const int NumIntRegs = TheISA::NumIntRegs;
284 const int NumFloatRegs = TheISA::NumFloatRegs;
285 const int NumMiscRegs = TheISA::NumMiscRegs;
286 const int TotalNumRegs = TheISA::TotalNumRegs;
287 const int VMPageSize = TheISA::VMPageSize;
288 const int LogVMPageSize = TheISA::LogVMPageSize;
289 const int ZeroReg = TheISA::ZeroReg;
290 const int StackPointerReg = TheISA::StackPointerReg;
291 const int GlobalPointerReg = TheISA::GlobalPointerReg;
292 const int ReturnAddressReg = TheISA::ReturnAddressReg;
293 const int ReturnValueReg = TheISA::ReturnValueReg;
294 const int ArgumentReg0 = TheISA::ArgumentReg0;
295 const int ArgumentReg1 = TheISA::ArgumentReg1;
296 const int ArgumentReg2 = TheISA::ArgumentReg2;
297 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
298 const int MaxAddr = (Addr)-1;
301 class SyscallReturn {
304 SyscallReturn(T v, bool s)
306 retval = (uint64_t)v;
314 retval = (uint64_t)v;
319 SyscallReturn& operator=(const SyscallReturn& s) {
325 bool successful() { return success; }
326 uint64_t value() { return retval; }
338 typedef TheISA::InternalProcReg InternalProcReg;
339 const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
340 const int NumInterruptLevels = TheISA::NumInterruptLevels;
342 #include "arch/alpha/ev5.hh"
345 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__