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29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
32 #include "arch/alpha/faults.hh"
33 #include "base/misc.hh"
34 #include "config/full_system.hh"
35 #include "sim/host.hh"
43 template <class ISA> class StaticInst;
44 template <class ISA> class StaticInstPtr;
47 int DTB_ASN_ASN(uint64_t reg);
48 int ITB_ASN_ASN(uint64_t reg);
55 typedef uint32_t MachInst;
56 typedef uint64_t Addr;
57 typedef uint8_t RegIndex;
60 MemoryEnd = 0xffffffffffffffffULL,
66 MaxRegsOfAnyType = 32,
67 // Static instruction parameters
71 // semantically meaningful register indices
72 ZeroReg = 31, // architecturally meaningful
73 // the rest of these depend on the ABI
75 GlobalPointerReg = 29,
76 ProcedureValueReg = 27,
77 ReturnAddressReg = 26,
87 LogVMPageSize = 13, // 8K bytes
88 VMPageSize = (1 << LogVMPageSize),
90 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
98 // These enumerate all the registers for dependence tracking.
100 // 0..31 are the integer regs 0..31
101 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
103 Ctrl_Base_DepTag = 64,
104 Fpcr_DepTag = 64, // floating point control register
109 typedef uint64_t IntReg;
110 typedef IntReg IntRegFile[NumIntRegs];
112 // floating point register file entry type
119 uint64_t q[NumFloatRegs]; // integer qword view
120 double d[NumFloatRegs]; // double-precision floating point view
123 // control register file contents
124 typedef uint64_t MiscReg;
126 uint64_t fpcr; // floating point condition codes
127 uint64_t uniq; // process-unique register
128 bool lock_flag; // lock flag for LL/SC
129 Addr lock_addr; // lock address for LL/SC
132 static const Addr PageShift = 13;
133 static const Addr PageBytes = ULL(1) << PageShift;
134 static const Addr PageMask = ~(PageBytes - 1);
135 static const Addr PageOffset = PageBytes - 1;
139 typedef uint64_t InternalProcReg;
141 #include "arch/alpha/isa_fullsys_traits.hh"
145 NumInternalProcRegs = 0
151 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
155 TotalDataRegs = NumIntRegs + NumFloatRegs
165 IntRegFile intRegFile; // (signed) integer register file
166 FloatRegFile floatRegFile; // floating point register file
167 MiscRegFile miscRegs; // control register file
168 Addr pc; // program counter
169 Addr npc; // next-cycle program counter
171 IntReg palregs[NumIntRegs]; // PAL shadow registers
172 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
173 int intrflag; // interrupt flag
174 bool pal_shadow; // using pal_shadow registers
175 inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
176 inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
177 #endif // FULL_SYSTEM
179 void serialize(std::ostream &os);
180 void unserialize(Checkpoint *cp, const std::string §ion);
183 static StaticInstPtr<AlphaISA> decodeInst(MachInst);
185 // return a no-op instruction... used for instruction fetch faults
186 static const MachInst NoopMachInst;
190 // An impossible number for instruction annotations
191 ITOUCH_ANNOTE = 0xffffffff,
194 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
195 panic("register classification not implemented");
196 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
199 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
200 panic("register classification not implemented");
201 return (reg >= 9 && reg <= 15);
204 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
205 panic("register classification not implemented");
209 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
210 panic("register classification not implemented");
214 static inline Addr alignAddress(const Addr &addr,
215 unsigned int nbytes) {
216 return (addr & ~(nbytes - 1));
219 // Instruction address compression hooks
220 static inline Addr realPCToFetchPC(const Addr &addr) {
224 static inline Addr fetchPCToRealPC(const Addr &addr) {
228 // the size of "fetched" instructions (not necessarily the size
229 // of real instructions for PISA)
230 static inline size_t fetchInstSize() {
231 return sizeof(MachInst);
234 static inline MachInst makeRegisterCopy(int dest, int src) {
235 panic("makeRegisterCopy not implemented");
239 // Machine operations
241 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
244 static void restoreMachineReg(RegFile ®s, const AnyReg ®,
248 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
249 const RegFile ®s);
251 static void unserializeSpecialRegs(const IniFile *db,
252 const std::string &category,
258 * Function to insure ISA semantics about 0 registers.
259 * @param xc The execution context.
262 static void zeroRegisters(XC *xc);
266 typedef AlphaISA TheISA;
268 typedef TheISA::MachInst MachInst;
269 typedef TheISA::Addr Addr;
270 typedef TheISA::RegIndex RegIndex;
271 typedef TheISA::IntReg IntReg;
272 typedef TheISA::IntRegFile IntRegFile;
273 typedef TheISA::FloatReg FloatReg;
274 typedef TheISA::FloatRegFile FloatRegFile;
275 typedef TheISA::MiscReg MiscReg;
276 typedef TheISA::MiscRegFile MiscRegFile;
277 typedef TheISA::AnyReg AnyReg;
278 typedef TheISA::RegFile RegFile;
280 const int NumIntRegs = TheISA::NumIntRegs;
281 const int NumFloatRegs = TheISA::NumFloatRegs;
282 const int NumMiscRegs = TheISA::NumMiscRegs;
283 const int TotalNumRegs = TheISA::TotalNumRegs;
284 const int VMPageSize = TheISA::VMPageSize;
285 const int LogVMPageSize = TheISA::LogVMPageSize;
286 const int ZeroReg = TheISA::ZeroReg;
287 const int StackPointerReg = TheISA::StackPointerReg;
288 const int GlobalPointerReg = TheISA::GlobalPointerReg;
289 const int ReturnAddressReg = TheISA::ReturnAddressReg;
290 const int ReturnValueReg = TheISA::ReturnValueReg;
291 const int ArgumentReg0 = TheISA::ArgumentReg0;
292 const int ArgumentReg1 = TheISA::ArgumentReg1;
293 const int ArgumentReg2 = TheISA::ArgumentReg2;
294 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
295 const int MaxAddr = (Addr)-1;
298 class SyscallReturn {
301 SyscallReturn(T v, bool s)
303 retval = (uint64_t)v;
311 retval = (uint64_t)v;
316 SyscallReturn& operator=(const SyscallReturn& s) {
322 bool successful() { return success; }
323 uint64_t value() { return retval; }
335 typedef TheISA::InternalProcReg InternalProcReg;
336 const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
337 const int NumInterruptLevels = TheISA::NumInterruptLevels;
339 #include "arch/alpha/ev5.hh"
342 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__