arch/alpha/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
  30 #define __ARCH_ALPHA_ISA_TRAITS_HH__
  31
  32 namespace LittleEndianGuest {}
  33 using namespace LittleEndianGuest;
  34
  35 //#include "arch/alpha/faults.hh"
  36 #include "base/misc.hh"
  37 #include "config/full_system.hh"
  38 #include "sim/host.hh"
  39 #include "sim/faults.hh"
  40
  41 class ExecContext;
  42 class FastCPU;
  43 class FullCPU;
  44 class Checkpoint;
  45
  46 #define TARGET_ALPHA
  47
  48 class StaticInst;
  49 class StaticInstPtr;
  50
  51 namespace EV5 {
  52 int DTB_ASN_ASN(uint64_t reg);
  53 int ITB_ASN_ASN(uint64_t reg);
  54 }
  55
  56 namespace AlphaISA
  57 {
  58
  59     typedef uint32_t MachInst;
  60     typedef uint8_t  RegIndex;
  61
  62     enum {
  63         MemoryEnd = 0xffffffffffffffffULL,
  64
  65         NumIntRegs = 32,
  66         NumFloatRegs = 32,
  67         // @todo: Figure out what this number really should be.
  68         NumMiscRegs = 32,
  69
  70         MaxRegsOfAnyType = 32,
  71         // Static instruction parameters
  72         MaxInstSrcRegs = 3,
  73         MaxInstDestRegs = 2,
  74
  75         // semantically meaningful register indices
  76         ZeroReg = 31,   // architecturally meaningful
  77         // the rest of these depend on the ABI
  78         StackPointerReg = 30,
  79         GlobalPointerReg = 29,
  80         ProcedureValueReg = 27,
  81         ReturnAddressReg = 26,
  82         ReturnValueReg = 0,
  83         FramePointerReg = 15,
  84         ArgumentReg0 = 16,
  85         ArgumentReg1 = 17,
  86         ArgumentReg2 = 18,
  87         ArgumentReg3 = 19,
  88         ArgumentReg4 = 20,
  89         ArgumentReg5 = 21,
  90
  91         LogVMPageSize = 13,     // 8K bytes
  92         VMPageSize = (1 << LogVMPageSize),
  93
  94         BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
  95
  96         WordBytes = 4,
  97         HalfwordBytes = 2,
  98         ByteBytes = 1,
  99         DepNA = 0,
 100     };
 101
 102     // These enumerate all the registers for dependence tracking.
 103     enum DependenceTags {
 104         // 0..31 are the integer regs 0..31
 105         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
 106         FP_Base_DepTag = 32,
 107         Ctrl_Base_DepTag = 64,
 108         Fpcr_DepTag = 64,               // floating point control register
 109         Uniq_DepTag = 65,
 110         Lock_Flag_DepTag = 66,
 111         Lock_Addr_DepTag = 67,
 112         IPR_Base_DepTag = 68
 113     };
 114
 115     typedef uint64_t IntReg;
 116     typedef IntReg IntRegFile[NumIntRegs];
 117
 118     // floating point register file entry type
 119     typedef union {
 120         uint64_t q;
 121         double d;
 122     } FloatReg;
 123
 124     typedef union {
 125         uint64_t q[NumFloatRegs];       // integer qword view
 126         double d[NumFloatRegs];         // double-precision floating point view
 127     } FloatRegFile;
 128
 129 extern const Addr PageShift;
 130 extern const Addr PageBytes;
 131 extern const Addr PageMask;
 132 extern const Addr PageOffset;
 133
 134 #if FULL_SYSTEM
 135
 136     typedef uint64_t InternalProcReg;
 137
 138 #include "arch/alpha/isa_fullsys_traits.hh"
 139
 140 #else
 141     enum {
 142         NumInternalProcRegs = 0
 143     };
 144 #endif
 145
 146     // control register file contents
 147     typedef uint64_t MiscReg;
 148     class MiscRegFile {
 149       protected:
 150         uint64_t        fpcr;           // floating point condition codes
 151         uint64_t        uniq;           // process-unique register
 152         bool            lock_flag;      // lock flag for LL/SC
 153         Addr            lock_addr;      // lock address for LL/SC
 154
 155       public:
 156         MiscReg readReg(int misc_reg);
 157
 158         MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
 159
 160         Fault setReg(int misc_reg, const MiscReg &val);
 161
 162         Fault setRegWithEffect(int misc_reg, const MiscReg &val,
 163                                ExecContext *xc);
 164
 165 #if FULL_SYSTEM
 166         void clearIprs();
 167
 168       protected:
 169         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 170
 171       private:
 172         MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
 173
 174         Fault setIpr(int idx, uint64_t val, ExecContext *xc);
 175 #endif
 176         friend class RegFile;
 177     };
 178
 179     enum {
 180         TotalNumRegs =
 181         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
 182     };
 183
 184     enum {
 185         TotalDataRegs = NumIntRegs + NumFloatRegs
 186     };
 187
 188     typedef union {
 189         IntReg  intreg;
 190         FloatReg   fpreg;
 191         MiscReg ctrlreg;
 192     } AnyReg;
 193
 194     struct RegFile {
 195         IntRegFile intRegFile;          // (signed) integer register file
 196         FloatRegFile floatRegFile;      // floating point register file
 197         MiscRegFile miscRegs;           // control register file
 198         Addr pc;                        // program counter
 199         Addr npc;                       // next-cycle program counter
 200 #if FULL_SYSTEM
 201         IntReg palregs[NumIntRegs];     // PAL shadow registers
 202         int intrflag;                   // interrupt flag
 203         bool pal_shadow;                // using pal_shadow registers
 204         inline int instAsid()
 205         { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
 206         inline int dataAsid()
 207         { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
 208 #endif // FULL_SYSTEM
 209
 210         void serialize(std::ostream &os);
 211         void unserialize(Checkpoint *cp, const std::string &section);
 212     };
 213
 214     StaticInstPtr decodeInst(MachInst);
 215
 216     // return a no-op instruction... used for instruction fetch faults
 217     extern const MachInst NoopMachInst;
 218
 219     enum annotes {
 220         ANNOTE_NONE = 0,
 221         // An impossible number for instruction annotations
 222         ITOUCH_ANNOTE = 0xffffffff,
 223     };
 224
 225     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
 226         panic("register classification not implemented");
 227         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
 228     }
 229
 230     static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
 231         panic("register classification not implemented");
 232         return (reg >= 9 && reg <= 15);
 233     }
 234
 235     static inline bool isCallerSaveFloatRegister(unsigned int reg) {
 236         panic("register classification not implemented");
 237         return false;
 238     }
 239
 240     static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
 241         panic("register classification not implemented");
 242         return false;
 243     }
 244
 245     static inline Addr alignAddress(const Addr &addr,
 246                                          unsigned int nbytes) {
 247         return (addr & ~(nbytes - 1));
 248     }
 249
 250     // Instruction address compression hooks
 251     static inline Addr realPCToFetchPC(const Addr &addr) {
 252         return addr;
 253     }
 254
 255     static inline Addr fetchPCToRealPC(const Addr &addr) {
 256         return addr;
 257     }
 258
 259     // the size of "fetched" instructions (not necessarily the size
 260     // of real instructions for PISA)
 261     static inline size_t fetchInstSize() {
 262         return sizeof(MachInst);
 263     }
 264
 265     static inline MachInst makeRegisterCopy(int dest, int src) {
 266         panic("makeRegisterCopy not implemented");
 267         return 0;
 268     }
 269
 270     // Machine operations
 271
 272     void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 273                                int regnum);
 274
 275     void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 276                                   int regnum);
 277
 278 #if 0
 279     static void serializeSpecialRegs(const Serializable::Proxy &proxy,
 280                                      const RegFile &regs);
 281
 282     static void unserializeSpecialRegs(const IniFile *db,
 283                                        const std::string &category,
 284                                        ConfigNode *node,
 285                                        RegFile &regs);
 286 #endif
 287
 288     /**
 289      * Function to insure ISA semantics about 0 registers.
 290      * @param xc The execution context.
 291      */
 292     template <class XC>
 293     void zeroRegisters(XC *xc);
 294
 295
 296 //typedef AlphaISA TheISA;
 297
 298 //typedef TheISA::MachInst MachInst;
 299 //typedef TheISA::Addr Addr;
 300 //typedef TheISA::RegIndex RegIndex;
 301 //typedef TheISA::IntReg IntReg;
 302 //typedef TheISA::IntRegFile IntRegFile;
 303 //typedef TheISA::FloatReg FloatReg;
 304 //typedef TheISA::FloatRegFile FloatRegFile;
 305 //typedef TheISA::MiscReg MiscReg;
 306 //typedef TheISA::MiscRegFile MiscRegFile;
 307 //typedef TheISA::AnyReg AnyReg;
 308 //typedef TheISA::RegFile RegFile;
 309
 310 //const int NumIntRegs   = TheISA::NumIntRegs;
 311 //const int NumFloatRegs = TheISA::NumFloatRegs;
 312 //const int NumMiscRegs  = TheISA::NumMiscRegs;
 313 //const int TotalNumRegs = TheISA::TotalNumRegs;
 314 //const int VMPageSize   = TheISA::VMPageSize;
 315 //const int LogVMPageSize   = TheISA::LogVMPageSize;
 316 //const int ZeroReg = TheISA::ZeroReg;
 317 //const int StackPointerReg = TheISA::StackPointerReg;
 318 //const int GlobalPointerReg = TheISA::GlobalPointerReg;
 319 //const int ReturnAddressReg = TheISA::ReturnAddressReg;
 320 //const int ReturnValueReg = TheISA::ReturnValueReg;
 321 //const int ArgumentReg0 = TheISA::ArgumentReg0;
 322 //const int ArgumentReg1 = TheISA::ArgumentReg1;
 323 //const int ArgumentReg2 = TheISA::ArgumentReg2;
 324 //const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
 325 const Addr MaxAddr = (Addr)-1;
 326 };
 327
 328 #if !FULL_SYSTEM
 329 class SyscallReturn {
 330         public:
 331            template <class T>
 332            SyscallReturn(T v, bool s)
 333            {
 334                retval = (uint64_t)v;
 335                success = s;
 336            }
 337
 338            template <class T>
 339            SyscallReturn(T v)
 340            {
 341                success = (v >= 0);
 342                retval = (uint64_t)v;
 343            }
 344
 345            ~SyscallReturn() {}
 346
 347            SyscallReturn& operator=(const SyscallReturn& s) {
 348                retval = s.retval;
 349                success = s.success;
 350                return *this;
 351            }
 352
 353            bool successful() { return success; }
 354            uint64_t value() { return retval; }
 355
 356
 357        private:
 358            uint64_t retval;
 359            bool success;
 360 };
 361
 362 #endif
 363
 364
 365 #if FULL_SYSTEM
 366 //typedef TheISA::InternalProcReg InternalProcReg;
 367 //const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 368 //const int NumInterruptLevels = TheISA::NumInterruptLevels;
 369
 370 #include "arch/alpha/ev5.hh"
 371 #endif
 372
 373 #endif // __ARCH_ALPHA_ISA_TRAITS_HH__