arch/mips/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
  30 #define __ARCH_MIPS_ISA_TRAITS_HH__
  31
  32 //#include "arch/mips/misc_regfile.hh"
  33 #include "base/misc.hh"
  34 #include "config/full_system.hh"
  35 #include "sim/host.hh"
  36 #include "sim/faults.hh"
  37
  38 #include <vector>
  39
  40 class FastCPU;
  41 class FullCPU;
  42 class Checkpoint;
  43
  44 namespace LittleEndianGuest {};
  45 using namespace LittleEndianGuest;
  46
  47 #define TARGET_MIPS
  48
  49 class StaticInst;
  50 class StaticInstPtr;
  51
  52 namespace MIPS34K {
  53 int DTB_ASN_ASN(uint64_t reg);
  54 int ITB_ASN_ASN(uint64_t reg);
  55 };
  56
  57 namespace MipsISA
  58 {
  59     typedef uint32_t MachInst;
  60 //  typedef uint64_t Addr;
  61     typedef uint8_t  RegIndex;
  62
  63     enum {
  64         MemoryEnd = 0xffffffffffffffffULL,
  65
  66         NumIntRegs = 32,
  67         NumFloatRegs = 32,
  68         NumMiscRegs = 256,
  69
  70         MaxRegsOfAnyType = 32,
  71         // Static instruction parameters
  72         MaxInstSrcRegs = 3,
  73         MaxInstDestRegs = 2,
  74
  75         // semantically meaningful register indices
  76         ZeroReg = 0,    // architecturally meaningful
  77         // the rest of these depend on the ABI
  78         StackPointerReg = 30,
  79         GlobalPointerReg = 29,
  80         ProcedureValueReg = 27,
  81         ReturnAddressReg = 26,
  82         ReturnValueReg = 0,
  83         FramePointerReg = 15,
  84         ArgumentReg0 = 16,
  85         ArgumentReg1 = 17,
  86         ArgumentReg2 = 18,
  87         ArgumentReg3 = 19,
  88         ArgumentReg4 = 20,
  89         ArgumentReg5 = 21,
  90
  91         LogVMPageSize = 13,     // 8K bytes
  92         VMPageSize = (1 << LogVMPageSize),
  93
  94         BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
  95
  96         WordBytes = 4,
  97         HalfwordBytes = 2,
  98         ByteBytes = 1,
  99         DepNA = 0,
 100     };
 101
 102     // These enumerate all the registers for dependence tracking.
 103     enum DependenceTags {
 104         // 0..31 are the integer regs 0..31
 105         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
 106         FP_Base_DepTag = 32,
 107         Ctrl_Base_DepTag = 64,
 108         Fpcr_DepTag = 64,               // floating point control register
 109         Uniq_DepTag = 65,
 110         IPR_Base_DepTag = 66,
 111         MiscReg_DepTag = 67
 112     };
 113
 114     typedef uint64_t IntReg;
 115     typedef IntReg IntRegFile[NumIntRegs];
 116
 117     // floating point register file entry type
 118     typedef union {
 119         uint64_t q;
 120         double d;
 121     } FloatReg;
 122
 123     typedef union {
 124         uint64_t q[NumFloatRegs];       // integer qword view
 125         double d[NumFloatRegs];         // double-precision floating point view
 126     } FloatRegFile;
 127
 128     // cop-0/cop-1 system control register file
 129     typedef uint64_t MiscReg;
 130     typedef MiscReg MiscRegFile[NumMiscRegs];
 131
 132
 133     enum MiscRegTags {
 134         //Coprocessor 0 Registers
 135         //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
 136         //(Register Number-Register Select) Summary of Register
 137         //------------------------------------------------------
 138         Index = 0,       //0-0 Index into the TLB array
 139
 140         MVPControl = 1,  //0-1 Per-processor register containing global
 141                      //MIPS® MT configuration data
 142
 143         MVPConf0 = 2,    //0-2 Per-processor register containing global
 144                      //MIPS® MT configuration data
 145
 146         MVPConf1 = 3,    //0-3 Per-processor register containing global
 147                      //MIPS® MT configuration data
 148
 149         Random = 8,      //1-0 Randomly generated index into the TLB array
 150
 151         VPEControl = 9,  //1-1 Per-VPE register containing relatively volatile
 152                      //thread configuration data
 153
 154         VPEConf0 = 10,    //1-2 Per-VPE multi-thread configuration
 155                      //information
 156
 157
 158         VPEConf1 = 11,    //1-2 Per-VPE multi-thread configuration
 159                      //information
 160
 161         YQMask = 12,      //Per-VPE register defining which YIELD
 162                      //qualifier bits may be used without generating
 163                      //an exception
 164
 165         VPESchedule = 13,
 166         VPEScheFBack =  14,
 167         VPEOpt = 15,
 168         EntryLo0 = 16, // Bank 3: 16 - 23
 169         TCStatus = 17,
 170         TCBind = 18,
 171         TCRestart = 19,
 172         TCHalt = 20,
 173         TCContext = 21,
 174         TCSchedule = 22,
 175         TCScheFBack = 23,
 176
 177         EntryLo1 = 24,// Bank 4: 24 - 31
 178
 179         Context = 32, // Bank 5: 32 - 39
 180         ContextConfig = 33,
 181
 182         //PageMask = 40, //Bank 6: 40 - 47
 183         PageGrain = 41,
 184
 185         Wired = 48, //Bank 7:48 - 55
 186         SRSConf0 = 49,
 187         SRSConf1 = 50,
 188         SRSConf2 = 51,
 189         SRSConf3 = 52,
 190         SRSConf4 = 53,
 191         BadVAddr = 54,
 192
 193         HWRena = 56,//Bank 8:56 - 63
 194
 195         Count = 64, //Bank 9:64 - 71
 196
 197         EntryHi = 72,//Bank 10:72 - 79
 198
 199         Compare = 80,//Bank 11:80 - 87
 200
 201         Status = 88,//Bank 12:88 - 96     //12-0 Processor status and control
 202         IntCtl = 89,                      //12-1 Interrupt system status and control
 203         SRSCtl = 90,                      //12-2 Shadow register set status and control
 204         SRSMap = 91,                      //12-3 Shadow set IPL mapping
 205
 206         Cause = 97,//97-104      //13-0 Cause of last general exception
 207
 208         EPC = 105,//105-112        //14-0 Program counter at last exception
 209
 210         PrId = 113//113-120,       //15-0 Processor identification and revision
 211         EBase = 114,      //15-1 Exception vector base register
 212
 213         Config = 121,//121-128
 214         Config1 = 122,
 215         Config2 = 123,
 216         Config3 = 124,
 217         Config6 = 127,
 218         Config7 = 128,
 219
 220
 221         LLAddr = 129,//129-136
 222
 223         WatchLo0 = 137,//137-144
 224         WatchLo1 = 138,
 225         WatchLo2 = 139,
 226         WatchLo3 = 140,
 227         WatchLo4 = 141,
 228         WatchLo5 = 142,
 229         WatchLo6 = 143,
 230         WatchLo7 = 144,
 231
 232         WatchHi0 = 145,//145-152
 233         WatchHi1 = 146,
 234         WatchHi2 = 147,
 235         WatchHi3 = 148,
 236         WatchHi4 = 149,
 237         WatchHi5 = 150,
 238         WatchHi6 = 151,
 239         WatchHi7 = 152,
 240
 241         XCContext64 = 153,//153-160
 242
 243         //161-168
 244
 245         //169-176
 246
 247         Debug = 177, //177-184
 248         TraceControl1 = 178,
 249         TraceControl2 = 179,
 250         UserTraceData = 180,
 251         TraceBPC = 181,
 252
 253         DEPC = 185,//185-192
 254
 255         PerfCnt0 = 193,//193 - 200
 256         PerfCnt1 = 194,
 257         PerfCnt2 = 195,
 258         PerfCnt3 = 196,
 259         PerfCnt4 = 197,
 260         PerfCnt5 = 198,
 261         PerfCnt6 = 199,
 262         PerfCnt7 = 200,
 263
 264         ErrCtl = 201, //201 - 208
 265
 266         CacheErr0 = 209, //209 - 216
 267         CacheErr1 = 210,
 268         CacheErr2 = 211,
 269         CacheErr3 = 212,
 270
 271         TagLo0 = 217,//217 - 224
 272         TagLo2 = 219,
 273         TagLo4 = 221,
 274         TagLo6 = 223,
 275
 276         DataLo1 = 226,//225 - 232
 277         DataLo3 = 228,
 278         DataLo5 = 220,
 279         DataLo7 = 232,
 280
 281         TagHi0 = 233,//233 - 240
 282         TagHi2 = 235,
 283         TagHi4 = 237,
 284         TagHi6 = 239,
 285
 286         DataHi0 = 241,//241 - 248
 287         DataHi2 = 243,
 288         DataHi4 = 245,
 289         DataHi6 = 247,
 290
 291         ErrorEPC = 249,//249 - 256
 292
 293         DESAVE = 257,
 294
 295         //More Misc. Regs
 296         Hi,
 297         Lo,
 298         FCSR,
 299         FPCR,
 300         LockAddr,
 301         LockFlag,
 302
 303         //Alpha Regs, but here now, for
 304         //compiling sake
 305         UNIQ
 306     };
 307
 308 extern const Addr PageShift;
 309 extern const Addr PageBytes;
 310 extern const Addr PageMask;
 311 extern const Addr PageOffset;
 312
 313 #if FULL_SYSTEM
 314
 315     typedef uint64_t InternalProcReg;
 316
 317 #include "arch/mips/isa_fullsys_traits.hh"
 318
 319 #else
 320     enum {
 321         NumInternalProcRegs = 0
 322     };
 323 #endif
 324
 325     enum {
 326         TotalNumRegs =
 327         NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
 328     };
 329
 330     enum {
 331         TotalDataRegs = NumIntRegs + NumFloatRegs
 332     };
 333
 334     typedef union {
 335         IntReg  intreg;
 336         FloatReg   fpreg;
 337         MiscReg ctrlreg;
 338     } AnyReg;
 339
 340     struct RegFile {
 341         IntRegFile intRegFile;          // (signed) integer register file
 342         FloatRegFile floatRegFile;      // floating point register file
 343         MiscRegFile miscRegs;           // control register file
 344
 345
 346         Addr pc;                        // program counter
 347         Addr npc;                       // next-cycle program counter
 348         Addr nnpc;                      // next-next-cycle program counter
 349                                         // used to implement branch delay slot
 350                                         // not real register
 351
 352         MiscReg hi;                     // MIPS HI Register
 353         MiscReg lo;                     // MIPS LO Register
 354
 355
 356 #if FULL_SYSTEM
 357         IntReg palregs[NumIntRegs];     // PAL shadow registers
 358         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
 359         int intrflag;                   // interrupt flag
 360         bool pal_shadow;                // using pal_shadow registers
 361         inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
 362         inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
 363 #endif // FULL_SYSTEM
 364
 365         //void initCP0Regs();
 366         void serialize(std::ostream &os);
 367         void unserialize(Checkpoint *cp, const std::string &section);
 368
 369         void createCP0Regs();
 370         void coldReset();
 371     };
 372
 373     StaticInstPtr decodeInst(MachInst);
 374
 375     // return a no-op instruction... used for instruction fetch faults
 376     extern const MachInst NoopMachInst;
 377
 378     enum annotes {
 379         ANNOTE_NONE = 0,
 380         // An impossible number for instruction annotations
 381         ITOUCH_ANNOTE = 0xffffffff,
 382     };
 383
 384    void getMiscRegIdx(int reg_name,int &idx, int &sel);
 385
 386
 387     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
 388         panic("register classification not implemented");
 389         return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
 390     }
 391
 392     static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
 393         panic("register classification not implemented");
 394         return (reg >= 9 && reg <= 15);
 395     }
 396
 397     static inline bool isCallerSaveFloatRegister(unsigned int reg) {
 398         panic("register classification not implemented");
 399         return false;
 400     }
 401
 402     static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
 403         panic("register classification not implemented");
 404         return false;
 405     }
 406
 407     static inline Addr alignAddress(const Addr &addr,
 408                                          unsigned int nbytes) {
 409         return (addr & ~(nbytes - 1));
 410     }
 411
 412     // Instruction address compression hooks
 413     static inline Addr realPCToFetchPC(const Addr &addr) {
 414         return addr;
 415     }
 416
 417     static inline Addr fetchPCToRealPC(const Addr &addr) {
 418         return addr;
 419     }
 420
 421     // the size of "fetched" instructions (not necessarily the size
 422     // of real instructions for PISA)
 423     static inline size_t fetchInstSize() {
 424         return sizeof(MachInst);
 425     }
 426
 427     static inline MachInst makeRegisterCopy(int dest, int src) {
 428         panic("makeRegisterCopy not implemented");
 429         return 0;
 430     }
 431
 432     // Machine operations
 433
 434     void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
 435                                int regnum);
 436
 437     void restoreMachineReg(RegFile &regs, const AnyReg &reg,
 438                                   int regnum);
 439
 440 #if 0
 441     static void serializeSpecialRegs(const Serializable::Proxy &proxy,
 442                                      const RegFile &regs);
 443
 444     static void unserializeSpecialRegs(const IniFile *db,
 445                                        const std::string &category,
 446                                        ConfigNode *node,
 447                                        RegFile &regs);
 448 #endif
 449
 450     /**
 451      * Function to insure ISA semantics about 0 registers.
 452      * @param xc The execution context.
 453      */
 454     template <class XC>
 455     void zeroRegisters(XC *xc);
 456
 457     const Addr MaxAddr = (Addr)-1;
 458 };
 459
 460 #if !FULL_SYSTEM
 461 class SyscallReturn {
 462         public:
 463            template <class T>
 464            SyscallReturn(T v, bool s)
 465            {
 466                retval = (uint64_t)v;
 467                success = s;
 468            }
 469
 470            template <class T>
 471            SyscallReturn(T v)
 472            {
 473                success = (v >= 0);
 474                retval = (uint64_t)v;
 475            }
 476
 477            ~SyscallReturn() {}
 478
 479            SyscallReturn& operator=(const SyscallReturn& s) {
 480                retval = s.retval;
 481                success = s.success;
 482                return *this;
 483            }
 484
 485            bool successful() { return success; }
 486            uint64_t value() { return retval; }
 487
 488
 489        private:
 490            uint64_t retval;
 491            bool success;
 492 };
 493
 494 #endif
 495
 496
 497 #if FULL_SYSTEM
 498 //typedef TheISA::InternalProcReg InternalProcReg;
 499 //const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 500 //const int NumInterruptLevels = TheISA::NumInterruptLevels;
 501
 502 #include "arch/mips/mips34k.hh"
 503 #endif
 504
 505 #endif // __ARCH_MIPS_ISA_TRAITS_HH__