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29 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
30 #define __ARCH_MIPS_ISA_TRAITS_HH__
32 //#include "arch/mips/misc_regfile.hh"
33 #include "base/misc.hh"
34 #include "config/full_system.hh"
35 #include "sim/host.hh"
36 #include "sim/faults.hh"
45 namespace LittleEndianGuest {};
46 using namespace LittleEndianGuest;
54 int DTB_ASN_ASN(uint64_t reg);
55 int ITB_ASN_ASN(uint64_t reg);
62 SyscallReturn(T v, bool s)
77 SyscallReturn& operator=(const SyscallReturn& s) {
83 bool successful() { return success; }
84 uint64_t value() { return retval; }
95 typedef uint32_t MachInst;
96 typedef uint32_t MachInst;
97 typedef uint64_t ExtMachInst;
98 typedef uint8_t RegIndex;
99 // typedef uint64_t Addr;
101 // Constants Related to the number of registers
103 const int NumIntArchRegs = 32;
104 const int NumPALShadowRegs = 8;
105 const int NumFloatArchRegs = 32;
106 // @todo: Figure out what this number really should be.
107 const int NumMiscArchRegs = 32;
109 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
110 const int NumFloatRegs = NumFloatArchRegs;
111 const int NumMiscRegs = NumMiscArchRegs;
113 const int TotalNumRegs = NumIntRegs + NumFloatRegs +
114 NumMiscRegs + 0/*NumInternalProcRegs*/;
116 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
118 // Static instruction parameters
119 const int MaxInstSrcRegs = 3;
120 const int MaxInstDestRegs = 2;
122 // semantically meaningful register indices
123 const int ZeroReg = 0;
124 const int AssemblerReg = 1;
125 const int ReturnValueReg1 = 2;
126 const int ReturnValueReg2 = 3;
127 const int ArgumentReg0 = 4;
128 const int ArgumentReg1 = 5;
129 const int ArgumentReg2 = 6;
130 const int ArgumentReg3 = 7;
131 const int KernelReg0 = 26;
132 const int KernelReg1 = 27;
133 const int GlobalPointerReg = 28;
134 const int StackPointerReg = 29;
135 const int FramePointerReg = 30;
136 const int ReturnAddressReg = 31;
138 const int SyscallNumReg = ReturnValueReg1;
139 const int SyscallPseudoReturnReg = ArgumentReg3;
140 const int SyscallSuccessReg = 19;
142 const int LogVMPageSize = 13; // 8K bytes
143 const int VMPageSize = (1 << LogVMPageSize);
145 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
147 const int MachineBytes = 4;
148 const int WordBytes = 4;
149 const int HalfwordBytes = 2;
150 const int ByteBytes = 1;
153 // These enumerate all the registers for dependence tracking.
154 enum DependenceTags {
155 // 0..31 are the integer regs 0..31
156 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
158 Ctrl_Base_DepTag = 64,
159 Fpcr_DepTag = 64, // floating point control register
161 IPR_Base_DepTag = 66,
165 typedef uint64_t IntReg;
166 typedef IntReg IntRegFile[NumIntRegs];
168 /* floating point register file entry type
174 typedef double FloatReg;
175 typedef uint64_t FloatRegBits;
178 uint64_t q[NumFloatRegs]; // integer qword view
179 double d[NumFloatRegs]; // double-precision floating point view
186 FloatRegBits q[NumFloatRegs]; // integer qword view
187 double d[NumFloatRegs]; // double-precision floating point view
191 FloatReg readReg(int floatReg)
196 FloatReg readReg(int floatReg, int width)
198 return readReg(floatReg);
201 FloatRegBits readRegBits(int floatReg)
206 FloatRegBits readRegBits(int floatReg, int width)
208 return readRegBits(floatReg);
211 Fault setReg(int floatReg, const FloatReg &val)
217 Fault setReg(int floatReg, const FloatReg &val, int width)
219 return setReg(floatReg, val);
222 Fault setRegBits(int floatReg, const FloatRegBits &val)
228 Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
230 return setRegBits(floatReg, val);
233 void serialize(std::ostream &os);
235 void unserialize(Checkpoint *cp, const std::string §ion);
239 void copyRegs(ExecContext *src, ExecContext *dest);
241 // cop-0/cop-1 system control register file
242 typedef uint64_t MiscReg;
243 //typedef MiscReg MiscRegFile[NumMiscRegs];
247 uint64_t fpcr; // floating point condition codes
248 uint64_t uniq; // process-unique register
249 bool lock_flag; // lock flag for LL/SC
250 Addr lock_addr; // lock address for LL/SC
252 MiscReg miscRegFile[NumMiscRegs];
255 //These functions should be removed once the simplescalar cpu model
260 void copyMiscRegs(ExecContext *xc);
262 MiscReg readReg(int misc_reg)
263 { return miscRegFile[misc_reg]; }
265 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
266 { return miscRegFile[misc_reg];}
268 Fault setReg(int misc_reg, const MiscReg &val)
269 { miscRegFile[misc_reg] = val; return NoFault; }
271 Fault setRegWithEffect(int misc_reg, const MiscReg &val,
273 { miscRegFile[misc_reg] = val; return NoFault; }
279 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
282 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
284 Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
286 friend class RegFile;
290 //Coprocessor 0 Registers
291 //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
292 //(Register Number-Register Select) Summary of Register
293 //------------------------------------------------------
294 Index = 0, //0-0 Index into the TLB array
296 MVPControl = 1, //0-1 Per-processor register containing global
297 //MIPS® MT configuration data
299 MVPConf0 = 2, //0-2 Per-processor register containing global
300 //MIPS® MT configuration data
302 MVPConf1 = 3, //0-3 Per-processor register containing global
303 //MIPS® MT configuration data
305 Random = 8, //1-0 Randomly generated index into the TLB array
307 VPEControl = 9, //1-1 Per-VPE register containing relatively volatile
308 //thread configuration data
310 VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration
314 VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration
317 YQMask = 12, //Per-VPE register defining which YIELD
318 //qualifier bits may be used without generating
324 EntryLo0 = 16, // Bank 3: 16 - 23
333 EntryLo1 = 24,// Bank 4: 24 - 31
335 Context = 32, // Bank 5: 32 - 39
338 //PageMask = 40, //Bank 6: 40 - 47
341 Wired = 48, //Bank 7:48 - 55
349 HWRena = 56,//Bank 8:56 - 63
351 Count = 64, //Bank 9:64 - 71
353 EntryHi = 72,//Bank 10:72 - 79
355 Compare = 80,//Bank 11:80 - 87
357 Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control
358 IntCtl = 89, //12-1 Interrupt system status and control
359 SRSCtl = 90, //12-2 Shadow register set status and control
360 SRSMap = 91, //12-3 Shadow set IPL mapping
362 Cause = 97,//97-104 //13-0 Cause of last general exception
364 EPC = 105,//105-112 //14-0 Program counter at last exception
366 PRId = 113,//113-120, //15-0 Processor identification and revision
367 EBase = 114, //15-1 Exception vector base register
369 Config = 121,//Bank 16: 121-128
377 LLAddr = 129,//Bank 17: 129-136
379 WatchLo0 = 137,//Bank 18: 137-144
388 WatchHi0 = 145,//Bank 19: 145-152
397 XCContext64 = 153,//Bank 20: 153-160
403 Debug = 177, //Bank 23: 177-184
409 DEPC = 185,//Bank 24: 185-192
411 PerfCnt0 = 193,//Bank 25: 193 - 200
420 ErrCtl = 201, //Bank 26: 201 - 208
422 CacheErr0 = 209, //Bank 27: 209 - 216
427 TagLo0 = 217,//Bank 28: 217 - 224
436 TagHi0 = 233,//Bank 29: 233 - 240
446 ErrorEPC = 249,//Bank 30: 241 - 248
448 DESAVE = 257,//Bank 31: 249-256
456 //Alpha Regs, but here now, for
463 extern const Addr PageShift;
464 extern const Addr PageBytes;
465 extern const Addr PageMask;
466 extern const Addr PageOffset;
470 typedef uint64_t InternalProcReg;
472 #include "arch/mips/isa_fullsys_traits.hh"
476 NumInternalProcRegs = 0
487 IntRegFile intRegFile; // (signed) integer register file
488 FloatRegFile floatRegFile; // floating point register file
489 MiscRegFile miscRegs; // control register file
492 Addr pc; // program counter
493 Addr npc; // next-cycle program counter
494 Addr nnpc; // next-next-cycle program counter
495 // used to implement branch delay slot
498 MiscReg hi; // MIPS HI Register
499 MiscReg lo; // MIPS LO Register
503 IntReg palregs[NumIntRegs]; // PAL shadow registers
504 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
505 int intrflag; // interrupt flag
506 bool pal_shadow; // using pal_shadow registers
507 inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
508 inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
509 #endif // FULL_SYSTEM
511 //void initCP0Regs();
512 void serialize(std::ostream &os);
513 void unserialize(Checkpoint *cp, const std::string §ion);
515 void createCP0Regs();
519 StaticInstPtr decodeInst(ExtMachInst);
521 // return a no-op instruction... used for instruction fetch faults
522 extern const MachInst NoopMachInst;
526 // An impossible number for instruction annotations
527 ITOUCH_ANNOTE = 0xffffffff,
530 //void getMiscRegIdx(int reg_name,int &idx, int &sel);
532 static inline ExtMachInst
533 makeExtMI(MachInst inst, const uint64_t &pc) {
535 ExtMachInst ext_inst = inst;
537 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
541 return ExtMachInst(inst);
545 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
546 panic("register classification not implemented");
547 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
550 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
551 panic("register classification not implemented");
552 return (reg >= 9 && reg <= 15);
555 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
556 panic("register classification not implemented");
560 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
561 panic("register classification not implemented");
565 static inline Addr alignAddress(const Addr &addr,
566 unsigned int nbytes) {
567 return (addr & ~(nbytes - 1));
570 // Instruction address compression hooks
571 static inline Addr realPCToFetchPC(const Addr &addr) {
575 static inline Addr fetchPCToRealPC(const Addr &addr) {
579 // the size of "fetched" instructions (not necessarily the size
580 // of real instructions for PISA)
581 static inline size_t fetchInstSize() {
582 return sizeof(MachInst);
585 static inline MachInst makeRegisterCopy(int dest, int src) {
586 panic("makeRegisterCopy not implemented");
590 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
592 panic("Returning from syscall\n");
595 // Machine operations
597 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
600 void restoreMachineReg(RegFile ®s, const AnyReg ®,
604 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
605 const RegFile ®s);
607 static void unserializeSpecialRegs(const IniFile *db,
608 const std::string &category,
614 * Function to insure ISA semantics about 0 registers.
615 * @param xc The execution context.
618 void zeroRegisters(XC *xc);
620 const Addr MaxAddr = (Addr)-1;
624 //typedef TheISA::InternalProcReg InternalProcReg;
625 //const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
626 //const int NumInterruptLevels = TheISA::NumInterruptLevels;
628 #include "arch/mips/mips34k.hh"
631 using namespace MipsISA;
633 #endif // __ARCH_MIPS_ISA_TRAITS_HH__