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29 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
30 #define __ARCH_MIPS_ISA_TRAITS_HH__
32 //#include "arch/mips/misc_regfile.hh"
33 #include "base/misc.hh"
34 #include "config/full_system.hh"
35 #include "sim/host.hh"
36 #include "sim/faults.hh"
44 namespace LittleEndianGuest {};
45 using namespace LittleEndianGuest;
53 int DTB_ASN_ASN(uint64_t reg);
54 int ITB_ASN_ASN(uint64_t reg);
61 SyscallReturn(T v, bool s)
76 SyscallReturn& operator=(const SyscallReturn& s) {
82 bool successful() { return success; }
83 uint64_t value() { return retval; }
94 typedef uint32_t MachInst;
95 typedef uint32_t MachInst;
96 typedef uint64_t ExtMachInst;
97 typedef uint8_t RegIndex;
98 // typedef uint64_t Addr;
100 // Constants Related to the number of registers
102 const int NumIntArchRegs = 32;
103 const int NumPALShadowRegs = 8;
104 const int NumFloatArchRegs = 32;
105 // @todo: Figure out what this number really should be.
106 const int NumMiscArchRegs = 32;
108 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
109 const int NumFloatRegs = NumFloatArchRegs;
110 const int NumMiscRegs = NumMiscArchRegs;
112 const int TotalNumRegs = NumIntRegs + NumFloatRegs +
113 NumMiscRegs + 0/*NumInternalProcRegs*/;
115 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
117 // Static instruction parameters
118 const int MaxInstSrcRegs = 3;
119 const int MaxInstDestRegs = 2;
121 // semantically meaningful register indices
122 const int ZeroReg = 31; // architecturally meaningful
123 // the rest of these depend on the ABI
124 const int StackPointerReg = 30;
125 const int GlobalPointerReg = 29;
126 const int ProcedureValueReg = 27;
127 const int ReturnAddressReg = 26;
128 const int ReturnValueReg = 0;
129 const int FramePointerReg = 15;
130 const int ArgumentReg0 = 16;
131 const int ArgumentReg1 = 17;
132 const int ArgumentReg2 = 18;
133 const int ArgumentReg3 = 19;
134 const int ArgumentReg4 = 20;
135 const int ArgumentReg5 = 21;
136 const int SyscallNumReg = ReturnValueReg;
137 const int SyscallPseudoReturnReg = ArgumentReg4;
138 const int SyscallSuccessReg = 19;
140 const int LogVMPageSize = 13; // 8K bytes
141 const int VMPageSize = (1 << LogVMPageSize);
143 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
145 const int MachineBytes = 4;
146 const int WordBytes = 4;
147 const int HalfwordBytes = 2;
148 const int ByteBytes = 1;
151 // These enumerate all the registers for dependence tracking.
152 enum DependenceTags {
153 // 0..31 are the integer regs 0..31
154 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
156 Ctrl_Base_DepTag = 64,
157 Fpcr_DepTag = 64, // floating point control register
159 IPR_Base_DepTag = 66,
163 typedef uint64_t IntReg;
164 typedef IntReg IntRegFile[NumIntRegs];
166 // floating point register file entry type
173 uint64_t q[NumFloatRegs]; // integer qword view
174 double d[NumFloatRegs]; // double-precision floating point view
177 // cop-0/cop-1 system control register file
178 typedef uint64_t MiscReg;
179 //typedef MiscReg MiscRegFile[NumMiscRegs];
183 uint64_t fpcr; // floating point condition codes
184 uint64_t uniq; // process-unique register
185 bool lock_flag; // lock flag for LL/SC
186 Addr lock_addr; // lock address for LL/SC
188 MiscReg miscRegFile[NumMiscRegs];
191 //These functions should be removed once the simplescalar cpu model
196 void copyMiscRegs(ExecContext *xc);
198 MiscReg readReg(int misc_reg)
199 { return miscRegFile[misc_reg]; }
201 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
202 { return miscRegFile[misc_reg];}
204 Fault setReg(int misc_reg, const MiscReg &val)
205 { miscRegFile[misc_reg] = val; return NoFault; }
207 Fault setRegWithEffect(int misc_reg, const MiscReg &val,
209 { miscRegFile[misc_reg] = val; return NoFault; }
215 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
218 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
220 Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
222 friend class RegFile;
226 //Coprocessor 0 Registers
227 //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
228 //(Register Number-Register Select) Summary of Register
229 //------------------------------------------------------
230 Index = 0, //0-0 Index into the TLB array
232 MVPControl = 1, //0-1 Per-processor register containing global
233 //MIPS® MT configuration data
235 MVPConf0 = 2, //0-2 Per-processor register containing global
236 //MIPS® MT configuration data
238 MVPConf1 = 3, //0-3 Per-processor register containing global
239 //MIPS® MT configuration data
241 Random = 8, //1-0 Randomly generated index into the TLB array
243 VPEControl = 9, //1-1 Per-VPE register containing relatively volatile
244 //thread configuration data
246 VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration
250 VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration
253 YQMask = 12, //Per-VPE register defining which YIELD
254 //qualifier bits may be used without generating
260 EntryLo0 = 16, // Bank 3: 16 - 23
269 EntryLo1 = 24,// Bank 4: 24 - 31
271 Context = 32, // Bank 5: 32 - 39
274 //PageMask = 40, //Bank 6: 40 - 47
277 Wired = 48, //Bank 7:48 - 55
285 HWRena = 56,//Bank 8:56 - 63
287 Count = 64, //Bank 9:64 - 71
289 EntryHi = 72,//Bank 10:72 - 79
291 Compare = 80,//Bank 11:80 - 87
293 Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control
294 IntCtl = 89, //12-1 Interrupt system status and control
295 SRSCtl = 90, //12-2 Shadow register set status and control
296 SRSMap = 91, //12-3 Shadow set IPL mapping
298 Cause = 97,//97-104 //13-0 Cause of last general exception
300 EPC = 105,//105-112 //14-0 Program counter at last exception
302 PRId = 113,//113-120, //15-0 Processor identification and revision
303 EBase = 114, //15-1 Exception vector base register
305 Config = 121,//Bank 16: 121-128
313 LLAddr = 129,//Bank 17: 129-136
315 WatchLo0 = 137,//Bank 18: 137-144
324 WatchHi0 = 145,//Bank 19: 145-152
333 XCContext64 = 153,//Bank 20: 153-160
339 Debug = 177, //Bank 23: 177-184
345 DEPC = 185,//Bank 24: 185-192
347 PerfCnt0 = 193,//Bank 25: 193 - 200
356 ErrCtl = 201, //Bank 26: 201 - 208
358 CacheErr0 = 209, //Bank 27: 209 - 216
363 TagLo0 = 217,//Bank 28: 217 - 224
372 TagHi0 = 233,//Bank 29: 233 - 240
382 ErrorEPC = 249,//Bank 30: 241 - 248
384 DESAVE = 257,//Bank 31: 249-256
392 //Alpha Regs, but here now, for
399 extern const Addr PageShift;
400 extern const Addr PageBytes;
401 extern const Addr PageMask;
402 extern const Addr PageOffset;
406 typedef uint64_t InternalProcReg;
408 #include "arch/mips/isa_fullsys_traits.hh"
412 NumInternalProcRegs = 0
423 IntRegFile intRegFile; // (signed) integer register file
424 FloatRegFile floatRegFile; // floating point register file
425 MiscRegFile miscRegs; // control register file
428 Addr pc; // program counter
429 Addr npc; // next-cycle program counter
430 Addr nnpc; // next-next-cycle program counter
431 // used to implement branch delay slot
434 MiscReg hi; // MIPS HI Register
435 MiscReg lo; // MIPS LO Register
439 IntReg palregs[NumIntRegs]; // PAL shadow registers
440 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
441 int intrflag; // interrupt flag
442 bool pal_shadow; // using pal_shadow registers
443 inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
444 inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
445 #endif // FULL_SYSTEM
447 //void initCP0Regs();
448 void serialize(std::ostream &os);
449 void unserialize(Checkpoint *cp, const std::string §ion);
451 void createCP0Regs();
455 StaticInstPtr decodeInst(ExtMachInst);
457 // return a no-op instruction... used for instruction fetch faults
458 extern const MachInst NoopMachInst;
462 // An impossible number for instruction annotations
463 ITOUCH_ANNOTE = 0xffffffff,
466 //void getMiscRegIdx(int reg_name,int &idx, int &sel);
468 static inline ExtMachInst
469 makeExtMI(MachInst inst, const uint64_t &pc) {
471 ExtMachInst ext_inst = inst;
473 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
477 return ExtMachInst(inst);
481 static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
482 panic("register classification not implemented");
483 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
486 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
487 panic("register classification not implemented");
488 return (reg >= 9 && reg <= 15);
491 static inline bool isCallerSaveFloatRegister(unsigned int reg) {
492 panic("register classification not implemented");
496 static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
497 panic("register classification not implemented");
501 static inline Addr alignAddress(const Addr &addr,
502 unsigned int nbytes) {
503 return (addr & ~(nbytes - 1));
506 // Instruction address compression hooks
507 static inline Addr realPCToFetchPC(const Addr &addr) {
511 static inline Addr fetchPCToRealPC(const Addr &addr) {
515 // the size of "fetched" instructions (not necessarily the size
516 // of real instructions for PISA)
517 static inline size_t fetchInstSize() {
518 return sizeof(MachInst);
521 static inline MachInst makeRegisterCopy(int dest, int src) {
522 panic("makeRegisterCopy not implemented");
526 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
528 // check for error condition. SPARC syscall convention is to
529 // indicate success/failure in reg the carry bit of the ccr
530 // and put the return value itself in the standard return value reg ().
531 if (return_value.successful()) {
533 //regs->miscRegFile.ccrFields.iccFields.c = 0;
534 regs->intRegFile[ReturnValueReg] = return_value.value();
536 // got an error, return details
537 //regs->miscRegFile.ccrFields.iccFields.c = 1;
538 regs->intRegFile[ReturnValueReg] = -return_value.value();
542 // Machine operations
544 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
547 void restoreMachineReg(RegFile ®s, const AnyReg ®,
551 static void serializeSpecialRegs(const Serializable::Proxy &proxy,
552 const RegFile ®s);
554 static void unserializeSpecialRegs(const IniFile *db,
555 const std::string &category,
561 * Function to insure ISA semantics about 0 registers.
562 * @param xc The execution context.
565 void zeroRegisters(XC *xc);
567 const Addr MaxAddr = (Addr)-1;
571 //typedef TheISA::InternalProcReg InternalProcReg;
572 //const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
573 //const int NumInterruptLevels = TheISA::NumInterruptLevels;
575 #include "arch/mips/mips34k.hh"
578 using namespace MipsISA;
580 #endif // __ARCH_MIPS_ISA_TRAITS_HH__