arch/sparc/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
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   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
  30 #define __ARCH_SPARC_ISA_TRAITS_HH__
  31
  32 #include "base/misc.hh"
  33 #include "config/full_system.hh"
  34 #include "sim/host.hh"
  35
  36 class ExecContext;
  37 class FastCPU;
  38 //class FullCPU;
  39 class Checkpoint;
  40
  41 class StaticInst;
  42 class StaticInstPtr;
  43
  44 namespace BigEndianGuest {}
  45
  46 #if !FULL_SYSTEM
  47 class SyscallReturn
  48 {
  49   public:
  50     template <class T>
  51     SyscallReturn(T v, bool s)
  52     {
  53         retval = (uint64_t)v;
  54         success = s;
  55     }
  56
  57     template <class T>
  58     SyscallReturn(T v)
  59     {
  60         success = (v >= 0);
  61         retval = (uint64_t)v;
  62     }
  63
  64     ~SyscallReturn() {}
  65
  66     SyscallReturn& operator=(const SyscallReturn& s)
  67     {
  68         retval = s.retval;
  69         success = s.success;
  70         return *this;
  71     }
  72
  73     bool successful() { return success; }
  74     uint64_t value() { return retval; }
  75
  76     private:
  77     uint64_t retval;
  78     bool success;
  79 };
  80
  81 #endif
  82
  83
  84 namespace SparcISA
  85 {
  86
  87     // These enumerate all the registers for dependence tracking.
  88     enum DependenceTags {
  89         // 0..31 are the integer regs 0..31
  90         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
  91         FP_Base_DepTag = 32,
  92         Ctrl_Base_DepTag = 96,
  93         //XXX These are here solely to get compilation and won't work
  94         Fpcr_DepTag = 0,
  95         Uniq_DepTag = 0
  96     };
  97
  98     //This makes sure the big endian versions of certain functions are used.
  99     using namespace BigEndianGuest;
 100
 101     typedef uint32_t MachInst;
 102     typedef uint64_t ExtMachInst;
 103
 104     const int NumIntRegs = 32;
 105     const int NumFloatRegs = 64;
 106     const int NumMiscRegs = 32;
 107
 108     // semantically meaningful register indices
 109     const int ZeroReg = 0;      // architecturally meaningful
 110     // the rest of these depend on the ABI
 111     const int StackPointerReg = 14;
 112     const int ReturnAddressReg = 31; // post call, precall is 15
 113     const int ReturnValueReg = 8; // Post return, 24 is pre-return.
 114     const int FramePointerReg = 30;
 115     const int ArgumentReg0 = 8;
 116     const int ArgumentReg1 = 9;
 117     const int ArgumentReg2 = 10;
 118     const int ArgumentReg3 = 11;
 119     const int ArgumentReg4 = 12;
 120     const int ArgumentReg5 = 13;
 121     // Some OS syscall use a second register (o1) to return a second value
 122     const int SyscallPseudoReturnReg = ArgumentReg1;
 123
 124     //XXX These numbers are bogus
 125     const int MaxInstSrcRegs = 8;
 126     const int MaxInstDestRegs = 9;
 127
 128     typedef uint64_t IntReg;
 129
 130     // control register file contents
 131     typedef uint64_t MiscReg;
 132
 133     typedef double FloatReg;
 134     typedef uint64_t FloatRegBits;
 135
 136     //8K. This value is implmentation specific; and should probably
 137     //be somewhere else.
 138     const int LogVMPageSize = 13;
 139     const int VMPageSize = (1 << LogVMPageSize);
 140
 141     //Why does both the previous set of constants and this one exist?
 142     const int PageShift = 13;
 143     const int PageBytes = ULL(1) << PageShift;
 144
 145     const int BranchPredAddrShiftAmt = 2;
 146
 147     const int MachineBytes = 8;
 148     const int WordBytes = 4;
 149     const int HalfwordBytes = 2;
 150     const int ByteBytes = 1;
 151
 152     void serialize(std::ostream & os);
 153
 154     void unserialize(Checkpoint *cp, const std::string &section);
 155
 156     StaticInstPtr decodeInst(ExtMachInst);
 157
 158     // return a no-op instruction... used for instruction fetch faults
 159     extern const MachInst NoopMachInst;
 160 }
 161
 162 #include "arch/sparc/regfile.hh"
 163
 164 namespace SparcISA
 165 {
 166
 167 #if !FULL_SYSTEM
 168     static inline void setSyscallReturn(SyscallReturn return_value,
 169             RegFile *regs)
 170     {
 171         // check for error condition.  SPARC syscall convention is to
 172         // indicate success/failure in reg the carry bit of the ccr
 173         // and put the return value itself in the standard return value reg ().
 174         if (return_value.successful()) {
 175             // no error
 176             regs->setMiscReg(MISCREG_CCR_XCC_C, 0);
 177             regs->setIntReg(ReturnValueReg, return_value.value());
 178         } else {
 179             // got an error, return details
 180             regs->setMiscReg(MISCREG_CCR_XCC_C, 1);
 181             regs->setIntReg(ReturnValueReg, return_value.value());
 182         }
 183     }
 184 #endif
 185 };
 186
 187 #endif // __ARCH_SPARC_ISA_TRAITS_HH__